JP2010251572A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device of a charge-trap flash structure which makes a memory cell into a high integration degree. <P>SOLUTION: In the semiconductor storage device 50, a plurality of opening parts 5 where an element separation layer 2, a source electrode 3a, a source electrode 3b, a drain electrode 4a and a drain electrode 4b are etched and opened in pillar shapes are separately arranged on a first main face (surface) of a semiconductor substrate layer 1a as a ground line SUBL. A semiconductor substrate layer 1b, a laminated film 6 and a gate electrode 7 are buried in the opening part 5. The semiconductor substrate layer 1b is arranged on an inner side of the opening part 5 so that it is brought into contact with the semiconductor substrate layer 1a. The laminated film 6 formed of a tunnel oxide film, a charge accumulation film and a current interruption film is arranged on an inner side of the semiconductor substrate layer 1b. A gate electrode 7 is buried on an inner side of the laminated film 6. A memory transistor where a plurality of source layers 8 and drain layers 9 are arranged in the semiconductor substrate layer 1b in a vertical direction, and a channel is disposed in the vertical direction is laminated and formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  An electrically writable and erasable nonvolatile semiconductor memory device such as a flash memory is widely adopted as a large-capacity data storage medium such as a digital camera, a mobile terminal, a portable audio device, or a personal computer (PC). Typical non-volatile memory cell transistors used in flash memory include a stacked gate structure composed of a floating gate (FG) and a control gate (CG), and a silicon nitride film as a charge storage film. There is a charge trap type flash (CTF; also called Charge Trap Flash) structure to be used. In recent years, with the progress of miniaturization and high integration of semiconductor elements, the distance between the gates of the memory cell transistors is reduced in the flash memory having the stacked gate structure, and the capacitive coupling between the floating gates (FG) of adjacent cells. This makes it easier for malfunctions to occur. For this reason, a memory cell transistor having a charge trap type flash structure in which capacitive coupling hardly occurs has been developed (see, for example, Patent Document 1).

  In order to highly integrate a memory cell having a charge trap type flash structure described in Patent Document 1 or the like, it is necessary to miniaturize the memory cell transistor in the planar direction. However, miniaturization in the planar direction has a problem that a physical limit is generated due to a limit of lithography. Further, when the memory cell is miniaturized, there is a problem that the characteristics of the memory cell transistor deteriorate and the desired characteristics cannot be maintained.

JP 2003-78043 A

  The present invention provides a non-volatile semiconductor memory device having a charge trap type flash structure in which memory cells can be highly integrated.

  A nonvolatile semiconductor memory device of one embodiment of the present invention includes a substrate, a columnar control electrode connected to a word line and formed perpendicular to the substrate, and a current blocking film formed around the control electrode A charge storage film formed around the current blocking film, a tunnel oxide film formed around the charge storage film, a semiconductor substrate layer formed around the tunnel oxide film, and a bit line Connected to the semiconductor substrate layer, connected to the drain electrode formed in the horizontal direction with respect to the substrate, and connected to the source line, connected to the semiconductor substrate layer, formed in the horizontal direction with respect to the substrate A memory cell transistor in which the drain electrode and the source electrode are stacked via an insulating film in a direction perpendicular to the substrate, and the memory cell transistor includes the source electrode In a direction perpendicular to the plate, characterized by comprising a memory cell array which are laminated so as to share the control electrode.

  Furthermore, a nonvolatile semiconductor memory device according to another aspect of the present invention includes a substrate, a columnar control electrode connected to a word line and formed perpendicular to the substrate, and a current formed around the control electrode. A blocking film; a charge storage film formed around the current blocking film; a tunnel oxide film formed around the charge storage film; a semiconductor substrate layer formed around the tunnel oxide film; and a bit A drain electrode connected to a line, connected to the semiconductor substrate layer and formed in a horizontal direction with respect to the substrate; a drain layer connected to the drain electrode; provided on the semiconductor substrate layer; and a source line A source electrode connected to the semiconductor substrate layer and formed in a horizontal direction with respect to the substrate; and a source layer connected to the source electrode and provided on the semiconductor substrate layer, The rain electrode and the source electrode are stacked in a direction perpendicular to the substrate via an insulating film, and the memory cell transistor shares the control electrode in the direction perpendicular to the substrate. And a memory cell array formed in a stacked manner.

  According to the present invention, it is possible to provide a non-volatile semiconductor memory device having a charge trap type flash structure in which memory cells can be highly integrated.

1 is an overhead view showing a structure of a nonvolatile semiconductor memory device according to Example 1 of the invention. Sectional drawing in alignment with the AA of FIG. The expanded sectional view of the area | region A of FIG. FIG. 4A is a plan view showing a nonvolatile semiconductor memory device according to Example 1 of the invention, FIG. 4A is a diagram showing a source electrode portion, and FIG. 4B is a diagram showing a drain electrode portion. 1 is an equivalent circuit diagram of a nonvolatile semiconductor memory device according to Example 1 of the invention. FIG. 3 is a diagram for explaining the operation of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 3 is a diagram for explaining the operation of a selected memory cell transistor at the time of writing in the nonvolatile semiconductor memory device according to the first embodiment of the invention. 3 is a diagram for explaining the operation of a selected memory cell transistor during erasure of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the non-volatile semiconductor memory device which concerns on Example 1 of this invention. Sectional drawing which shows the non-volatile semiconductor memory device which concerns on Example 2 of this invention. Sectional drawing which shows the non-volatile semiconductor memory device which concerns on Example 3 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a nonvolatile semiconductor memory device according to Example 1 of the invention will be described with reference to the drawings. 1 is a bird's-eye view showing the structure of the nonvolatile semiconductor memory device, FIG. 2 is a sectional view taken along line AA in FIG. 1, FIG. 3 is an enlarged sectional view of region A in FIG. FIG. 4A is a diagram showing a source electrode portion, and FIG. 4B is a diagram showing a drain electrode portion. In this embodiment, a NOR type flash memory is stacked on a semiconductor substrate layer to make a memory cell three-dimensional.

As shown in FIG. 1, the semiconductor memory device 50 has a charge trap type flash (CTF; also called Charge Trap Flash) structure using a silicon nitride film as a charge storage layer, and memory cells are stacked. This is a three-dimensional NOR flash memory. The charge trap flash (CTF) is sometimes called MONOS (Metal Oxide Nitride Oxide Semiconductor), SONOS (polysilicon oxide nitride oxide silicon), or TANOS (silicon oxide SiN Al ₂ O ₃ TaN). Here, illustration and description of an insulating film provided around the memory cell transistors and separating the memory cell transistors are omitted.

  A plurality of gates as gate electrodes are provided on the ground line SUBL so as to be separated from each other in a direction perpendicular to a substrate (not shown). The gate Gate is connected to the word line WL. A plurality of source lines SL are provided apart from each other in the horizontal direction with respect to a substrate (not shown) and the ground line SUBL (left side in the figure). A plurality of bit lines BL are provided apart from each other in the horizontal direction with respect to a substrate (not shown) and the ground line SUBL (right side in the figure).

  As shown in FIG. 2, in the semiconductor memory device 50, a semiconductor substrate layer 1a as a ground line SUBL is provided on a substrate (not shown) via an insulating film, for example. On the first main surface (front surface) of the semiconductor substrate layer 1a, openings 5 in which the element isolation layer 2, the source electrode 3a, the source electrode 3b, the drain electrode 4a, and the drain electrode 4b are opened in a columnar shape are separated from each other. A plurality of them are provided.

  In the opening 5, a semiconductor substrate layer 1 b, a laminated film 6, and a gate electrode (Gate) 7 are embedded. Inside the opening 5, the semiconductor substrate layer 1b is provided in contact with the upper surface of the semiconductor substrate layer 1a. A laminated film 6 is provided inside the semiconductor substrate layer 1 b facing the element isolation layer 2. A gate electrode (Gate) 7 is embedded inside the stacked film 6 facing the semiconductor substrate layer 1b.

  As shown in FIG. 3, the laminated film 6 includes a tunnel oxide film 21, a charge storage film 22, and a current blocking film 23. The tunnel oxide film 21 is provided between the semiconductor substrate layer 1 b and the charge storage film 22. The charge storage film 22 is provided between the tunnel oxide film 21 and the current blocking film 23 and has a function of holding charges. The current blocking film 23 is provided between the charge storage film 22 and the gate electrode (Gate) 7.

  The source electrode 3a, the drain electrode 4a, the source electrode 3b, and the drain electrode 4b are separated from each other by the element isolation layer 2, are in contact with the semiconductor substrate layer 1b, and are stacked. The source layer 8 uses the impurities in the source electrodes 3a and 3b as a diffusion source, is connected to the source electrode 3a or the source electrode 3b, and is provided on the semiconductor substrate layer 1b. The drain layer 9 uses the impurities in the drain electrodes 4a and 4b as a diffusion source, is connected to the drain electrode 4a or the drain electrode 4b, and is provided on the semiconductor substrate layer 1b.

  The source electrode 3a is connected to the source line SL via the via 10, and the source electrode 3b is connected to the source line SL via the via 12. The drain electrode 4 a is connected to the bit line BL via the via 11, and the drain electrode 4 b is connected to the bit line BL via the via 13.

  In the source electrode portion, as shown in FIG. 4A, an opening 5 having a central portion provided in the source electrode 3 a is provided in the region of the source electrode 3 a and the element isolation layer 2. The source layer 8 is provided between the source electrode 3a and the laminated film 6, and is not provided between the element isolation layer 2 and the laminated film 6 (the semiconductor substrate layer 1b remains). That is, impurities in the source electrode 3 a are diffused into the semiconductor substrate layer 1 b between the source electrode 3 a and the stacked film 6, so that the semiconductor substrate layer 1 b becomes the source layer 8.

  In the drain electrode portion, as shown in FIG. 4B, an opening 5 having a central portion provided in the drain electrode 4a is provided in the region of the drain electrode 4a and the element isolation layer 2. The drain layer 9 is provided between the drain electrode 4a and the laminated film 6, and is not provided between the element isolation layer 2 and the laminated film 6 (the semiconductor substrate layer 1b remains). That is, impurities in the drain electrode 4 a are diffused into the semiconductor substrate layer 1 b between the drain electrode 4 a and the laminated film 6, so that the semiconductor substrate layer 1 b becomes the drain layer 9.

  As a result, a plurality of source layers 8 and drain layers 9 are alternately formed in the vertical direction, and a channel is formed in the semiconductor substrate layer 1 b between the source layer 8 and the drain layer 9. The semiconductor substrate layer 1b between the element isolation layer 2 and the laminated film 6 functions as a substrate and is connected to the semiconductor substrate layer 1a. As a result, the memory cell transistors in the vertical direction are stacked in the direction perpendicular to the substrate to constitute a memory cell array, and the first to fourth memory cell arrays are formed apart from each other in the horizontal direction.

  Here, the horizontal sectional shape of the opening 5 is round (that is, the opening 5 is a cylinder), but may be rectangular (that is, the opening 5 is a prism). Further, although the source layer 8 and the drain layer 9 are formed so as to be in contact with the laminated film 6, they may be formed so as not to be in contact (the semiconductor substrate layer 1b is left).

  Next, the operation of the nonvolatile semiconductor memory device will be described with reference to FIGS. 5 is an equivalent circuit diagram of the nonvolatile semiconductor memory device, FIG. 6 is a diagram for explaining the operation of the nonvolatile semiconductor memory device, and FIG. 7 is for explaining the operation of the selected memory cell transistor at the time of writing in the nonvolatile semiconductor memory device. FIG. 8 is a diagram for explaining the operation of the selected memory cell transistor at the time of erasure of the nonvolatile semiconductor memory device. 7 and 8 are cross-sectional views of the memory cell transistor corresponding to the region B in FIG.

  As shown in FIG. 5, in the nonvolatile semiconductor memory device 50 which is a NOR type charge trap type flash, the drain is connected to the bit line BL, the source is connected to the source line SL, the gate is connected to the word line WL, Memory cell transistors whose substrates are connected to a ground line SUBL (not shown) are arranged in a matrix. Memory cell transistors respectively connected to the word lines WL0 to WL5 constitute a memory cell array.

  Here, the operation will be described in the case where a memory cell transistor connected to the bit line BL3, the source line SL3, and the word line WL3 is selected as a memory cell (selected bit).

  As shown in FIG. 6, in the write operation, for example, the voltage Vwlv2 is applied to the selected word line WL3, Vblv2 is applied to the selected bit line BL3, and the selected source line SL3 and ground line SUBL are 0 ( Zero) V is set. With this setting, as shown in FIG. 7, a current flows from the drain to the source, electrons in the vicinity of the channel are activated, hot electrons are generated, and hot electrons are generated by the voltage Vwlv2 applied to the gate electrode (WL3). Is injected into the charge storage film 22 through the tunnel oxide film 21 to write information.

  In the erase operation, for example, the voltage Vwlv3 (negative voltage) is applied to the selected word line WL3, the voltage Vslv1 is applied to the selected source line SL3, the voltage Vsublv1 is applied to the ground line SUBL, and the selected bit line BL3 is set to an open state. With this setting, as shown in FIG. 8, electrons held in the charge storage film 22 are extracted from the charge storage film 22 through the tunnel oxide film 21 to the source side (tunnel current).

  In the read operation, for example, the voltage Vwlv1 is applied to the selected word line WL3, Vblv1 is applied to the selected bit line BL3, and the selected source line SL3 and the ground line SUBL are set to 0 (zero) V. . With this setting, the presence / absence of current flowing between the source and drain is read as data.

  Next, a method for manufacturing the nonvolatile semiconductor memory device will be described with reference to FIGS. 9A to 16B are diagrams showing a manufacturing process of the nonvolatile semiconductor memory device, FIGS. 9A to 16A are plan views, and FIGS. 9B to 16B are cross-sectional views. 9B to 16B are cross-sectional views taken along line BB shown in FIG. 9A. Here, a memory cell array is provided in which memory cell transistors are stacked in three stages in a direction perpendicular to the substrate.

  As shown in FIG. 9B, for example, the element isolation layer 2, the source electrode 31, the element isolation layer 2, the drain electrode 41, and the element isolation layer 2 on the first main surface (surface) of the P-type semiconductor substrate layer 1a. The source electrode 32, the element isolation layer 2, the drain electrode 42, the element isolation layer 2, the source electrode 33, the element isolation layer 2, the drain electrode 43, and the element isolation layer 2 are stacked to form a stacked film 90. The semiconductor substrate layer 1a is a P-type polycrystalline silicon film formed by, for example, a CVD method.

  The laminated film 90 is arranged in a stripe shape as shown in FIG. 9A, and the element isolation layer 2 is provided therebetween.

  Here, for the source electrode 31, the drain electrode 41, the source electrode 32, the drain electrode 42, the source electrode 33, and the drain electrode 43, for example, a polycrystalline silicon film doped with an N-type impurity at a high concentration is used. Alternatively, an amorphous silicon film or a polycide film doped with an N-type impurity at a high concentration may be used instead.

  Next, as shown in FIG. 10, using a well-known lithography method with a resist film (not shown) as a mask, for example, the element isolation layer 2, the drain electrode 43, the element isolation layer 2, and the source electrode 33 stacked by the RIE method. The element isolation layer 2, the drain electrode 42, the element isolation layer 2, the source electrode 32, the element isolation layer 2, the drain electrode 41, the element isolation layer 2, the source electrode 31, and the element isolation layer 2 are etched to obtain a semiconductor substrate layer. A cylindrical opening 5 is formed on 1a. In the opening 5 shown in FIG. 10A, the center position is provided on the drain electrode / source electrode side, the upper end is only the element isolation layer 2, and the drain electrode / source electrode is not provided.

  Subsequently, as shown in FIG. 11, for example, a P-type semiconductor substrate layer 1 b is formed on the opening 5 and the semiconductor substrate layer 1 a. At this time, the native oxide formed on the side surfaces (opening 5 side) of the source electrode 31, the drain electrode 41, the source electrode 32, the drain electrode 42, the source electrode 33, and the drain electrode 43 is removed by etching. After that, it is preferable to form the semiconductor substrate layer 1b. By removing the native oxide by etching, the connection state between the semiconductor substrate layer 1a and the semiconductor substrate layer 1b is improved. The semiconductor substrate layer 1b is a P-type polycrystalline silicon film formed by, for example, a CVD method.

  Then, as shown in FIG. 12, a tunnel oxide film 21, a charge storage film 22, and a current blocking film 23 are stacked on the semiconductor substrate layer 1b of the opening 5 (stacked film 6 in the figure).

Here, as the tunnel oxide film 21, for example, a SiO ₂ film (silicon oxide film) having a thickness in the range of 0.5 to 10 nm is used. Instead, SiO ₂ having the same thickness in terms of EOT (equivalent oxide thickness) is used. A laminated film of ₂ films / SiN film / SiO _2, a laminated film of SiO ₂ film / high dielectric constant insulating film / SiO ₂ film, or a laminated film of high dielectric constant insulating film / SiO ₂ film may be used. For the charge storage layer 22, for example, a SiN film (silicon nitride film) having a thickness in the range of 3 to 50 nm is used.

For example, an Al ₂ O ₃ film (alumina film) having a thickness in the range of 5 to 30 nm is used as the current blocking film 23 as the block film. Instead, an MgO film having a higher dielectric constant than the silicon oxide film, SrO High dielectric constant insulation such as a film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, Y ₂ O ₃ film, ZrSiO film, HfSiO film, or LaAlO film A film or a laminated film thereof (including a laminated film of an Al ₂ O ₃ film (alumina film)) may also be used.

  Next, as shown in FIG. 13, a gate electrode (Gate) 7 is formed on the current blocking film 23 in the opening 5 so as to fill the opening 5. Here, the semiconductor substrate layer 1b, the tunnel oxide film 21, the charge storage film 22, the current blocking film 23, and the gate electrode (Gate) 7 are sequentially formed. However, the semiconductor substrate layer 1b, the tunnel oxide film 21, and the charge storage film are formed. After the film 22, the current blocking film 23, and the gate electrode (Gate) 7 are continuously formed, the semiconductor substrate layer is used until the surface of the element isolation layer 2 is exposed by using, for example, a CMP (chemical mechanical polishing) method. 1b, the tunnel oxide film 21, the charge storage film 22, the current blocking film 23, and the gate electrode (Gate) 7 may be flatly polished.

  After forming the gate electrode (Gate) 7, high-temperature heat treatment is performed to diffuse impurities in the source electrode 31, the drain electrode 41, the source electrode 32, the drain electrode 42, the source electrode 33, and the drain electrode 43, and the semiconductor substrate layer 1b Then, for example, a source layer 8 and a drain layer 9 having high N-type impurities are formed.

  Subsequently, as illustrated in FIG. 14, the element isolation layer 2, the drain electrode 41, the element isolation layer 2, the source electrode 32, the element isolation layer 2, the drain electrode 42, and the element isolation on the source electrode 31 that is separated from the opening 5. The layer 2, the source electrode 33, the element isolation layer 2, the drain electrode 43, and the element isolation layer 2 are selectively removed by etching, and an insulating film 51 as an interlayer insulating film is embedded in the etched away region.

  Then, as shown in FIG. 15, the element isolation layer 2, the source electrode 32, the element isolation layer 2, the drain electrode 42, the element isolation layer 2, the source electrode 33, and the element isolation layer on the drain electrode 41 spaced apart from the opening 5. 2, the drain electrode 43 and the element isolation layer 2 are selectively removed by etching, and an insulating film 51 as an interlayer insulating film is embedded in the etched area. Similarly, on the source electrode 32 spaced from the opening 5, on the drain electrode 42 separated from the opening 5, on the source electrode 33 separated from the opening 5, and on the drain electrode 43 separated from the opening 5. An insulating film 51 as an insulating film is embedded.

  Next, as shown in FIG. 16, the interlayer insulating film 51 is selectively etched to form an opening 52 on the source electrode 31, an opening 53 on the drain electrode 41, an opening 54 on the source electrode 32, and a drain. An opening 55 is formed on the electrode 42, an opening 56 is formed on the source electrode 33, and an opening 57 is formed on the drain electrode 43. After the openings 52 to 57 are formed, vias are embedded in the openings 52 to 57, respectively. In addition, about the process after this, since a well-known technique is used, illustration and description are abbreviate | omitted.

  As described above, in the nonvolatile semiconductor memory device of this embodiment, the element isolation layer 2, the source electrode 3a, the source electrode 3b, the drain are formed on the first main surface (surface) of the semiconductor substrate layer 1a as the ground line SUBL. A plurality of openings 5 in which the electrodes 4a and the drain electrodes 4b are etched and opened in a columnar shape are provided apart from each other. A semiconductor substrate layer 1b, a laminated film 6, and a gate electrode (Gate) 7 are embedded in the opening 5, and the semiconductor substrate layer 1b is provided inside the opening 5 so as to be in contact with the semiconductor substrate layer 1a. A laminated film 6 including a tunnel oxide film 21, a charge storage film 22, and a current blocking film 23 is provided inside the semiconductor substrate layer 1b. A gate electrode (Gate) 7 is embedded inside the laminated film 6. A plurality of source layers 8 and drain layers 9 are provided in the semiconductor substrate layer 1b in the vertical direction. The source layer 8 is formed using impurities in the source electrode as a diffusion source, and the drain layer 9 is formed using impurities in the drain electrode as a diffusion source. In the opening 5, a memory cell transistor in which a source layer 8, a channel, and a drain layer 9 are formed in a vertical direction is stacked.

  Therefore, it is possible to provide the nonvolatile semiconductor memory device 50 which is a three-dimensional NOR type flash memory having a charge trap type flash structure and a high degree of integration that does not depend on miniaturization in the planar direction. In addition, since the degree of integration can be increased without miniaturizing the memory cell transistor, desired characteristics can be maintained without deterioration of the characteristics of the memory cell transistor.

  In this embodiment, the center position of the opening 5 is set on the source electrode and drain electrode side, but the present invention is not necessarily limited to this. For example, the center position of the opening 5 may be set on the element isolation region 2 side. Further, an opening 5 having a center position in the element isolation region may be formed between the source electrodes and between the drain electrodes. Furthermore, the semiconductor substrate layer 1a may be replaced with a semiconductor substrate.

  Next, a non-volatile semiconductor memory device according to Example 2 of the present invention will be described with reference to the drawings. FIG. 17 is a cross-sectional view showing a nonvolatile semiconductor memory device. In this embodiment, the source layer of the memory cell transistor is omitted.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 17, the semiconductor memory device 60 is a three-dimensional NOR flash memory having a charge trap flash structure using a silicon nitride film as a charge storage layer and having memory cells stacked.

  In the semiconductor memory device 60, a semiconductor substrate layer 1a as a ground line SUBL is provided on a substrate (not shown) via an insulating film, for example. On the first main surface (front surface) of the semiconductor substrate layer 1a, openings 5 formed by columnar etching openings of the element isolation layer 2, the source electrode 3aa, the source electrode 3bb, the drain electrode 4a, and the drain electrode 4b are separated from each other. A plurality of them are provided.

  The source electrode 3aa, the drain electrode 4a, the source electrode 3bb, and the drain electrode 4b are separated from each other by the element isolation layer 2, are in contact with the semiconductor substrate layer 1b, and are stacked. The source electrode 3aa and the source electrode 3bb are electrically connected to the semiconductor substrate layer 1b. Although the metal silicide film is used for the source electrode 3aa and the source electrode 3bb, a refractory metal film or the like may be used instead.

  As described above, in the nonvolatile semiconductor memory device of this embodiment, the element isolation layer 2, the source electrode 3aa, the source electrode 3bb, the drain are formed on the first main surface (surface) of the semiconductor substrate layer 1a as the ground line SUBL. A plurality of openings 5 in which the electrodes 4a and the drain electrodes 4b are etched and opened in a columnar shape are provided apart from each other. A semiconductor substrate layer 1b, a laminated film 6, and a gate electrode (Gate) 7 are embedded in the opening 5, and the semiconductor substrate layer 1b is provided inside the opening 5 so as to be in contact with the semiconductor substrate layer 1a. A laminated film 6 including a tunnel oxide film 21, a charge storage film 22, and a current blocking film 23 is provided inside the semiconductor substrate layer 1b. A gate electrode (Gate) 7 is embedded inside the laminated film 6. A plurality of drain layers 9 are provided in the semiconductor substrate layer 1b in the vertical direction. The drain layer 9 is formed using impurities in the drain electrode as a diffusion source. In the opening 5, memory cell transistors having channels formed in the vertical direction are stacked.

  Therefore, it is possible to provide a nonvolatile semiconductor memory device 60 that is a three-dimensional NOR type flash memory having a charge trap type flash structure and a high degree of integration that does not depend on miniaturization in the planar direction. In addition, since the degree of integration can be increased without miniaturizing the memory cell transistor, desired characteristics can be maintained without deterioration of the characteristics of the memory cell transistor.

  Further, by omitting the source layer of the memory cell transistor, the cutoff characteristic of the memory cell transistor is improved while maintaining the hot carrier injection efficiency, and further miniaturization is possible.

  Next, a non-volatile semiconductor memory device according to Example 3 of the present invention will be described with reference to the drawings. FIG. 18 is a cross-sectional view showing a nonvolatile semiconductor memory device. In this embodiment, the source layer and the drain layer of the memory cell transistor are omitted.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 18, the semiconductor memory device 70 has a charge trap type flash structure using a silicon nitride film as a charge storage layer, and is a three-dimensional NOR type flash memory in which memory cells are stacked.

  In the semiconductor memory device 70, a semiconductor substrate layer 1a as a ground line SUBL is provided on a substrate (not shown) via an insulating film, for example. On the first main surface (front surface) of the semiconductor substrate layer 1a, the opening 5 formed by etching the element isolation layer 2, the source electrode 3aa, the source electrode 3bb, the drain electrode 4aa, and the drain electrode 4bb in a columnar shape is separated from each other. A plurality of them are provided.

  The source electrode 3aa, the drain electrode 4aa, the source electrode 3bb, and the drain electrode 4bb are separated from each other by the element isolation layer 2, are in contact with the semiconductor substrate layer 1b, and are stacked. The source electrode 3aa and the source electrode 3bb are electrically connected to the semiconductor substrate layer 1b. The drain electrode 4aa and the drain electrode 4bb are electrically connected to the semiconductor substrate layer 1b. Although the source electrodes 3aa and 3bb and the drain electrodes 4aa and 4bb use metal silicide films, refractory metal films or the like may be used instead.

  As described above, in the nonvolatile semiconductor memory device of this embodiment, the element isolation layer 2, the source electrode 3aa, the source electrode 3bb, the drain are formed on the first main surface (surface) of the semiconductor substrate layer 1a as the ground line SUBL. A plurality of openings 5 formed by opening the electrodes 4aa and the drain electrodes 4bb in a columnar shape are provided apart from each other. A semiconductor substrate layer 1b, a laminated film 6, and a gate electrode (Gate) 7 are embedded in the opening 5, and the semiconductor substrate layer 1b is provided inside the opening 5 so as to be in contact with the semiconductor substrate layer 1a. A laminated film 6 including a tunnel oxide film 21, a charge storage film 22, and a current blocking film 23 is provided inside the semiconductor substrate layer 1b. A gate electrode (Gate) 7 is embedded inside the laminated film 6. A plurality of drain layers 9 are provided in the semiconductor substrate layer 1b in the vertical direction. In the opening 5, memory cell transistors having channels formed in the vertical direction are stacked.

  Therefore, it is possible to provide a nonvolatile semiconductor memory device 70 that is a three-dimensional NOR flash memory having a charge trap type flash structure and a high degree of integration that does not depend on miniaturization in the planar direction. In addition, since the degree of integration can be increased without miniaturizing the memory cell transistor, desired characteristics can be maintained without deterioration of the characteristics of the memory cell transistor.

  Further, by omitting the source layer and the drain layer of the memory cell transistor, the cutoff characteristic of the memory cell transistor is improved, and further miniaturization is possible.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiments, the present invention is applied to a NOR flash memory having a charge trap flash structure, but the present invention can also be applied to an AND flash memory having a charge trap flash structure. In an AND type flash memory having a charge trap type flash structure, it is preferable to provide a drain side select transistor on the bit line side and a source side select transistor on the source line side.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A substrate, a columnar control electrode connected to a word line and formed perpendicular to the substrate, a current blocking film formed around the control electrode, and a periphery of the current blocking film A charge storage film formed; a tunnel oxide film formed around the charge storage film; a semiconductor substrate layer formed around the tunnel oxide film; and a bit line connected to the semiconductor substrate layer A drain electrode formed in a horizontal direction with respect to the substrate; connected to the drain electrode; and an impurity in the drain electrode as a diffusion source; a drain layer provided in the semiconductor substrate layer; and a source line A source electrode connected to the semiconductor substrate layer and formed in a horizontal direction with respect to the substrate; connected to the source electrode; and an impurity in the source electrode as a diffusion source, and the semiconductor A memory cell transistor having a source layer provided on a substrate layer, wherein the drain electrode and the source electrode are stacked via an insulating film in a direction perpendicular to the substrate, and the memory cell transistor is the substrate And a memory cell array stacked so as to share the control electrode in a direction perpendicular to the non-volatile semiconductor memory device.

(Supplementary note 2) The nonvolatile semiconductor memory device according to supplementary note 1, wherein the control electrode has a cylindrical shape or a prismatic shape.

(Supplementary Note 3) The nonvolatile semiconductor memory device according to Supplementary Note 1 or 2, wherein the nonvolatile semiconductor memory device is a NOR flash memory.

1a, 1b Semiconductor substrate layer 2 Element isolation layers 3a, 3b, 3aa, 3bb, 31-33 Source electrodes 4a, 4b, 4aa, 4bb, 41-43 Drain electrodes 5, 52-57 Openings 6, 90 Laminated film 7 Gate Electrode (Gate)
8 Source layer 9 Drain layer 10-13 Via 21 Tunnel oxide film 22 Charge storage film 23 Current blocking film 50, 60, 70 Non-volatile semiconductor device 51 Insulating film BL, BL0-BL6 Bit line Gate Gate SL, SL0-SL6 Source line SUBL Ground line WL, WL0-WL5 Word line

Claims (5)

A substrate,
A columnar control electrode connected to a word line and formed perpendicular to the substrate; a current blocking film formed around the control electrode; and a charge storage film formed around the current blocking film; A tunnel oxide film formed around the charge storage film; a semiconductor substrate layer formed around the tunnel oxide film; a bit line connected to the semiconductor substrate layer; and A drain electrode formed in a horizontal direction; and a source electrode connected to a source line, connected to the semiconductor substrate layer, and formed in a horizontal direction with respect to the substrate. The drain electrode and the source electrode are A memory cell transistor formed by stacking an insulating film in a direction perpendicular to the substrate;
A memory cell array in which the memory cell transistors are stacked so as to share the control electrode in a direction perpendicular to the substrate;
A non-volatile semiconductor memory device comprising:   2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell transistor is provided with a drain layer in the semiconductor substrate layer using an impurity in the drain electrode as a diffusion source. A substrate,
A columnar control electrode connected to a word line and formed perpendicular to the substrate; a current blocking film formed around the control electrode; and a charge storage film formed around the current blocking film; A tunnel oxide film formed around the charge storage film; a semiconductor substrate layer formed around the tunnel oxide film; a bit line connected to the semiconductor substrate layer; and A drain electrode formed in a horizontal direction, a drain layer connected to the drain electrode and provided in the semiconductor substrate layer, connected to a source line, connected to the semiconductor substrate layer, and horizontal to the substrate A source electrode connected to the source electrode and provided on the semiconductor substrate layer, the drain electrode and the source electrode being perpendicular to the substrate A memory cell transistor formed by lamination via a Enmaku,
A memory cell array in which the memory cell transistors are stacked so as to share the control electrode in a direction perpendicular to the substrate;
A non-volatile semiconductor memory device comprising:   4. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of the memory cell arrays are provided on the substrate, and transistor regions are separated from each other by an insulating film.   The nonvolatile semiconductor memory device according to claim 4, wherein the semiconductor substrate layers of the plurality of memory cell arrays are connected to a ground line.

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