JP2009289950A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress intercell interference effects of a charge-trap flash. <P>SOLUTION: In a semiconductor memory device 70, each STI (shallow trench isolation) 2 is buried in a first main face (surface) of a semiconductor substrate 1, which is P-type silicon in a word-line direction. A tunnel oxide film 3, a charge accumulation layer 4, a current cutoff layer 5 are laminatedly formed on the first main face (surface) of the semiconductor substrate between the STIs (shallow trench isolation) 2. Each end part of the charge accumulating layer 4 is internally provided by an interval ΔW1, between the end of a channel width W<SB>CH</SB>and the end of the charge accumulation layer from each end part of the channel width W<SB>CH</SB>. A control electrode 7 as a word line WL3 is provided on each current cutoff layer 5 and each insulating film 6. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device.

  An electrically writable and erasable nonvolatile semiconductor memory device such as a flash memory is widely adopted as a large-capacity data storage medium such as a digital camera, a mobile terminal, a portable audio device, or a personal computer (PC). Typical non-volatile memory cell transistors used in flash memory include a stacked gate structure composed of a floating gate (FG) and a control gate (CG), and a silicon nitride film as a charge storage film. There is a charge trap type flash (CTF; also called Charge Trap Flash) structure to be used. In recent years, with the progress of miniaturization and high integration of semiconductor elements, the distance between the gates of the memory cell transistors is reduced in the flash memory having the stacked gate structure, and the capacitive coupling between the floating gates (FG) of adjacent cells. This makes it easier for malfunctions to occur. For this reason, a memory cell transistor having a charge trap type flash structure in which capacitive coupling hardly occurs has been developed (see, for example, Patent Document 1).

In the memory cell transistor having a charge trap type flash structure described in Patent Document 1 and the like, the thickness of the charge storage layer is as thin as several nanometers, so that compared to a stacked gate structure using a floating gate electrode film, Inter-cell interference effects can be reduced. However, even in the memory cell transistor of the charge trap type flash structure, when the inter-cell spacing is further reduced, the inter-cell interference effect is suppressed due to the capacity coupling which increases rapidly in inverse proportion to the inter-cell spacing. It becomes difficult.
JP 2003-78043 A

  The present invention provides a semiconductor memory device that can suppress the inter-cell interference effect.

  In a semiconductor memory device of one embodiment of the present invention, a semiconductor substrate, a tunnel oxide film, a charge storage layer, a current blocking layer, and a control electrode are stacked over the semiconductor substrate, and the control electrode is connected to a word line. A memory cell transistor, and a memory cell in which the memory cell transistor is cascade-connected between a bit line and a source line, and in the word line direction, the width of the charge storage layer is larger than the channel width of the memory cell transistor. It is characterized by being narrow.

  Furthermore, in a semiconductor memory device according to another aspect of the present invention, a semiconductor substrate, a tunnel oxide film, a charge storage layer, a current blocking layer, and a control electrode are stacked on the semiconductor substrate, and the control electrode is connected to a word line. And a memory cell in which the memory cell transistors are cascade-connected between a bit line and a source line, and the width of the charge storage layer in the word line direction is the channel width of the memory cell transistor The length of the charge storage layer is shorter than the length of the control electrode in the bit line direction.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor memory device which can suppress the intercell interference effect can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor memory device according to Embodiment 1 of the present invention will be described with reference to the drawings. 1A and 1B are diagrams showing a semiconductor memory device, FIG. 1A is a circuit diagram showing the semiconductor memory device, FIG. 1B is a plan view showing the semiconductor memory device, and FIG. 2 is an AA of FIG. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1B. In this embodiment, the width and length of the charge storage layer of the memory cell transistor are changed in order to reduce the inter-cell interference effect.

The semiconductor memory device 70 is provided with a plurality of memory cells such as memory cells MC1 to MC3. The plurality of memory cells constitute a memory cell block, and the plurality of memory cell blocks constitute a memory cell array. The semiconductor memory device 70 is provided with a plurality of memory cell arrays. The semiconductor memory device 70 is a NAND flash memory having a charge trap flash (CTF; also called charge trap flash) structure using a silicon nitride film as a charge storage film. The charge trap flash (CTF) is sometimes called MONOS (Metal Oxide Nitride Oxide Semiconductor), SONOS (polysilicon oxide nitride oxide silicon), or TANOS (silicon oxide SiN Al ₂ O ₃ TaN).

  In each of the memory cells MC1 to MC3, a control transistor STR is provided on the bit line BL side connected to the sense amplifier, a control transistor STR is provided on the source line SL side, and a plurality of memory transistors connected in cascade therebetween. An MTR is provided. Bit lines BL1, BL2, and BL3 and control line SGD, word WLn,..., Word WL4, word WL3, word line WL1, control line SGS, and source line SL cross each other.

  The control line SGD is connected to the gate of the control transistor STR on the bit lines BL1 to 3 side connected to the sense amplifier. The word line WLn is connected to the control gate (control gate) of the nth memory transistor MTR connected to the bit lines BL1 to BL3. The word line WL4 is connected to the control gate of the fourth memory transistor MTR connected to the bit lines BL1 to BL3. The word line WL3 is connected to the control gate of the third memory transistor MTR connected to the bit lines BL1 to BL3. The word line WL2 is connected to the control gate of the second memory transistor MTR connected to the bit lines BL1 to BL3. The word line WL1 is connected to the control gate of the first memory transistor MTR connected to the bit lines BL1 to BL3. The control line SGS is connected to the gate of the control transistor STR on the bit lines BL1 to BL3 connected to the source line SL.

  As shown in FIG. 1B, in the semiconductor memory device 70, the source line SL, the control line SGS, the word line WL1, the word line WL2, the word line WL3, the word line WL4,..., The word line WLn, the control line SGDs are spaced apart from each other in the vertical direction (in the drawing) and are arranged in parallel. Bit lines BL1 to BL3 are spaced apart from each other in the horizontal direction (in the drawing) and arranged in parallel. An element isolation region is provided between the bit lines BL to separate the bit lines BL. A source line contact SLC is provided at the intersection of the source line SL and the bit lines BL1 to BL3. A bit line contact BLC is provided on the bit line BL between the control line SGD and a sense amplifier (not shown).

  As shown in FIG. 2, in the word line direction, STI (shallow trench isolation) 2 is embedded in the first main surface (front surface) of the semiconductor substrate 1 made of P-type silicon in the semiconductor memory device 70. On the first main surface (surface) of the semiconductor substrate between STI (shallow trench isolation) 2, a tunnel oxide film 3, a charge storage layer 4, and a current blocking layer 5 are stacked. A channel layer is formed on the first main surface (front surface) of the semiconductor substrate immediately below the tunnel oxide film 3.

  Here, the tunnel oxide film 3, the charge storage layer 4, and the current blocking layer 5 are not provided on the STI (shallow trench isolation) 2 in the word line direction. That is, the charge storage layer 4 is separated between adjacent cells. The purpose is to prevent the charge storage layer 4 from being dispersed in the charge storage layer 4 by separating the charge storage layer 4 from adjacent cells.

End of the charge storage layer 4 is provided inside by a distance ΔW1 charge storage layer end and the channel width end than the end of the channel width W _CH. The relationship between the charge storage layer width W _DCL1 , the channel width W _CH , and the distance ΔW1 between the channel width end and the charge storage layer end is:
W _DCL1 = W _CH -2ΔW1 ............ Formula (1)
It is expressed. By than the end portion of the channel width W _CH provided within only the interval ΔW1 charge storage layer end and the channel width end, without narrowing the channel width, widening the only interval of the charge storage layer between the word line direction adjacent cell Therefore, the inter-cell interference effect can be reduced.

  On the STI (shallow trench isolation) 2 between the tunnel oxide film 3, the charge storage layer 4, and the current blocking layer 5, an insulating film 6 as an interlayer insulating film is provided. On the current blocking layer 5 and the insulating film 6, a control electrode 7 as the word line WL3 is provided. An insulating film 8 as an interlayer insulating film is provided on the control electrode 7. The wiring layers 9 as the bit lines BL1 to BL3 are embedded in the surface of the insulating film 8 so as to expose the surface. An insulating film 10 as a surface protective film is provided on the insulating film 8 and the wiring layer 9.

As shown in FIG. 3, in the bit line direction, the semiconductor memory device 70 includes an N ⁺ layer 11 serving as a source or drain of the memory cell transistor MTR on the first main surface (front surface) of the semiconductor substrate 1 made of P-type silicon. Is provided.

A tunnel oxide film 3, a charge storage layer 4, a current blocking layer 5, and a control electrode 7 are stacked on the first main surface (front surface) of the semiconductor substrate between the N ⁺ layers 11. Tunnel oxide film 3 is provided so as to overlap with N ⁺ layer 11. A channel layer is formed on the first main surface (front surface) of the semiconductor substrate immediately below the tunnel oxide film 3.

The end of the charge storage layer 4 is provided more inside than the end of the control electrode 7 by a distance ΔL1 between the control electrode end and the charge storage layer end. The _{relationship among the} charge storage layer length L _DCL1 , the control electrode length L _SG , and the distance _ΔL1 between the control electrode end and the charge storage layer end is:
L _DCL1 = L _SG -2ΔL1 ..... Equation (2)
It is expressed. The control electrode length L _SG is set to a half pitch. By providing the distance ΔL1 between the control electrode end and the charge storage layer end rather than the end portion of the control electrode 7, the opposing area of the charge storage layer between adjacent cells in the word line direction is reduced, and between adjacent cells in the bit line direction Since the interval between the charge storage layers can be increased, the effect of further reducing the inter-cell interference effect is obtained.

On the N ⁺ layer 11 between the tunnel oxide film 3, the charge storage layer 4, the current blocking layer 5, and the control electrode 7, an insulating film 6 as an interlayer insulating film is provided. An insulating film 8 as an interlayer insulating film is provided on the insulating film 6 and the control electrode 7. On the insulating film 8, a wiring layer 9 as the bit line BL2 is provided. On the wiring layer 9, an insulating film 10 as a surface protective film is provided.

Here, in order to reduce the inter-cell interference effect, the relationship between the distance ΔW1 between the channel width end and the charge storage layer end and the distance ΔL1 between the control electrode end and the charge storage layer end is, for example,
ΔW1 ≧ ΔL1> 0 (3)
It is preferable to set to. The reason for this is that the interference effect between adjacent cells in the word line direction is generally more problematic in circuit operation, and that the write / erase efficiency decreases if the volume of the charge storage layer is made too small.

  Next, the operation of the semiconductor memory device will be described with reference to FIGS. 4A and 4B illustrate a write operation of the semiconductor memory device, FIG. 4A illustrates a memory cell block, FIG. 4B illustrates a write operation condition, and FIG. 5 illustrates cell spacing and inter-cell interference effects. The solid line (a) in the figure shows the characteristics of this example, and the broken line (b) in the figure shows the characteristics of the comparative example. Here, illustration and description of the read operation are omitted. In the comparative example, the charge storage layer is not provided on the STI (shallow trench isolation) 2, and the width and length of the charge storage layer are the same as those of the tunnel oxide film and the current blocking layer. Note that description of the erase operation and the read operation is omitted.

  As shown in FIG. 4A, for example, when the memory cell transistor MTR connected to the word line WL3 of the memory cell 2 is selected as a selection transistor and a write operation is performed, as shown in FIG. When writing “0 (zero)” to the selection transistor, the corresponding bit line BL is set to “0V”, and when writing “1” to the selection transistor, the corresponding bit line BL is set to the boosted high-potential power supply voltage Vdd. To do. The source line SL is set to 0 V, the control line SGD is set to the control voltage Vsg1 that is the (+) voltage, and the control voltage Vsg2 that is the (+) voltage is applied to the control line SGS to turn on the control transistor STR. The selected word line WL3 is set to the write voltage Vpgm, and the non-selected word line WL is set to the intermediate voltage Vm.

  That is, the write operation is performed by electron injection (FN (Fowler Nordheim) tunneling) from the substrate to the memory cell transistor MTR. If writing to the memory cell MC2 is performed after writing the memory cell MC1, the threshold voltage of the MC1 changes due to the inter-cell interference effect, and normal reading of the MC1 becomes difficult. In order to avoid this, it is necessary to devise a circuit operation such as gradually writing MC1 and MC2 alternately. However, the writing speed is remarkably lowered.

  The thickness of the floating electrode of the flash memory having the stacked gate structure is, for example, 50 nanometers (50 nm) or more, whereas the thickness of the charge storage layer used in the charge trap flash (CTF structure) is several nanometers ( Several nanometers). For this reason, it has been expected that in the charge trap type flash (CTF structure), the inter-cell interference does not occur even if the cell interval becomes narrow and the miniaturization progresses. However, an inter-cell interference effect has been confirmed even in an actual charge trap flash (CTF structure) in which the cells are miniaturized. This is because the capacity between cells increases rapidly in inverse proportion to the interval.

  As shown in FIG. 5, in the comparative example shown by the broken line (b), the inter-cell interference effect such as the parasitic gate effect is large even when the cell interval is relatively wide. Increase.

  On the other hand, in the present embodiment shown by the solid line (a), the inter-cell interference effect is small when the cell interval is relatively wide, and the increase in the inter-cell interference effect is suppressed even when the inter-cell interval is narrowed. The difference between the comparative example and this example is not simply the interval between the charge storage layers. In this embodiment, since the charge storage layer is inside the control gate, the control gate plays a role of shielding an electric field extending from the adjacent cell, and has an effect of suppressing the inter-cell interference effect. For example, in the comparative example, when the size is smaller than the technology node 20 nm (half pitch 20 nm), the inter-cell interference effect increases, and a malfunction of the memory cell may occur. However, in this embodiment, the technology node 20 nm. Even when it is made finer than (half pitch 20 nm), the inter-cell interference effect can be suppressed, and the memory cell can be operated normally.

  Next, a method for manufacturing a semiconductor memory device will be described with reference to FIGS. 6 to 10 are cross-sectional views showing the manufacturing process of the semiconductor memory device.

  As shown in FIG. 6, first, after forming a channel layer on a semiconductor substrate 1 made of P-type silicon by using, for example, an ion implantation method, a tunnel oxide film 3, a charge storage layer 4, a current blocking layer 5, and a hard mask are formed. The material 21 is laminated.

Here, as the tunnel oxide film 3, for example, a SiO ₂ film (silicon oxide film) having a thickness in the range of 0.5 to 10 nm is used. Instead, SiO ₂ having the same thickness in terms of EOT (Equivalent Oxide Thickness) is used. A laminated film of ₂ films / SiN film / SiO _2, a laminated film of SiO ₂ film / high dielectric constant insulating film / SiO ₂ film, or a laminated film of high dielectric constant insulating film / SiO ₂ film may be used. For the charge storage layer 4, for example, a SiN film (silicon nitride film) with a thickness of 3 to 50 nm is used.

For the current blocking layer 5 as a block film, for example, an Al ₂ O ₃ film (alumina film) having a thickness in the range of 5 to 30 nm is used. Instead, an MgO film having a higher dielectric constant than a silicon oxide film, SrO High dielectric constant insulation such as a film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, Y ₂ O ₃ film, ZrSiO film, HfSiO film, or LaAlO film A film or a laminated film thereof (including a laminated film of an Al ₂ O ₃ film (alumina film)) may also be used.

  After the tunnel oxide film 3, the charge storage layer 4, the current blocking layer 5, and the hard mask material 21 are stacked, a resist film 22 is formed using a well-known lithography method.

  Next, as shown in FIG. 7, using the resist film 22 as a mask, the hard mask material 21 is etched by, for example, RIE (Reactive Ion Etching). After removing the resist film 22, the current blocking layer 5, the charge storage layer 4, the tunnel oxide film 3, and the semiconductor substrate 1 are etched by, for example, RIE using the hard mask material 21 as a mask, and the first main surface of the semiconductor substrate 1 is etched. Grooves 23 are formed on the (surface). The current blocking layer 5, the charge storage layer 4, and the tunnel oxide film 3 are etched vertically, for example.

  Here, the current blocking layer 5, the charge storage layer 4, the tunnel oxide film 3, and the semiconductor substrate 1 are etched using the hard mask material 21 as a mask, but may be etched using the resist film as a mask.

  Subsequently, as shown in FIG. 8, an insulating film is deposited on the first main surface (front surface) of the semiconductor substrate 1, and, for example, the entire surface is etched back to form STI (shallow trench isolation) in the groove 23. After the formation of STI (shallow trench isolation) 2, both ends of the charge storage layer 4 are etched by, for example, CDE (Chemical Dry Etching) method so that the charge storage layer 4 is located inside the tunnel oxide film 3 and the current blocking layer 5. Retreat.

In the CDE method, the etching rate of the silicon nitride film of the charge storage layer 4 can be made larger (approximately two digits or more) than the etching rate of the oxide films constituting the mask material 21, the tunnel oxide film 3 and the current blocking layer 5. For example, it is preferable to add nitrogen (N ₂ ) gas to the etching gas.

  Then, as shown in FIG. 9, after forming the insulating film 6 on the STI (shallow trench isolation) 2 and the mask material 21, the surface of the current blocking layer 5 is exposed by using, for example, a CMP (Chemical Mechanical Polishing) method. Then, flat polishing is performed (the insulating film 6 and the mask material 21 are polished).

Next, as shown in FIG. 10, the gate electrode 7 is formed on the current blocking layer 5 and the insulating film 6. Here, the gate electrode 7 uses a laminated film of an N ⁺ polycrystalline silicon film doped with a high concentration of N-type impurities and a metal silicide, but a P ⁺ multiple doped with a high concentration of P-type impurities. A stacked film of a crystalline silicon film and a metal silicide, a P ⁺ polycrystalline silicon film, or an N ⁺ polycrystalline silicon film doped with N-type impurities at a high concentration may be used. Alternatively, a metal film / polycrystalline silicon laminated film or a metal film / metal nitride laminated film may be used. In this case, the metal silicide is CoSi, NiSi, WSi, MoSi, TiSi or the like, the metal is W or the like, and the metal nitride is WN, TaN, TiN or the like.

Subsequently, although not shown, the gate electrode 7, the current blocking layer 5, and the charge storage layer 4 are vertically etched by, for example, RIE using a hard mask material or a resist film as a mask. After the etching in the vertical direction, similarly to the word line direction, the side surface portion in the bit line direction of the charge storage layer 4 is made to recede from the current blocking layer 5 by using, for example, the CDE method. Thereafter, the tunnel oxide film 3 is etched to form the gate of the memory cell transistor MTR. A semiconductor memory device 70 which is a NAND flash memory having a charge trap flash (CTF) structure is formed by forming an N ⁺ layer 11, an insulating film 8, a wiring layer 9, an insulating film 10 and the like using a known technique. .

As described above, in the semiconductor memory device of this embodiment, the STI (shallow trench isolation) 2 is embedded in the first main surface (front surface) of the semiconductor substrate 1 made of P-type silicon in the word line direction. On the first main surface (surface) of the semiconductor substrate between STI (shallow trench isolation) 2, a tunnel oxide film 3, a charge storage layer 4, and a current blocking layer 5 are stacked. End of the charge storage layer 4 is provided inside by a distance ΔW1 charge storage layer end and the channel width end than the end of the channel width W _CH. On the current blocking layer 5 and the insulating film 6, a control electrode 7 as the word line WL3 is provided. In the bit line direction, an N ⁺ layer 11 serving as a source or drain of the memory cell transistor MTR is provided on the first main surface (front surface) of the semiconductor substrate 1. A tunnel oxide film 3, a charge storage layer 4, a current blocking layer 5, and a control electrode 7 are stacked on the first main surface (front surface) of the semiconductor substrate between the N ⁺ layers 11. Tunnel oxide film 3 is provided so as to overlap with N ⁺ layer 11. A channel layer is formed on the first main surface (front surface) of the semiconductor substrate immediately below the tunnel oxide film 3. The end of the charge storage layer 4 is provided more inside than the end of the control electrode 7 by a distance ΔL1 between the control electrode end and the charge storage layer end.

  Therefore, a parasitic gate effect in which the potential of the charge storage layer of the memory cell transistor of the own cell or the potential of the channel is modulated by the potential of the charge storage layer of the memory cell transistor constituting the semiconductor memory device 70 having the charge trap type flash structure. It can be greatly suppressed. Therefore, even when the cell interval is reduced and the half pitch is reduced, the inter-cell interference effect of the semiconductor memory device 70 can be suppressed.

  In this embodiment, the memory cell transistor is formed on the semiconductor substrate 1 made of P-type silicon. However, the memory cell transistor may be formed on a P well layer or an SOI (silicon on insulator) substrate. . In addition, although the gate portion of the memory cell transistor is stacked on the plane of the semiconductor substrate 1, the gate portion may be formed (three-dimensionally formed) on the semiconductor substrate 1 having a semi-cylindrical shape or a columnar shape. .

  Next, a semiconductor memory device according to Embodiment 2 of the present invention will be described with reference to the drawings. 11 is a cross-sectional view in the word line direction of the semiconductor memory device, and FIG. 12 is a cross-sectional view in the bit line direction of the semiconductor memory device. In this embodiment, the charge storage layer has a forward tapered shape.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

As shown in FIG. 11, in the word line direction, in the semiconductor memory device 70a, a forward tapered charge storage layer 4 whose upper part is narrower than the lower part is provided between the tunnel oxide film 3 and the current blocking layer 5. It is done. The lower end of the charge storage layer 4 is provided inside by a distance ΔW1 charge storage layer end and the channel width end than the end of the channel width W _CH.

  As shown in FIG. 12, in the bit line direction, in the semiconductor memory device 70a, a forward tapered charge storage layer 4 whose upper part is narrower than the lower part is provided between the tunnel oxide film 3 and the current blocking layer 5. It is done. The lower end portion of the charge storage layer 4 is provided more inside than the end portion of the control electrode 7 by a distance ΔL1 between the control electrode end and the charge storage layer end.

  Next, a method for manufacturing a semiconductor memory device will be described with reference to FIG. FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor memory device.

  As shown in FIG. 13, after the formation of STI (shallow trench isolation) 2 in the same manner as in Example 1, the charge storage layer 4 is etched into a forward taper shape by using hot phosphoric acid, for example. Is made to recede from the tunnel oxide film 3 and the current blocking layer 5 to the inside.

  The condition of the hot phosphoric acid is, for example, in the range of 160 to 180 ° C., and the etching rate of the silicon nitride film of the charge storage layer 4 is higher than the etching rate of the oxide film constituting the mask material 21, the tunnel oxide film 3 and the current blocking layer 5. It is preferable to use a condition (approximately 40 times or more) that is larger (approximately 5 times or more) than the etching rate of the semiconductor substrate 1. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

As described above, in the semiconductor memory device of this embodiment, the tunnel oxide film 3 and the charge storage layer are formed on the first main surface (surface) of the semiconductor substrate between the STI (shallow trench isolation) 2 in the word line direction. 4 and the current blocking layer 5 are laminated. The charge storage layer 4 has a forward tapered shape. The lower end of the charge storage layer 4 is provided inside by a distance ΔW1 charge storage layer end and the channel width end than the end of the channel width W _CH. On the current blocking layer 5 and the insulating film 6, a control electrode 7 as the word line WL3 is provided. In the bit line direction, a tunnel oxide film 3, a charge storage layer 4, a current blocking layer 5, and a control electrode 7 are stacked on the first main surface (surface) of the semiconductor substrate between the N ⁺ layers 11. The charge storage layer 4 has a forward tapered shape. The lower end portion of the charge storage layer 4 is provided more inside than the end portion of the control electrode 7 by a distance ΔL1 between the control electrode end and the charge storage layer end.

  Therefore, a parasitic gate effect in which the potential of the charge storage layer of the memory cell transistor of the own cell and the potential of the channel are modulated by the potential of the charge storage layer of the memory cell transistor constituting the semiconductor memory device 70a of the charge trap type flash structure. It can be greatly suppressed. Therefore, even when the cell interval is narrowed and the half pitch is reduced, the inter-cell interference effect of the semiconductor memory device 70a can be suppressed.

  Next, a semiconductor memory device according to Embodiment 3 of the present invention will be described with reference to the drawings. 14 is a cross-sectional view in the word line direction of the semiconductor memory device, and FIG. 15 is a cross-sectional view in the bit line direction. In this embodiment, the charge storage layer has a reverse taper shape.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

As shown in FIG. 14, in the word line direction, the semiconductor memory device 70 b is provided with a reverse-tapered charge storage layer 4 between the tunnel oxide film 3 and the current blocking layer 5, the lower part being narrower than the upper part. It is done. The upper end of the charge storage layer 4 is provided inside by a distance ΔW1 charge storage layer end and the channel width end than the end of the channel width W _CH.

  As shown in FIG. 15, in the bit line direction, the semiconductor storage device 70 b is provided with a reverse-tapered charge storage layer 4 between the tunnel oxide film 3 and the current blocking layer 5, the lower part being narrower than the upper part. It is done. The upper end portion of the charge storage layer 4 is provided more inside than the end portion of the control electrode 7 by a distance ΔL1 between the control electrode end and the charge storage layer end.

  Next, a method for manufacturing a semiconductor memory device will be described with reference to FIG. FIG. 16 is a cross-sectional view showing the manufacturing process of the semiconductor memory device.

  As shown in FIG. 16, after the formation of STI (shallow trench isolation) 2 as in the first embodiment, the both ends of the charge storage layer 4 are inversely tapered using, for example, an oxygen plasma method generated by magnetron high-frequency discharge. As a result, the charge storage layer 4 is made to recede from the tunnel oxide film 3 and the current blocking layer 5 to the inside.

  Oxidation of the silicon nitride film (SiN film) that is the charge storage layer 4 by oxygen plasma is performed, for example, at a pressure of 5 to 7 Torr and 400 ° C. or lower.

As described above, in the semiconductor memory device of this embodiment, the tunnel oxide film 3 and the charge storage layer are formed on the first main surface (surface) of the semiconductor substrate between the STI (shallow trench isolation) 2 in the word line direction. 4 and the current blocking layer 5 are laminated. The charge storage layer 4 has a reverse taper shape. The upper end of the charge storage layer 4 is provided inside by a distance ΔW1 charge storage layer end and the channel width end than the end of the channel width W _CH. On the current blocking layer 5 and the insulating film 6, a control electrode 7 as the word line WL3 is provided. In the bit line direction, a tunnel oxide film 3, a charge storage layer 4, a current blocking layer 5, and a control electrode 7 are stacked on the first main surface (surface) of the semiconductor substrate between the N ⁺ layers 11. The charge storage layer 4 has a reverse taper shape. The upper end portion of the charge storage layer 4 is provided more inside than the end portion of the control electrode 7 by a distance ΔL1 between the control electrode end and the charge storage layer end.

  For this reason, a parasitic gate effect in which the potential of the charge storage layer of the memory cell transistor of the self cell or the channel potential is modulated by the potential of the charge storage layer of the memory cell transistor constituting the semiconductor memory device 70b of the charge trap type flash structure. It can be greatly suppressed. Therefore, even when the cell interval is narrowed and the half pitch is reduced, the inter-cell interference effect of the semiconductor memory device 70b can be suppressed.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the present invention is applied to a NAND flash memory having a charge trap type flash (CTF) structure, but it can also be applied to an ORNAND type flash memory having a charge trap type flash (CTF) structure.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A semiconductor substrate, a memory cell transistor in which a tunnel oxide film, a charge storage layer, a current blocking layer, and a control electrode are stacked on the semiconductor substrate, and the control electrode is connected to a word line, and a bit line And memory cells in which the memory cell transistors are cascade-connected between the source lines, and in the word line direction, the width of the charge storage layer is narrower than the channel width of the memory cell transistors, and in the bit line direction The charge storage layer has a length shorter than that of the control electrode, and has a charge trap structure.

(Supplementary Note 2) The current blocking layer, _Al 2 _{O 3} film, MgO film, SrO film, BaO film, TiO film, _Ta 2 _{O 5} film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, Y ₂ O ₃ film, ZrSiO film, HfSiO film, or LaAlO film is a laminated film including a high dielectric constant insulating film, and the laminated film is SiO ₂ film / the high dielectric constant insulating film from the first insulating film side. Supplementary note 1 which is a film / SiO ₂ film, SiO ₂ film / the high dielectric constant insulating film, the high dielectric constant insulating film / SiO ₂ film, or the high dielectric constant insulating film / SiO ₂ film / the high dielectric constant insulating film. The semiconductor memory device described in 1.

(Additional remark 3) The said memory cell is a semiconductor memory device of Additional remark 1 or 2 which is a silicon nitride film.

(Supplementary Note 4) The tunnel oxide film is a SiO ₂ film or a laminated film including a SiO ₂ film. In the case of the laminated film, from the semiconductor substrate side, the SiO ₂ film / SiN film / SiO ₂ film, SiO ₂ film / 4. The semiconductor memory device according to appendix 1 or 3, which is a high dielectric constant insulating film / SiO ₂ film or a high dielectric constant insulating film / SiO ₂ film.

FIG. 1A is a circuit diagram illustrating a semiconductor memory device, and FIG. 1B is a plan view illustrating the semiconductor memory device. FIG. 2 is a cross-sectional view of the semiconductor memory device taken along line AA in FIG. FIG. 3 is a cross-sectional view of the semiconductor memory device taken along line BB in FIG. FIGS. 4A and 4B illustrate a write operation of the semiconductor memory device according to the first embodiment of the invention, FIG. 4A illustrates a memory cell block, and FIG. 4B illustrates a write operation condition. The figure which shows the relationship between the cell space | interval which concerns on Example 1 of this invention, and the interference effect between cells, The solid line (a) in a figure shows the characteristic of a present Example, The broken line (b) in a figure shows the characteristic of a comparative example Figure. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 1 of this invention. Sectional drawing of the word line direction of the semiconductor memory device concerning Example 2 of this invention. Sectional drawing of the bit line direction of the semiconductor memory device based on Example 2 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 2 of this invention. Sectional drawing of the word line direction of the semiconductor memory device concerning Example 3 of this invention. Sectional drawing of the bit line direction of the semiconductor memory device concerning Example 3 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor memory device based on Example 3 of this invention.

Explanation of symbols

1 Semiconductor substrate 2 STI (shallow trench isolation)
3 Tunnel oxide film 4 Charge storage layer 5 Current blocking layers 6, 8, 10 Insulating film 7 Control electrode 9 Wiring layer 11 N ⁺ layer 21 Hard mask material 22 Resist film 23 Groove 70, 70a, 70b Semiconductor memory device BL1-3 bits Line BLC Bit line contact L _DCL1 Charge storage layer length L _SG control electrode length MC1-3 Memory cell MTR Memory cell transistor SDG, SGS Control line SL Source line SLC Source line contact STR Control transistor Vdd High potential side power supply voltage Vm Intermediate voltage Vpgm write voltage Vsg1, Vsg2 control voltage _{W CH} channel width _{W DCL1} charge accumulation layer width _WL 1 to 4, WL _n word lines ΔL1 control electrode terminal and the interval of the charge storage layer end and the distance ΔW1 channel width end of the charge storage layer end

Claims (5)

A semiconductor substrate;
A memory cell transistor in which a tunnel oxide film, a charge storage layer, a current blocking layer, and a control electrode are stacked on the semiconductor substrate, and the control electrode is connected to a word line;
A memory cell in which the memory cell transistors are cascade-connected between a bit line and a source line;
And a width of the charge storage layer is narrower than a channel width of the memory cell transistor in the word line direction. A semiconductor substrate;
A memory cell transistor in which a tunnel oxide film, a charge storage layer, a current blocking layer, and a control electrode are stacked on the semiconductor substrate, and the control electrode is connected to a word line;
A memory cell in which the memory cell transistors are cascade-connected between a bit line and a source line;
The width of the charge storage layer is narrower than the channel width of the memory cell transistor in the word line direction, and the length of the charge storage layer is shorter than the length of the control electrode in the bit line direction. A semiconductor memory device.   The distance between the end of the channel layer of the memory cell transistor and the end of the charge storage layer in one direction in the word line direction is such that the end of the control electrode and the end of the charge storage layer in one direction in the bit line direction. 3. The semiconductor memory device according to claim 2, wherein the distance is larger than the interval of.   4. The semiconductor memory according to claim 1, wherein the charge storage layer has a forward tapered shape in which an upper width is narrower than a lower width in a word line direction or a bit line direction. 5. apparatus.   4. The semiconductor memory according to claim 1, wherein the charge storage layer has an inverse tapered shape in which a lower width is narrower than an upper width in a word line direction or a bit line direction. 5. apparatus.

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