JPS60120552A - Bipolar cmis device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the latchup withstand voltage of a CMOS element and to completely electrically separate a bipolar transistor by forming a high density buried layer under a region formed with a bipolar CMOS device. CONSTITUTION:High density buried layers 2, 3, 7, 8 are formed on a substrate 1. The buried layer 2 is formed under a region forming a bipolar transistor. The layer 3 is formed under a region for forming a P-channel CMOS element, and is a reverse conductive type N<+> type buried layer to the substrate together with the layer 2. A bipolar transistor, a P-channel CMOS element and an N-channel CMOS element are respectively formed in the N<-> type well layer 12, 13 and a P<-> type well layer 16 of the active regions. The latchup withstand voltage of the CMOS element is improved by the layer 3. Further, the electric separation of the bipolar transistor can be electrically separated by the layers 15 of the separated well layer and the layer 2.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology for forming a bipolar transistor and a complementary metal insulator semiconductor element (complementary metal insulator semiconductor, so-called CMIS) on the same substrate. In particular, the present invention relates to techniques that can be effectively used to form completely isolated bipolar transistors and bipolar CMOS devices suitable for improving latch-up breakdown voltage.

[Background technology] In general, a bipolar transistor and a CMO3 element are formed on the same substrate, and an ECL (emitter coupled logic) version of CMO8R, AM or an LS using CMO8
Various TTL and ECL versions of I are being developed. In this case, various techniques are being studied to completely electrically isolate the bipolar transistor from the CMO 5 on the same substrate and to improve the latch-up breakdown voltage. Various techniques have also been developed to efficiently manufacture bipolar CMO3 by making the most of the current 0MO3 element manufacturing process.

For example, as one such technology, Japanese Patent Application Laid-open No. 54
``Method for manufacturing bipolar CMO8 type O8 circuit'' in No. 131887 is disclosed. This technique forms a heavily doped N4 buried layer below the N-channel MO8 and controls the diffusion depth of the P-type impurity well layer, which is the active region for the N-channel MO8. Therefore, the device isolation region of the bipolar transistor and CMO3 and the diffusion of the P-type impurity well layer can be performed simultaneously, and the manufacturing process can be simplified. However, bipolar CMOS requires complete electrical isolation of bipolar transistors, simplification of the process, and latch-up countermeasures.
It does not disclose general device technology.

[Object of the Invention] Accordingly, an object of the present invention is to provide a bipolar CMIS device and a method for manufacturing the same, which aim at complete electrical isolation of bipolar transistors and improvement of the latch-up withstand voltage of the CMO8 section.

Furthermore, it is an object of the present invention to facilitate the formation of isolation regions and to be able to sufficiently prevent latch-up even when the semiconductor substrate concentration is lowered, greatly increasing the degree of freedom in the manufacturing process of bipolar CMIS devices. Bipolar C raised to
The present invention provides a MOS device and a method for manufacturing the same.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, a bipolar transistor and a CMO of one conductivity type
By forming a heavily doped buried layer of conductivity type opposite to that of the semiconductor board below the region where the 8 elements are formed, the latch-up breakdown voltage can be improved due to the low resistance of the heavily doped buried layer, and the bipolar transistor region and Since a separation layer of impurity semiconductor is formed between the CMO5 region of one conductivity type,
Complete electrical isolation of the bipolar transistor is achieved through PN junction isolation.

Furthermore, according to a preferred embodiment, in addition to the area below the bipolar 1 to transistor and one conductivity type 0MO3 element regions,
By forming a high concentration buried layer of the same conductivity type as the semiconductor substrate below the isolation region and the 0MO8 element region of a different conductivity type, the latch-up withstand voltage can be lowered by lowering the concentration of the semiconductor substrate due to the low resistance of the high concentration buried layer. The electrical isolation can be sufficiently improved, and the diffusion for isolation is assisted by upwelling due to the highly doped buried layer below the isolation region, achieving complete electrical isolation.

[Embodiment] First, a most preferred embodiment of the structure of the bipolar CMOS device of the present invention will be described with reference to FIG. Fifth
In the figure, reference numeral 1 indicates an impurity semiconductor substrate, for example, a P-type silicon semiconductor substrate. This board 1
Highly doped buried layers 2, 3, 7 and 8 are formed above.

The buried layer 2 is located below the region where the bipolar transistor is formed, and is an N+ buried layer of a conductivity type opposite to that of the semiconductor substrate 1. The buried layer 3 is located below the region where the I] channel CMO8 element is formed, and is also an N+ buried layer of the opposite conductivity type to the semiconductor substrate 1.

Here, these buried layers 2 and 3 are connected to the first and second layers, respectively.
This is called the embedded layer. Further, the buried layer N7 is located below the isolation region and is a P+ buried layer having the same conductivity type as the semiconductor substrate l. The buried layer 8 is located below the region where the N-channel 0MO8 element is formed, and is also a P+ layer of the same conductivity type as the semiconductor substrate 1.
It is a buried layer.

Here, these buried layers 7 and 8 are replaced with third and fourth layers, respectively.
This is called the embedded layer.

Above the first buried layer 2 and the second buried layer 3,
N-type well layers 12 and 13 are formed in the epitaxial layer, respectively.

Further, above the third buried layer 7 and the fourth buried layer 8, there is a P-type well layer 1 formed in the epitaxial layer.
5 and 16 are formed.

The P-type well layer 15 is an isolation well layer that electrically isolates the bipolar transistor and the P-channel CMO8 element.

A bipolar transistor, a P-channel CMO8 element, and an N-channel CMO, S element are formed in the N-well layers 12 and 13 and the P-well layer 16 of these active regions, respectively.

Reference numeral 17 indicates a P-type impurity region of the base diffusion region, reference numeral 18
is the N+ type impurity region of the emitter diffusion region, and the symbol 1-9 is N÷ which forms the ohmic contact for the collector.
Type impurity region, code 24 is field 1 (oxide film,
They form a bipolar transistor. Codes 2o and 21 are P channels C and MO, respectively.
P+ type impurity region forming the source and drain of the S element,
Reference numeral 25 is a gate oxide film, and reference numeral 26 is a polysilicon electrode, forming a P-channel CMO8 element. Similarly, numerals 22 and 23 respectively represent N channel 0M
An N+ type impurity region forming the source and drain of the O8 element, reference numeral 25 is a gate oxide film, and reference numeral 26 is a polysilicon electrode, forming an N-channel 0MO8 element.

According to the preferred embodiment of the bipolar CMOS device of the present invention configured as described above, the second buried layer 3 with high concentration not only improves the latch-up voltage of the CMO8 element, but also improves the latch-up breakdown voltage of the CMO8 element. The bipolar transistors are electrically isolated by the P-type well layer 15 and the first buried layer 2. Furthermore, the rise of the third buried layer 7 makes it possible to obtain a complete isolation function for the P-type well layer]-5, and the presence of the fourth buried layer 8 provides a sufficient latch-up breakdown voltage. It is also possible to lower the concentration of the semiconductor substrate 1.

In the embodiment shown in FIG. 5, the third buried layer 7 and the fourth buried layer 8 are not formed, and the P-
It is also possible to use the mold well layers 15 and 16 by diffusing them until they reach the semiconductor substrate 1.

Next, a method for manufacturing the bipolar CMOS device according to the preferred embodiment shown in FIG. 5 will be explained with reference to the process diagrams shown in FIGS. 1 to 4.

In FIG. 1, an impurity semiconductor substrate 1, for example, P-
The surface of the type silicon semiconductor substrate is oxidized, for example, 5i0
A dioxide film 4 is formed to a thickness of about 50 nm. Next, 5i02
For example, a 5i3Na film 5 with a thickness of 140 nm is formed on the oxide film 4.
form a degree. After this, the first buried layer 2 and the second
A photoresist process for forming the buried layer 3 is performed to form a required window opening. Then, a first buried layer 2 and a second buried layer 3, which are high concentration N+ diffusion layers, are simultaneously formed using antimony, arsenic, or the like.

In FIG. 2, after a relatively thick oxide film 6 is formed on the first buried layer 2 and the second buried layer 3, the Si3N4 film 5 as an oxidation-resistant film is removed. Thereafter, a third buried layer 7 and a fourth buried layer 8, which are high concentration P+ diffusion layers, are simultaneously formed using boron or the like. Epitaxial growth is performed on the buried layers 2, 3 and 7, 8 thus formed.

In FIG. 3, an SiO2 oxide film 10 of about 40 nm and a 50nm SiO2 oxide film 10 of about 40 nm are again formed on an epitaxial layer 9 of about 1.6 μm, for example, formed by epitaxial growth.
A Si3N4 film 11 having a thickness of about m is formed. At this time, on each of the buried layers 2, 3 and 7, 8, upwelling layers of the same conductivity type are formed during epitaxial growth, forming N- and P- layers in the figure.
, N-.

It is formed as shown as P-. This upwelling layer has a thickness of approximately 1 .mu.m at a concentration of 10"/cm" if the epitaxial layer 9 is 1.6 .mu.m. Next, as shown in FIG. 1, a photoresist process is performed to form the required openings. At this time, the same mask used in the process shown in FIG. 1 can be used as the mask. Here, N-type well regions 12 and 13, which will become regions for the bipolar transistor and the N-channel 0MO3 element, are formed at the same time.

In FIG. 4, after forming a field oxide film 14 on the N-type well layer 12 on the first buried layer 2 and the N-type well layer 13 on the second buried layer 3, The Si3N4 film as a film is removed. Thereafter, P-type well layers 15 and 16 are simultaneously formed using boron or the like. At this time, the P-type well layer 15 operates as a P-type isolation well for the isolation layer, and the third buried layer 7
The electrical isolation becomes even more complete due to the upwelling of .

In FIG. 5, after the process shown in FIG.
8 gate oxide film 25, polysilicon gate electrode C
There is formation by the VD method, and formation of the emitter, base, collector contact, source, drain, etc. of each active region, but since these can be performed using conventional techniques, they will not be described in detail here. Note that the P-type impurity region 17, which is the base diffusion region of the bipolar transistor, is a P-channel CM.
It may be formed simultaneously with the formation of the source and drain of the OS device, or it may be formed separately and independently. Also, N is the emitter diffusion region of the bipolar transistor.
The 10-type impurity region 18 may be formed at the same time as the source/drain diffusion of the N-channel CMOS device. N+ type impurity region 19, which is an ohmic contact of the collector, can also be formed at the same time. When the emitter and base are formed independently, the emitter diffusion depth of the electrically isolated bipolar transistor is 0.3 μm and the base diffusion depth is 0.5 μm.
It is also possible to obtain high performance bipolar transistors of about 5 μm.

In the embodiment shown in FIGS. 1 to 4, the P-type well layers 15 and 16 are formed to reach the semiconductor substrate 1 without forming the third buried layer 7 and the fourth buried layer 8. It is also possible to use it by diffusing it until it becomes .

[Effects] Preferred embodiments of the bipolar CMOS device of the present invention and its manufacturing method have been described in detail above, and the effects of the present invention are as follows.

Since a high concentration buried layer of reverse voltage type is formed below the region where the bipolar transistor and one conductivity type 0MO3 element are formed, the latch-up withstand voltage can be improved due to the low resistance of the high concentration buried layer. Moreover, since the isolation well layer of impurity semiconductor is formed between the bipolar transistor region and the CMO8 region of one conductivity type, the bipolar transistor can be completely electrically isolated by PN junction isolation.

Furthermore, bipolar transistor and one conductivity type 0MO5
In addition to the lower part of the element region, there is also an isolation well layer and C of other conductivity type.
Since a heavily doped buried layer of the same conductivity type as the semiconductor substrate is formed below the well layer for the MO8 element, the resistance of the heavily doped buried layer is low.

The latch-up withstand voltage can be sufficiently improved even if the concentration of the semiconductor substrate is lowered, and the diffusion for isolation is assisted by the well-concentrated buried layer under the isolation well layer, resulting in complete electrical isolation. This has the effect of being able to.

Due to both of the above effects, the flexibility of the manufacturing process is greatly improved because the bipolar transistor, 0MO3 element, and the bottom of the isolation well are all formed with a high concentration buried layer. Various effects such as the ability to form an impurity semiconductor region can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Field of Application] The bipolar CMOS device and its manufacturing method of the present invention are most effective when applied to the ECL version of 0MO3RA, M, but it can also be applied to LS using other CMIS.
For example, it can be widely applied to TTL versions and ECL versions as well.

[Brief explanation of the drawing]

1 to 4 are step-by-step process diagrams showing preferred embodiments of the manufacturing process of the bipolar CMOS device of the present invention, and FIG. FIG. 2 is a structural diagram of a preferred embodiment of a bipolar CMOS device. 1... Semiconductor substrate, 2... First buried layer (N÷buried layer), 3... Second buried layer (N+ type buried layer)
, 7... third buried layer (P+ type buried layer), 8...
- Fourth buried layer (P+ type buried layer). 12.13... N-well layer, 15... Separation well layer (P-well layer), 16... P-well layer. Agent Patent Attorney Akio Takahashi

Claims (1)

[Claims] 1. High concentration first and second buried layers of a second conductivity type formed at a predetermined distance on a semiconductor substrate of a first conductivity type, and the semiconductor substrate a second conductivity type epitaxial layer formed over the entire surface; and a second conductivity type epitaxial layer formed directly above the first and second buried layers to form a bipolar transistor region and a first channel type CMIS element region, respectively. diffusion between the well layer of conductivity type and the first and second buried layers until reaching the semiconductor substrate in order to electrically isolate the bipolar transistor region and the first channel type CMIS element region. an isolation well layer of a first conductivity type and a CMIS of a second channel type.
A bipolar CMIS device comprising a well layer of a first conductivity type diffused up to the semiconductor substrate to form a device region. 2. Further comprising third and fourth buried layers of the first conductivity type with high concentration formed in parallel between the first and second buried layers, and separating the first conductivity type. The well layer is diffused until reaching the third buried layer, and the well layer of the first conductivity type is diffused until reaching the fourth buried layer. A bipolar CMIS device according to scope 1. 3. Bipolar 1-transistor and C on the same semiconductor substrate
1. A method for manufacturing a bipolar CMIS device, which comprises a MIS element and is manufactured through the following steps. (A) A step of selectively diffusing highly concentrated impurities of a second conductivity type into a semiconductor substrate of a first conductivity type to form first and second buried layers having a desired spacing. (B) A step of forming an epitaxial layer of a second conductivity type over the entire surface of the semiconductor substrate. (C) An oxide film is formed on the epitaxial layer, and a piebola transistor region directly above the first buried layer and a first channel type CMI directly above the second buried layer are formed.
A step of selectively removing the oxide film to form an opening for diffusion in order to simultaneously form an S element region. (1)) A step of diffusing a second conductivity type impurity through the opening until it reaches the first and second buried layers. (E) An oxide film is formed on the surface of the device formed in the step (D), and a region separating the bipolar transistor region and the first channel type CMIS element region and a second channel type CMIS element region are formed. A step of selectively removing the oxide film to form an opening hole for diffusion in order to simultaneously form a CMIS element region. (F) a step of diffusing a first conductivity type impurity through the opening until it reaches the semiconductor substrate; 4. After the step (A), further form highly concentrated third and fourth buried layers of the first conductivity type in parallel between the first and second buried layers, and perform the step (A). 4. The method of manufacturing a bipolar CMIS device according to claim 3, wherein the diffusion of F) is performed until reaching these third and fourth buried layers.