KR930008900B1 - Manufacturing method of cmos using boe - Google Patents

Manufacturing method of cmos using boe Download PDF

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KR930008900B1
KR930008900B1 KR1019900014498A KR900014498A KR930008900B1 KR 930008900 B1 KR930008900 B1 KR 930008900B1 KR 1019900014498 A KR1019900014498 A KR 1019900014498A KR 900014498 A KR900014498 A KR 900014498A KR 930008900 B1 KR930008900 B1 KR 930008900B1
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buried layer
buried
layer
forming
cmos
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KR920007182A (en
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이경수
신봉조
김흥식
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The CMOS using BOE (buried oxidation epitaxy) is parpared by forming a oxide film as mask for producing P+ and N+ buried layers on the substrate, implanting 1.0E14-1.0E15 ion and 35 kev - 20 kev energy to form the P+ buried layer, implanting at the same condition to form the N+ buried layer, depositing 1-5 m epitaxial layer on the all area of the substrate and driving in the implante ions to reath 0.3-0.5 m of the device-surface channel. The device has a high punch-through voltage and an improved latch-up and a good isolation.

Description

BOE를 이용한 시모스 제조방법Method of manufacturing CMOS using BOE

제 1a-1g 도는 본 발명에 따른 시모스 제조 공정도.Figure 1a-1g is a CMOS manufacturing process according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 기판 11 : 산화막10 substrate 11 oxide film

12,12a,12b : 포토레지스터 13 : 에피택셜12,12a, 12b photoresistor 13: epitaxial

14a : P+ 매립층 14b : N+ 매립층14a: P + buried layer 14b: N + buried layer

15 : 웰산화막 16 : N웰15 well oxide film 16: N well

17 : 필드산화막17: field oxide film

본 발명은 시모스(CMOS) 제조방법에 관한 것으로, 특히 에피택셜(Epitaxial)층을 이용하여 P+ 매립(Buried)층과 N+ 매립층을 형성시킴으로서 모스 소자 중 숏채널(Short Channel) 소자의 펀치-쓰루(Punch-Through)와 래치-업(Latch-Up)을 향상시킬 뿐 아니라 인접한 소자가의 완전한 아이솔레이션(Isolation)을 시킬 수 있도록 한 BOE(Buried Oxidation Epitaxy)를 이용한 시모스 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing CMOS, and in particular, by forming an P + buried layer and an N + buried layer using an epitaxial layer, a punch-through of a short channel device among MOS devices is performed. The present invention relates to a method for fabricating CMOS using BOE (Buried Oxidation Epitaxy), which not only improves punch-through and latch-up, but also enables complete isolation of adjacent devices.

종래에 에피택셜층은 바이폴라 소자에 주로 사용되었는데, N+ 매립층을 이용하여 콜렉터 저항을 줄이고 콜렉터와 에이터간의 항복 전압을 증가시키고, 또한 소자간 분리에도 유리하게 사용되었다.In the past, epitaxial layers were mainly used for bipolar devices, and the N + buried layer was used to reduce the collector resistance, increase the breakdown voltage between the collector and the actor, and also advantageously separate the devices.

모스소자중 숏채널 소자에서는 펀치-쓰루를 사용하기 위해 기판쪽 농도를 높여주기 위하여 딥(Deep) 이온 주입을 사용하고 있다.In the short channel device of the MOS device, deep ion implantation is used to increase the concentration of the substrate in order to use the punch-through.

그러나 이와 같은 종래의 시모스 공정에 있어서는 벌크(Bulk) 부분의 농도가 낮아 채널 사이에 펀치-쓰루를 유발시켰으며 래치-업이 생겼다.However, in the conventional CMOS process, the concentration of the bulk portion is low, causing punch-through between channels, and latch-up occurs.

또한 완전한 아이솔레션이 안되는 단점이 있었다.It also had the disadvantage of not being fully isolated.

이에 따라 본 발명은 상기한 단점을 해결하기 위해 기존의 시모스 공정을 수행하기 전에 먼저, 반도체 기판(10) 상에 3000Å 정도 두께의 산화막(11)을 형성한 후 매립층이 형성될 영역상의 상기 산화막(11)을 포토레지스트(12)를 이용한 사진식각 공정에 의해 제거한다(제 1a 도).Accordingly, in order to solve the above disadvantages, the present invention first forms an oxide film 11 having a thickness of about 3000 Å on the semiconductor substrate 10 before performing the conventional CMOS process, and then the oxide film on the region where the buried layer is to be formed ( 11) is removed by a photolithography process using the photoresist 12 (Fig. 1A).

이어서 상기 포토레지스터(12)를 제거한 후 P+ 매립층이 형성될 영역 이외의 영역을 포토레지스트(12a)로 마스킹 한 다음 엔모스(NMOS)쪽에 P+ 매립층 형성을 위해 보론(Boron)을 이온주입량 1.0E14-1.0E15, 에너지 35KeV±20KeV으로 주입한다(제 1b 도).Subsequently, after removing the photoresist 12, masking the region other than the region where the P + buried layer is to be formed with the photoresist 12a, and boron is implanted to form the P + buried layer on the NMOS side. Inject at 1.0E15, energy 35KeV ± 20KeV (FIG. 1B).

다음에 상기 포토레지스트(12a)를 제거한 다음 N+ 매립층이 형성될 영역 이외의 영역을 포토레지스트(12b)를 마스킹한 후 피모스(P MOS)쪽에 N+ 매립층 형성을 위해 비소(As)을 이온주입량 3.0E14-3.0E15, 에너지 35KeV±20KeV으로 주입한다(제1도(c)).Next, after removing the photoresist 12a, the photoresist 12b is masked in a region other than the region where the N + buried layer is to be formed, and then arsenic (As) ion implantation amount 3.0 is formed to form an N + buried layer on the PMOS side. Inject with E14-3.0E15, energy 35KeV ± 20KeV (FIG. 1 (c)).

이어서 상기 포토레지스트(12b)와 산화막(11)을 제거한 후 에피택셜층(13)을 1-5㎛ 두께로 성장시키고 드라이브-인(Drive-In) 공정을 실시하면 상기 P+ 매립층 및 N+ 매립층 형성을 위한 이온이 주입된 부분이 상기 성장된 에피택셜층(14)쪽으로 확산되어 기판(10)과 에피택셜층(14)에 걸쳐서 P+ 매립층(14a)과 N+ 매립층(14b)이 형성된다(제 1d 도).Subsequently, after removing the photoresist 12b and the oxide film 11, the epitaxial layer 13 is grown to a thickness of 1-5 μm and a drive-in process is performed to form the P + buried layer and the N + buried layer. A portion implanted with ions diffuses toward the grown epitaxial layer 14 to form a P + buried layer 14a and an N + buried layer 14b over the substrate 10 and the epitaxial layer 14 (FIG. 1D). ).

이때 에피택셜층(13) 위로 확산되는 정도가 소자 표면 채널의 0.3-0.3㎛까지 올라가도록 드라이브인 공정을 수행함으로서 소자의 문턱 전압에는 영향을 주지 않고, 단지 채널 부근의 농도만을 높여줌으로서 숏 채널을 소자의 펀치-쓰루전압을 딥이온 주입을 사용하지 않고도 증가시킬 수 있으며, 또한 이 매립층들(14a,14b)은 앤모스쪽과 피모스쪽의 기판 저항을 감소시키는 역할을 해주므로 래치-업을 향상시킨다.At this time, by performing the drive-in process so that the diffusion on the epitaxial layer 13 is increased to 0.3-0.3 μm of the device surface channel, the short channel is increased by only increasing the concentration near the channel without affecting the device's threshold voltage. The punch-through voltage of the device can be increased without the use of deep ion implantation, and the buried layers 14a and 14b also serve to reduce the substrate resistance on the NMOS side and the PMOS side, thus providing latch-up. Improve.

또한, 상기 매립층들(14a,14b)은 아이솔레이션 공정에서 필드산화막과 접촉하게 되므로 완전한 아이솔레이션이 되어 누설전류가 발생할 소지를 없애준다.In addition, since the buried layers 14a and 14b come into contact with the field oxide layer in the isolation process, the buried layers 14a and 14b are completely isolated to eliminate the possibility of leakage current.

상기 매립층의 드라이브-인 공정 이후의 공정은 기존의 시모스 공정과 동일하다.The process after the drive-in process of the buried layer is the same as the conventional CMOS process.

즉, 제 1e 도에 도시된 바와 같이 상기 에피택셜층(13)상에 3000Å 정도의 산화막(15)을 형성하고 N웰 영역을 오픈시킨 다음 N웰 형성용 이온을 주입하고 드라이브-인 공정을 실시하여 N웰(16)을 형성한 후, 제 1f 도에 도시된 바와 같이 통상의 아이솔레이션 공정(Field Photo/Implantation : BF2 3.0E13, 에너지 80KeV/포토레지스터 제거/산화)을 행하여 필드산화막(17)을 형성하고, 제 1g 도에 도시된 바와 같이 게이트를 형성하고 P+영역 및 N+영역을 형성한 후 메탈 공정과 패시베이션 공정을 행한다.That is, as shown in FIG. 1E, an oxide film 15 of about 3000 Å is formed on the epitaxial layer 13, an N well region is opened, an ion for N well formation is implanted, and a drive-in process is performed. After the N well 16 is formed, the field oxide film 17 is formed by performing a conventional isolation process (Field Photo / Implantation: BF2 3.0E13, energy 80KeV / photoresist removal / oxidation) as shown in FIG. 1F. After forming, as shown in FIG. 1G, a gate is formed, a P + region and an N + region are formed, followed by a metal process and a passivation process.

이와 같이 본 발명에 따른 BOE를 이용한 시모스 제조방법은 N+ 매립층과 P+ 매립층을 에피택셜층을 이용하여 형성함으로써 MOS소자중 숏채널 소자에서 야기되는 펀치-쓰루 전압을 높여주고, 또한 이 매립층에 의한 엔모스와 피모스의 기판 저항을 낮춤으로서 래치-업을 향상시킬 수 있으며, 완전한 아이소레이션을 실현할 수 있는 효과를 갖는다.As described above, the CMOS manufacturing method using the BOE according to the present invention forms an N + buried layer and a P + buried layer by using an epitaxial layer to increase the punch-through voltage caused in the short channel device among the MOS devices, and furthermore, By lowering the substrate resistance of MOS and PMOS, latch-up can be improved, and the effect of realizing complete isolation can be achieved.

Claims (5)

반도체 기판상에 P+ 매립층과 N+ 매립층 형성을 위한 이온주입시의 마스크로 되는 산화막을 형성하는 공정과, 상기 반도체 기판에 P+ 매립층 형성을 위한 이온주입과 N+ 매립층 형성을 위한 이온주입을 차례로 실시하는 공정, 및 반도체 기판 전면에 에피택셜층을 성장시킨 후 상기 주입된 이온을 드라이브 인(Drive in)시키는 공정을 포함하는 것을 특징으로 하는 BOE를 이용한 시모스 제조방법.Forming an oxide film serving as a mask for ion implantation for forming a P + buried layer and an N + buried layer on a semiconductor substrate, followed by ion implantation for forming a P + buried layer and ion implantation for forming an N + buried layer in the semiconductor substrate And growing the epitaxial layer on the entire surface of the semiconductor substrate, and then driving the implanted ions into the semiconductor substrate. 제 1 항에 있어서, 상기 P+ 매립층의 주입되는 이온량을 1.0E14-1.0E15, 에너지를 35KeV±20KeV로 한 것을 특징으로 하는 BOE를 이용한 시모스 제조방법.The method of claim 1, wherein the amount of ions implanted into the P + buried layer is 1.0E14-1.0E15, and the energy is 35 KeV ± 20 KeV. 제 1 항에 있어서, N+ 매립층의 주입되는 이온량을 3.0E14-3.0E15, 에너지를 35KeV±20KeV로 한 것을 특징으로 하는 BOE를 이용한 시모스 제조방법.The method of claim 1, wherein the amount of ions implanted into the N + buried layer is 3.0E14-3.0E15 and the energy is 35KeV ± 20KeV. 제 1 항에 있어서, 상기 에피택셜층을 1-5㎛ 정도의 두께로 성장시킴을 특징으로 하는 BOE를 이용한 시모스 제조방법.The method of claim 1, wherein the epitaxial layer is grown to a thickness of about 1-5 μm. 제 1 항에 있어서, 상기 드라이브-인 공정시 P+ 매립층 및 N+ 매립층이 상기 에피택셜층 위로 확산되는 정도가 소자 표면 채널의 0.3-0.5㎛까지 올라가도록 한 것을 특징으로 하는 BOE를 이용한 시모스 제조방법.The method of claim 1, wherein the diffusion of the P + buried layer and the N + buried layer onto the epitaxial layer increases to 0.3-0.5 μm of the device surface channel during the drive-in process.
KR1019900014498A 1990-09-13 1990-09-13 Manufacturing method of cmos using boe KR930008900B1 (en)

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