JPS6024055A - Manufacture of complementary type semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a complementary type device having high latch-up resistant performance and degree of integration by a method wherein an insulating film is applied on a first conduction type semiconductor substrate, the substrate is exposed through selective etching, a second conduction type impurity region is formed to the exposed substrate, a semiconductor layer is grown selectively in an epitaxial manner, an impurity is diffused from the semiconductor layer through heat treatment and a well region is shaped. CONSTITUTION:A fixed number of thick field oxide films 32 are formed on the surface of an N type Si substrate 31, and P type impurity ions in high concentration are implanted into an N channel forming region to form an implantation region 33. The upper section of the region 33 is buried with a P type well region 34 and a section between other films 32 with an N type region 36 through a selective epitaxial method while a P<+> type well region 35, impurity concentration therein is increased slowly in the depth direction, is formed under the heat treating region 34 at that time. N<+> type source and drain regions 39 and 40 are shaped in the region 34 and a gate electrode 38 is further formed through a gate oxide film 37 through a normal method, and the same structure is also formed in the region 36 as a P channel.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a complementary semiconductor device.

[Technical background of the invention and its problems]

A conventional complementary MO8 semiconductor device (hereinafter abbreviated as CMO8) has a structure shown in FIG. In other words, 1 in the figure
is a NW silicon substrate, and a PW well region 2 is selectively provided on this substrate 1. P+ type source/drain regions 364 electrically isolated from each other are provided on the surface of the substrate 1 other than the well region 2, and a dirt oxide film 6 is formed on the substrate 1 between these source/drain regions 3 and 4.
A dart electrode 6 is provided through the . These P type source/drain regions 3.4, dirt oxide film 5, dirt electrode 6, etc. constitute a P channel MO transistor.

On the other hand, N+ type source/drain regions 7.8 are provided on the surface of the P-type well region 20 and are electrically isolated from each other. A dirt electrode 10 is provided with the membrane 9 interposed therebetween.

An N-channel MO transistor is formed by the n-type source/drain regions 11B, the oxide film 9, the dirt electrodes 10, etc. The circuit formed with such 0MO8 is the simplest inverter circuit), the dirt electrodes 6.10 of each transistor are connected with aluminum wiring etc. and become the input vin side, and the P+ type, joint type drain region 4. 8 is also connected with aluminum wiring, etc., and the output is V. It becomes ut. In addition, the P medium-sized source region 3 of the P-channel MO8) transistor and the N-type region (not shown) for applying a substrate bias potential are connected to a source V using aluminum wiring or the like.
Connected to DD. Furthermore, a type 1 source region 7 of the N-channel MO transistor 8) and a P (not shown) for applying a potential are added.
The 10-shaped area refers to the reference power supply V8a, which is caused by aluminum wiring, etc.
It is connected to the.

In the conventional 0MO8 described above, the P-type well region 2 is 1 to 1
Since it has a sheet resistance value of 0Ω, it easily causes a so-called latch-up phenomenon in which a parasitic thyristor turns on, which significantly deteriorates device performance.

This latch-up phenomenon can be prevented by lowering the layer resistance of the P-type well region 2. In order to lower the layer resistance of the P-type well region, it is easiest to increase the junction depth Xρ and increase the concentration. However, xj
If the depth is increased, the controllability of the XJ deteriorates, resulting in a result that goes against the trend toward higher integration. Furthermore, when the concentration is increased, the junction capacitance with the source/drain regions increases, which becomes an obstacle to high performance.

Therefore, in order to eliminate these drawbacks, 0MO8 with the structure shown in Figure 2 has been proposed (D, E, E
str@ich at al,, Int, Electr
on DevicesMeeting Teeh,Dl
g, P, 230, 1978).

That is, in the figure, reference numeral 11 denotes an N-type silicon substrate, and this substrate 11 is coated with an N-type epitaxial layer 12. A P+ type buried layer 13 is selectively provided near the interface between the substrate 1 and the N- type epitaxial layer 12. The surface of the epitaxial layer 12 and the P+ type buried layer 13
A P-type well region 14 is provided between the two. P type source/drain regions 15 and 16 are provided on the surface of the N″″ type epitaxial layer 12 and are electrically isolated from each other. A dirt electrode 18 is provided on the epitaxial layer 12 between these P+ medium-sized source/drain regions 15 and 16 via a dirt oxide film 11f.

Further, in the well region 14, N medium-sized source/drain regions 19 and 20 are provided so as to be electrically isolated from each other. A dart electrode 22 is provided on the well region 14 between these type 1 source/drain regions 19 and 20 with an oxide film 21 interposed therebetween. According to the 0MO8 having such a structure, since the low concentration P type well region 14 is provided on the high concentration P+ type buried layer 13, the relatively high resistance P type well region 14 has a P+ type buried layer on the bottom surface. 13 are coupled in parallel, as a result, the P-type well region 1
4 layer resistance can be reduced.

However, since there is no P+ type buried layer on the side surface of the P-type well region 14 and the resistance remains high, it has the disadvantage that it cannot deal with a latch-up path passing through the side surface of the P-type well region 14.

[Purpose of the invention]

The present invention has been made in view of the above circumstances.
The present invention aims to provide a method for manufacturing a complementary semiconductor device with significantly improved chia-lag performance and a high degree of integration.

[Summary of the invention]

In the method for manufacturing a complementary semiconductor device of the present invention, an insulating film is formed on a semiconductor substrate of a first conductivity type, the substrate is exposed by selective etching, and a high concentration impurity region of a second conductivity type is formed in a part of the insulating film. After the semiconductor layer is formed, a semiconductor layer is selectively epitaxially grown on the exposed substrate, and the impurity is further diffused from the impurity region by heat treatment to form a well region.

According to this method, it is possible to eliminate the latch and f/4 waves passing through the side surface of the well region, and to effectively increase the impurity concentration of the parasitic vertical bipolar transistor, thereby making it possible to improve the complementary semiconductor device in which 7j chiazo is less likely to occur. can be manufactured.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3(IL)-(,) and FIGS. 4(-)-(c)'e.

First, a layer of 1.5 to 2 μm thick is applied to the surface of the N-type silicon substrate 31.
After forming a thermal oxide film, a field oxide film 32 is formed by selectively etching the field oxide film 32 by photolithography, and a part of the substrate 31 is exposed (as shown in FIG. 3).

Next, selectively apply an acceleration energy of 40 keV or more to a portion where an N-channel transistor is to be formed, and a dose of 1X10 to 5X.
Zolon is ion-implanted under the condition of 1015 crn-2 to form a high concentration solon-containing region 33 (as shown in FIG. 3(b)).
. Then selective epitaxial growth techniques (e.g. N,
Endo et al, *Int, E1ectron
Device Meeting Teeh, Dig-P,
241-1982) at 1000°C.

50 Torr= 51) 12Ct2:H2:HCt=
A single crystal silicon layer is selectively epitaxially grown on the exposed substrate 31 under conditions of 0.4:98.6:1 for about 5 minutes until it reaches a thickness equal to that of the field oxide film 32. Next, 30 minutes in a nitrogen atmosphere at 1000°C.
After performing heat treatment for 0 minutes, the high concentration solone containing region 33
Diffusion of the single crystal silicon layer Hepolon on top of P
A type well region 34 and a P+ type buried layer 35 thereunder are formed. Further, the single crystal silicon layer on the substrate 31 becomes an N-type single crystal silicon 7 layer 36. Further, the impurity concentration of the P-type well region 34 is low at the surface and gradually increases in the depth direction (as shown in FIG. 3C). Next, the P-type well region 34
and an r-total electrode 38.38f on the N-type single crystal silicon 7 layer 36 via dirt oxide films 37m and 37k, respectively.
Form. Next, N is selectively applied to the P-type well region 34.
After selectively ion-implanting K-type impurities and P-type impurities into the N-type single crystal silicon 7 layer 36, heat treatment is performed to form N+
The drain region of the I source is 39.40 and the drain region of the P medium source is
Drain regions 41 and 42'ff are formed (as shown in the same figure (d)). Next, a CVD oxide film 4371 of 1 m long is deposited on the entire surface, and then a contact hole 44 is opened. After fully depositing the At film on the entire surface, turning is performed to form the At wiring 45.
and produce CMO8't'' (shown in the same figure (, )).
.

According to the above method, the field oxide film 32t- is formed in the step shown in FIG. After that, a P-type well region 34 is formed by selective epitaxial growth and heat treatment in the step shown in FIG. It has a structure in which a P+ type buried region 35 is formed on the bottom surface. Therefore, in the manufactured 0MO8, the lattice and 7'd' waves passing through the side surface of the P-type reel region 34 cannot be avoided in principle, and the parasitic vertical bipolar transistor is effectively made of silicon with a high impurity concentration. , since the gain is low, latch-up is extremely unlikely to occur. Also,
The device characteristics are better as the impurity concentration of the semiconductor layer is lower, but according to the method of the above embodiment, it is not possible to obtain an ideal impurity distribution in which the surface concentration of the well region 34 is low and gradually increases in the depth direction. Therefore, the device characteristics are significantly improved compared to the conventional technology. Furthermore, in the conventional technology, 5
Since the p- and W-well regions and the substrate are separated by a ~10 μm deep PN junction, it is necessary to leave room for the separation region in consideration of controllability during manufacturing, and the disadvantage is that the degree of integration cannot be increased. However, according to the method of the present invention, the P-type well region 34 and ? The IJ single-crystal silicon layer 36 can be separated through the field oxide film 32f, and since the separation margin for these is determined only by the processing accuracy, the degree of integration can be dramatically improved.

For 0MO8, which has a structure in which the sides of the well region are surrounded by an element isolation insulating film, it is also possible to consider a method in which, for example, a part of the silicon substrate is selectively etched to form a groove, and then an insulating film is buried in this groove. However, it is difficult to embed the insulating film in the trench in a state in which it is in complete contact with the trench, and problems of its own arise especially when the trench has a large area, so this method cannot be said to be a preferable method.

Example 2 First, a layer with a thickness of 1.5 to 2 μm is formed on the surface of an N-type silicon substrate 51.
After forming a thermal oxide film, a part of it is selectively etched by photolithography to form a field oxide film 52, exposing a part of the substrate 5 (as shown in FIG. 4(a)). ).

Next, selectively apply an acceleration energy of 40 keV or more to a portion where an N-channel transistor is to be formed, and a dose of 1×1015.
A high-concentration poron-containing region 53 is formed by ion-implanting poron under conditions of ˜5×110 15 C''. Next, selectively apply an acceleration energy of 40 keV or more to the area where the P-channel transistor is to be formed, at a dose of 1 x 10 to 5 x 10 α.
High-concentration phosphorus-containing region 5 is formed by ion-implanting phosphorus under the following conditions.
4 (as shown in FIG. 4(b)).

Next, using the selective epitaxial technique as in Example 1, a single crystal silicon layer is selectively epitaxially grown on the exposed substrate 3 by luma to a thickness equal to that of the field oxide film 32. Subsequently, heat treatment is performed for 300 minutes in a nitrogen atmosphere at 1000° C. to diffuse boron and phosphorus from the high-concentration boron-containing region 53 and the high-concentration phosphorus-containing region 54, respectively, thereby forming a P-type well region 55. Below that, P+ type buried region 56, N type single crystal 7
Form the 937 layer 52 and the furnace-type buried region 58 thereunder (as shown in FIG.
P-channel transistors are formed in each N-type single crystal silicon layer and CMO8'i is manufactured.However, the method of the second embodiment described above can also obtain the same effect as the first embodiment. Further, since the impurity concentration of the N-type single crystal silicon 7 layer 57 can be distributed such that it is low at the surface and gradually increases in the depth direction, the device characteristics can be further improved.

In addition, to manufacture a CMO8''f having the same structure as in Examples 1 and 2, for example, after forming a field oxide film on an N-type silicon substrate in the same manner as in the process shown in FIG.
A single crystal silicon layer is formed on the exposed substrate using selective epitaxial technology, and then P-type impurities are ion-implanted into the area where the N-channel transistor is to be formed, and N-type impurity is ion-implanted into the area where the P-channel transistor is to be formed, followed by heat treatment. You can also do this.

According to this method, the impurity 9 degree distribution in the P-type well region and the N-type single crystal silicon layer is slightly different from that in Examples 1 and 2, but it is almost the same as in Examples 1 and 2. effect can be obtained.

Further, in Examples 1 and 2, the P-type well region is formed on the N-type silicon substrate, but the present invention is not limited to this, and the present invention can of course be similarly applied to the case where the N-type well region is formed on the P-type silicon substrate. Similar effects can be obtained by using antimony, arsenic, etc. as N-type impurities.In addition, in Examples 1 and 2 above, ion implantation was used to fully dope the impurities, but this is not limited to this. Even if conventional techniques such as coating methods are used, the effects remain the same.

In addition, in Examples 1 and 2 above, silicon dioxide was used as the insulating film for element isolation, but it is not limited to this, and any insulating material may be used, such as silicon nitride, intrinsic silicon, or a laminated structure of these and silicon dioxide. The effect remains unchanged.

Furthermore, in Examples 1 and 2 above, the optimal thickness of the single crystal silicon layer to be formed was 1.5 to 2.0 μm, but if the process design is optimized, a thickness of 0.6 to 3.0 μm can also be used. The effect remains the same. In addition, the main purpose of heat treatment after all impurity ion implantation is to redistribute impurities in single crystal silicon, so even if the heat treatment temperature (temperature, time) and atmosphere are changed,
If you optimize it, the effect will not change.

〔Effect of the invention〕

As described in detail above, according to the method for manufacturing a complementary semiconductor device of the present invention, there are remarkable effects such as significantly improving the chia and zo performance of the complementary semiconductor device and enabling high integration. .

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional views of a conventional CMO8, respectively.
Figure 3 (,) to (,) are CMs in Example 1 of the present invention.
4(a) to 4(c) are cross-sectional views showing a method for manufacturing CMO8 in Example 2 of the present invention. 31.51...N-type silicon substrate, 32.52...
Field oxidation 7g, 3g, 1; 3... High concentration zolon containing region, 34.55... P-type well region, 35.5
6...P ten-shaped buried region, 36.57...N-type single crystal silicon layer, 37...dirt oxide film, 38--dart electrode, 39.40...joint-type second train region,
41.42...P ten type drain region, 43.
...CVD oxide film, 44...contact hole, 45
...At wiring, 54...High concentration phosphorus containing region, 58
...N-type embedded area. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (2)

[Claims] (1) forming an insulating film on the surface of a first conductivity type semiconductor substrate;
selectively removing a portion of the insulating film to expose the substrate; and selectively forming a second conductivity type high concentration impurity region on a portion of the surface of the exposed substrate. ,
A complementary method comprising the steps of selectively epitaxially growing a semiconductor layer on the exposed substrate, and diffusing impurities from the impurity region by heat treatment to form a well region of a second conductivity type. A method for manufacturing a type semiconductor device. (2) A method for manufacturing a complementary semiconductor device according to claim 1, characterized in that the impurity concentration of the well region is low at the surface and high at the deep part.