JP2750924B2 - Complementary field effect element and method of manufacturing the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary field effect device and a method of manufacturing the same, and more particularly, to a field effect device formed adjacent to each other on a main surface of a first conductivity type semiconductor substrate. The present invention relates to a complementary field effect element having an impurity layer of one conductivity type and an impurity layer of a second conductivity type, and a method for manufacturing the same.

[Prior Art] Conventionally, in a CMOS circuit, a parasitic bipolar transistor becomes conductive and latch-up in which a large current flows between power supply terminals of the CMOS circuit has been a problem. When this latch-up occurs, there arises a disadvantage that a circuit operation is hindered or the IC itself is destroyed. Therefore, various methods have conventionally been considered to prevent latch-up.

FIGS. 6A to 6M are cross-sectional structural views for illustrating a manufacturing process of a conventional CMOS circuit in which measures against latch-up are taken. With reference to FIGS. 6A to 6M, a description will be given of a conventional process of manufacturing a CMOS circuit in which measures against latch-up are taken. First, as shown in FIG. 6A, an oxide film 21 made of SiO ₂ is formed on a P-type silicon substrate 1. Oxide film 21
A nitride film 22 made of Si ₃ N ₄ is formed thereon. Boron B ⁺ is implanted from above the nitride film 22 at a high energy by an ion implantation method. Thereby, p ⁺ for preventing latch-up
A buried layer 15 is formed. Next, as shown in FIG. 6B, a resist 23 is patterned on the nitride film 22. Resist 23
Is used as a mask to etch nitride film 22. Next, 6C
As shown in the figure, the resist 23 is removed. Thermal oxidation is performed using nitride film 22 as a mask. As a result, LOCOS (Local Oxidatio of Silic
on) Isolation and activation of p ⁺ buried layer 15 are performed. After that, the nitride film 22 is removed. Next, as shown in FIG. 6D, a resist 25 is formed. Using the resist 25 as a mask, phosphorus P ⁺ is implanted at a high energy by an ion implantation method. Thereby, N well 3 is formed. At the same time, by implanting phosphorus P ⁺ with low energy, a V _TH control implantation region 26 is formed. Next, as shown in FIG. 6E, a resist is patterned in a portion other than the region where the P well 2 is to be formed. Using resist 27 as a mask, boron B ⁺ is implanted at high energy. As a result, a P well 2 is formed. By implanting boron B ⁺ at a low energy at the same time as the formation of the P well 2 and the formation of the P well 2, the _VTH control implantation region 28 is formed. Next, as shown in FIG. 6F, the resist 27 is removed. Thereby, the well region of the CMOS circuit is formed. Next, as shown in FIG. 6G, the oxide film 21 is removed. As shown in FIG. 6H, the oxide film
A gate oxide film 30 is formed in a region where 21 has been removed. As shown in FIG. 6I, a polysilicon film 31 serving as a gate electrode is formed on the gate oxide film 30. Next, as shown in FIG.
Finally, the gate oxide film 30 and the polysilicon film 31 formed in regions other than the regions where the gate oxide films 10 and 12 and the gate electrodes 11 and 13 are formed are etched using photolithography. As shown in FIG. 6K, the resist is formed in a region other than the region where the n ⁺ diffusion layers 4, 5 serving as the source and drain of the P well 2 and the n ⁺ diffusion layer 9 for fixing the well potential of the N well 3 are formed. Form 32. As ⁺ is implanted using the resist 32 as a mask. Thus, n ⁺ diffusion layers 4 and 5 of P well 2 and n ⁺ diffusion layer 9 of N well 3 are formed. Next, the 6L
As shown in the figure, the resist 32 is removed. A resist 33 is formed in a region other than the region where the p ⁺ diffusion layers 7, 8 serving as the source and drain of the N well 3 and the p ⁺ diffusion layer 6 for fixing the well potential of the P well 2 are formed. Using the resist 33 as a mask, boron B ⁺ is ion-implanted. Thereby, the p ⁺ diffusion layers 7 and 8 of the N well 3 and the p ⁺
The diffusion layer 6 is formed. Finally, as shown in FIG. 6M,
The resist 33 is removed and a source / drain drive is performed to activate impurities. At the same time, the N well 3 and the P well 2 are also activated. In this way, a conventional CMOS circuit that has taken measures against latch-up is formed.

FIG. 7 is a schematic diagram for explaining a configuration of a parasitic bipolar transistor and a resistance component of the CMOS circuit shown in FIG. 6M. With reference to FIG. 7, a conventional latch-up measure will be described. First, an operation in which latch-up occurs will be described. For example, holes may be generated in P well 2 as hot carriers. This hole flows through the N ⁺ diffusion layers 4 and 5 in the P well 2 into the NPN transistors 103 and 104.
, And a collector current of a current amplification factor times that of the base current flows. That is, current flows from N well 3 to n ⁺ diffusion layers 4 and 5 in P well 2.
At this time, current hardly flows from p ⁺ diffusion layers 7 and 8 in N well 3 due to the diffusion potential with N well 3. When the N-well 3 within n ⁺ diffusion layer 9 from the n ⁺ diffusion layer 9 in the P-well 3 at a current flows to the P-well 2, a current flows through the resistor 201. Due to this current, the voltage generated across the resistor 201 raises the base potential of the PNP transistors 101 and 102,
Turn on the PNP transistors 101 and 102. PNP transistor 1
When the transistors 01 and 102 are turned on, a current flows through the P-type silicon substrate 1, which is a collector of the PNP transistors 101 and 102, and finally a current flows through the p ⁺ diffusion layer 6 in the P well 2. Since this current flows through the resistor 202, a voltage is generated across the resistor 202. This voltage is applied to NPN transistors 103 and 104
NPN transistors 103 and 104
Collector current increases. As a result, the current flowing through the resistor 201 increases more and more. In this way, in the state where the positive feedback is applied, a large current remains flowing between V _DD and V _SS irrespective of the current caused by the hole as the hot carrier which initially triggered.
Latch-up occurs in this manner. Also,
As described above, even if carriers are not initially generated as described above, for example, the voltage of the n ⁺ diffusion layer 5 in the P well 2 becomes lower than V _SS or N
This occurs even when the voltage of the p ⁺ diffusion layer 8 in the well 3 becomes higher than V _DD .

Conventionally, to prevent such latch-up,
The p ⁺ diffusion layer 15 shown in FIG. 6M was formed. Thereby, the resistance value of the resistor 202 can be reduced. Therefore, even if the same current flows from the p ⁺ diffusion layers 7 and 8 in the N well 3 to the p ⁺ diffusion layer 6 in the P well 2 through the P-type silicon substrate 1, the voltage generated at both ends of the resistor 202. Becomes smaller. As a result, there is an effect that the NPN transistors 103 and 104 are hardly turned on. Further, since p ⁺ buried layer 15 is formed in a region corresponding to the bases of NPN transistors 103 and 104, there is also an effect of reducing the gain of NPN transistors 103 and 104. As described above, conventionally, by forming the p ⁺ buried layer 15 in a direction along the main surface of the P-type silicon substrate 1 in a region deeper than the P-well 2 and the N-well 3 of the P-type silicon substrate 1, the NPN The resistance value of the resistor 202, which causes the base potential of the transistors 103 and 104 to rise and turn on, is reduced, and the gain of the NPN transistors 103 and 104 is reduced to prevent latch-up.

[Problems to be Solved by the Invention] As described above, in the conventional CMOS circuit, the p ⁺ buried layer 15 is formed in a region deeper than the region where the P well 2 and the N well 3 of the P-type semiconductor substrate 1 are formed. By forming
Latch-up was prevented. That is, the resistance 202 which causes the base potential of the NPN transistors 103 and 104 to rise
The resistance value of the NPN transistors 103 and 104 is made difficult to turn on by lowering the resistance value of the NPN transistors 103 and 104, and the latch-up is prevented by reducing the gain of the NPN transistors 103 and 104.

However, when the CMOS circuit is miniaturized and the distance between the p ⁺ diffusion layer 7 of the N well 3 and the n ⁺ diffusion layer 4 of the P well 2 is narrowed, P
Carriers flowing through the NP transistors 101 and 102 pass through the wall surfaces of the N well 3 and the P well 2 more easily than pass through the p ⁺ buried layer 15. As a result, there is a disadvantage that the effect of the p ⁺ buried layer 15 is significantly reduced.

That is, the collector currents of PNP transistors 101 and 102 pass through the wall between N well 3 and P well 2 without flowing through p ⁺ buried layer 15 and flow into P well 2. And
Finally, it flows to the p ⁺ diffusion layer 6 in the P well 2. In this current path, the base potential of the NPN transistors 103 and 104 is increased by a new resistor (not shown) in the P well 2.
Since it is turned on, even if the resistance value of the resistor 202 is reduced by the p ⁺ buried layer 15, there is no effect of making it difficult to turn on the NPN transistors 103 and 104. Also, NPN transistor 1
Since the current flowing to the bases of the transistors 03 and 104 does not pass through the p ⁺ buried layer 15, the effect of lowering the gain of the NPN transistors 103 and 104 is lost. Therefore, there is a new inconvenience that the gains of the NPN transistors 103 and 104 become larger than when the transistors pass through the p ⁺ buried layer 15. As a result, there is a problem that latch-up cannot be effectively prevented.

In other words, in the conventional CMOS circuit with the latch-up countermeasures, when the distance between the emitters of the parasitic transistor becomes small, the carrier of the current flowing through the PNP transistor becomes p ⁺
Since the holes pass through the well side without passing through the buried layer, there is a problem that latch-up cannot be effectively prevented depending on the p ⁺ buried layer 15.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a complementary field effect element capable of obtaining a strong latch-up resistance even when the distance between the emitters of a parasitic transistor is short, and a method of manufacturing the same. The purpose is to:

[Means for Solving the Problems] According to the invention of claim 1, a first conductivity type well region and a second conductivity type well region formed adjacent to each other on a main surface of a first conductivity type semiconductor substrate are formed. Complementary field effect element having a high concentration buried layer and a high concentration impurity layer. The high-concentration buried layer is a region deeper than a region where the first conductivity type well region and the second conductivity type well region of the first conductivity type semiconductor substrate are formed, and is formed in the first and second conductivity type well regions. A region formed at a depth separated from the bottom surface by a predetermined distance in the depth direction is formed so as to be embedded in the semiconductor substrate at a predetermined depth from the main surface of the first conductivity type semiconductor substrate. I have. The high-concentration buried layer is formed so as to extend over the entirety of the semiconductor substrate in a direction along the main surface of the first conductivity type semiconductor substrate, and is formed by ion implantation, and has a higher impurity concentration than the semiconductor substrate. And has the same first conductivity type as the semiconductor substrate. The high-concentration impurity layer is formed by ion implantation in a boundary region between the well region of the first conductivity type and the well region of the second conductivity type. It is formed to extend to the layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a complementary field effect element having a first conductivity type impurity layer and a second conductivity type impurity layer formed adjacent to each other on a main surface of a first conductivity type semiconductor substrate. And includes the following two steps.

A predetermined depth from the main surface of the first conductivity type semiconductor substrate in a region deeper than a region where the first conductivity type impurity layer and the second conductivity type impurity layer of the first conductivity type semiconductor substrate are formed; And forming the first conductivity type high-concentration buried layer extending in the direction along the main surface of the first conductivity type semiconductor substrate by ion implantation.

By using a resist having the same pattern shape as one of the resist used when forming the first conductivity type impurity layer and the resist used when forming the second conductivity type impurity layer, By ion-implanting with the same implantation strength as when forming the high concentration buried layer of the first conductivity type in the boundary region of the region where the impurity layer of the first conductivity type and the impurity layer of the second conductivity type are formed. Forming a high concentration impurity layer;

[Operation] In the complementary field effect element according to claim 1, the first conductive type semiconductor substrate is formed along the main surface of the first conductive type semiconductor substrate in a region having a depth separated by a predetermined distance from the bottom surface of the first and second conductive type well regions. A high-concentration buried layer of the same conductivity type as that of the semiconductor substrate having a higher impurity concentration than the semiconductor substrate extending over the entire semiconductor substrate in the direction perpendicular to the semiconductor substrate is formed. The high-concentration impurity layer extending to the embedded layer is formed, so that the first-conductivity-type well region and the second-conductivity-type well region are completely separated by the high-concentration buried layer and high-concentration impurity layer. As well as being separated, the first conductivity type well region and the second conductivity type well region each have a shape surrounded by a high concentration buried layer and a high concentration impurity layer. Therefore, the first
The high-concentration buried layer and the high-concentration impurity layer can effectively prevent carriers in one of the well regions of the conductivity type or the well region of the second conductivity type from invading the other well region. Become. Specifically, for example, carriers from the diffusion layer in one well region try to reach the diffusion layer in the other well region via the lateral and downward directions, but the high concentration impurity layer and the high concentration buried layer Since one and the other diffusion layers are completely surrounded, carriers from the diffusion layer in one well region reach the diffusion layer in the other well region with the high-concentration impurity layer and the high-concentration buried layer acting as obstacles. It becomes difficult. This makes it possible to effectively prevent latch-up. Also,
According to the first aspect of the present invention, since the high-concentration buried layer is formed so as to be buried with a predetermined width in the depth direction inside the semiconductor substrate, the high concentration buried layer extends downward from the diffusion layer in one well region. When the carrier heading toward the diffusion layer in the other well region attempts to reach the semiconductor substrate through the high-concentration buried layer, it must penetrate the high-concentration buried layer again and head upward. Since it is necessary to pass through the high-concentration buried layer twice, it is very difficult for carriers to reach the diffusion layer in the other well region by this route. For example, when the semiconductor substrate itself is made to have a high concentration without providing a high-concentration buried layer, carriers traveling downward from the diffusion layer in one well region pass through the high-concentration semiconductor substrate only once, and then the other. Since it is possible to go to the diffusion layer in the well region, carriers are more likely to pass than in the configuration in which the high concentration buried layer of the present invention is provided with a predetermined width inside the semiconductor substrate, and the effect of preventing latch-up is low. I can say that. Therefore, the configuration of the present invention in which the high-concentration buried layer is extended to the entire semiconductor substrate with a predetermined width inside the semiconductor substrate can prevent latch-up more effectively than when the entire semiconductor substrate is high-concentration. Is possible.

In the method for manufacturing a complementary field effect element according to claim 2,
A resist having the same pattern shape as one of the resist used when forming the first conductive type impurity layer and the resist used when forming the second conductive type impurity layer is used. Since a high-concentration impurity layer is formed in a boundary region between the one-conductivity-type impurity layer and the second-conductivity-type impurity layer, a resist forming pattern for forming a resist when forming the high-concentration impurity layer is newly provided. Need not be added to

[Embodiment of the Invention] FIG. 1 is a cross-sectional structural view of a CMOS circuit provided with a latch-up countermeasure according to an embodiment of the present invention. Referring to FIG. 1, a CMOS circuit is formed on a P-type silicon substrate 1, a P-well 2 and an N-well 3 formed adjacently on the P-type silicon substrate 1, and an N-type N ⁺ diffusion layers 4, 5 serving as source and drain regions of channel transistor
If, formed on the P-well 2, the p ⁺ diffusion layer 6 for fixing the well potential of the P-well 2 is formed on the N-well 3, p ⁺ diffusion layer serving as the source and drain regions of the P-channel transistor 7, 8 and formed on the N-well 3,
N ⁺ diffusion layer 9 for fixing the well potential of N well 3
A gate electrode 11 formed between n ⁺ diffusion layers 4 and 5 on P well 2 via gate oxide film 10, and a gate oxide film between p ⁺ diffusion layers 7 and 8 on N well 3. 12, a field oxide film 14 for element isolation formed between the n ⁺ diffusion layer 4 and the p ⁺ diffusion layer 7, and a P well 2 of the P-type silicon substrate 1. The region deeper than N well 3 includes p ⁺ buried layer 15 formed along the main surface and p ⁺ high concentration layer 16 formed at the boundary region between P well 2 and N well 3.

FIG. 2 is a schematic diagram for explaining parasitic transistors and resistance components of the CMOS circuit shown in FIG. Second
Referring to the drawing, in the present embodiment, N well 3 of P well 2
By forming the p ⁺ high-concentration layer 16 in a region adjacent to the NPN transistors 103 and 104, the concentration on the collector side of the NPN transistors 103 and 104 is increased and the gain of the NPN transistors 103 and 104 is reduced.
Thereby, p ⁺ diffusion layer 7 in N well 3 and P well 2
When the distance between the n ⁺ diffusion layer 4 and the n ⁺ diffusion layer 4 becomes narrow, the carriers flowing through the PNP transistors 101 and 102 pass through the side surface of the N well 3 without passing through the p ⁺ diffusion layer 15 and p ⁺ A current path reaching the diffusion layer 6 is formed, and the NPN
Even if the transistors 103 and 104 are turned on, the collector currents of the NPN transistors 103 and 104 do not increase so much. As a result, the current flowing through the resistor 201 is reduced, and the PNP transistors 101 and 102 are hardly turned on.

Thus, in the present embodiment, the N well 3 of the P well 2
By forming p ⁺ high concentration layer 16 at the boundary between
A resistor 2 that reduces the gain of the transistors 103 and 104 and raises the base potential of the PNP transistors 101 and 102
Since the current flowing through 01 is reduced, it becomes difficult to turn on the PNP transistor. As a result, NPN transistors 103 and 104
Therefore, latch-up can be effectively prevented even when the emitters of the parasitic transistors are close to each other.

3A to 3L are cross-sectional structural views for explaining a manufacturing process of the CMOS circuit shown in FIG. The structural process will be described with reference to FIGS. 3A to 3L. First, as shown in FIG. 3A, an oxide film 21 made of SiO ₂ is formed on a P-type silicon substrate 1. Si ₃ on oxide film 21
A nitride film 22 made of N ₄ is formed. Thereafter, boron B ⁺ is implanted at a high energy by an ion implantation method to form a p ⁺ buried layer 15.
To form Next, as shown in FIG. 3B, a P-well resist mask 27 which is the same as a P-well resist mask 27 used for forming a P-well 2 described later on the nitride film 22 is patterned. Using the P-well resist mask 27 as a mask, boron B ⁺ is, for example, 200 keV to 10 MeV, 1 × 10 ¹² to
Ions are implanted under the condition of 1 × 10 ¹⁵ cm ⁻² . By this ion implantation, B ⁺ ions incident from the middle of the cross section of the P-well resist mask 27 pass through the P-well resist mask 27 and are re-implanted into the P-type silicon substrate 1. Further, boron B ⁺ implanted into the edge of the P-well resist mask 27 and coming out of the middle of the cross section of the P-well resist mask 27 is again implanted into the P-type silicon substrate 1. As a result, the p ⁺ high concentration layer 16 is formed at the boundary between the P well 2 and the N well 3 which will be formed in a process described later with the edge cross section of the P well resist mask 27 as the center. Next, as shown in FIG. 3C, a resist 23 is patterned on a region of the nitride film 22 other than a region where an element is formed. The nitride film 22 is etched using the resist 23 as a mask. Next, as shown in FIG. 3D, the resist 23 is removed. By performing thermal oxidation using the nitride film 22 as a mask, the field oxide film
14 is formed to perform LOCOS (Local Oxidation of Silicon) isolation and activate the p ⁺ indentation layer 15 and the p ⁺ high concentration layer 16. After that, the nitride film 22 is removed. Next, 3E
As shown in the figure, a resist 25 is patterned on a region other than a region where an N well is formed. An N well is formed by ion-implanting phosphorus P ⁺ with high energy using the resist 25 as a mask. At the same time, phosphorus P ⁺ is ion-implanted at a low energy, so that a _VTH control implantation region is formed.
Form 26. Next, as shown in FIG. 3F, after removing the resist 25, the P
The well resist mask 27 is patterned. Using the P-well resist mask 27 as a mask, boron P ⁺ is ion-implanted at a high energy to form a P-well 2.
At the same time, V _TH control implantation region 28 is formed by ion implantation of boron B ⁺ with low energy. As shown in FIG. 3G, after removing the resist 29, the oxide film 21 is removed. As shown in FIG. 3H, a gate oxide film 30 is formed in a region where the oxide film 21 has been removed. As shown in FIG. 3I, a polysilicon film 31 serving as a gate electrode is formed on the gate oxide film 30 and the field oxide film 14. As shown in FIG. 3J, the gate oxide films 10 and 12 and the gate oxide film 30 and the polysilicon film 31 other than the regions to be the gate electrodes 11 and 13 are etched using photolithography. Next, as shown in 3K view, the source of the P-well 2, the drain region n ⁺ diffusion layer 4, 5 and N for fixing the well potential n ⁺
The resist 32 is patterned except for the region where the diffusion layer 9 is to be formed. As ⁺ is ion-implanted using the resist 32 as a mask. Thus, n ⁺ diffusion layer 9 for fixing the source of the P-well 2, the well potential of the n ⁺ diffusion 4,5 and N-well 3 to be a drain region is formed. Next, the third L
As shown in the figure, a resist 33 is applied to regions other than regions where p ⁺ diffusion layers 7 and 8 serving as source and drain regions of N well 3 and p ⁺ diffusion layer 6 for fixing the well potential of P well 2 are formed. Perform patterning. Using the resist 33 as a mask, boron B ⁺ is ion-implanted. Thus, p ⁺ diffusion layers 7 and 8 serving as source and drain regions of N well 3 and p ⁺ diffusion layer 6 for fixing the well potential of P well 2 are formed. Finally, as shown in FIG. 1, the resist 33 is removed and a source / drain drive is performed to activate impurities. At the same time, the P well 2 and the N well 3 are activated. In this manner, a CMOS circuit with the latch-up countermeasures of the present embodiment is formed. In the present embodiment, it is possible to use a P-well resist mask 27 used to form the P-well 2 at the time of forming the high concentration buried layer 16, when forming the p ⁺ high concentration layer 16 It is not necessary to newly add a resist forming pattern for forming a resist used for the above.

In this embodiment, the p ⁺ buried layer 15 is implanted and formed before the field oxide film 14 is formed, but may be implanted after the field oxide film 14 is formed. Further, in the embodiment, the p ⁺ high-concentration layer 16 is formed by using a resist having the same pattern shape as the resist for forming the P well.
The present invention is not limited thereto, using the resist of the resist and the same pattern for N-well formed p ⁺ high concentration layer 16
May be formed.

FIGS. 4 and 5 are sectional structural views of a CMOS circuit provided with a latch-up countermeasure according to another embodiment of the present invention. Referring to FIG. 4, even if n ⁺ high concentration layer 17 is formed in the boundary region between N well 3 and P well 2, the CMO shown in FIG.
An effect similar to that of the S circuit can be obtained. Referring to FIG.
Both the p ⁺ high concentration layer 16 is formed in the well 2 and the n ⁺ high concentration layer 17 is formed in the N well 3. Even in this case, the first
As in the case of the CMOS circuit shown in the figure, latch-up can be effectively prevented even when the emitters of the parasitic transistors are close to each other.

[Effects of the Invention] As described above, according to the first aspect of the present invention, the high-concentration buried layer provided to extend over the entire semiconductor substrate in a direction along the main surface of the semiconductor substrate and the first buried layer. And a high-concentration impurity layer provided so as to reach the high-concentration buried layer at the boundary region between the well regions of the second conductivity type, so that carriers in one well region pass through the boundary region between the two well regions. And the carrier from one well region can be effectively prevented from passing under the well region and entering the other well region, thereby significantly improving the latch-up resistance. Can be improved.

According to the second aspect of the present invention, one of a resist used when forming the first conductivity type impurity layer and a resist used when forming the second conductivity type impurity layer is used. A resist for forming a resist for forming a high-concentration impurity layer by forming a high-concentration impurity layer in a boundary region between the first and second conductivity-type impurity layers using a resist having the same pattern shape. Since a high-concentration impurity layer can be formed without newly adding a forming pattern, a method for manufacturing a complementary field effect element capable of easily forming a high-concentration impurity layer without complicating a manufacturing apparatus is provided. can do.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a CMOS circuit provided with a latch-up countermeasure according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining parasitic transistors and resistance components of the CMOS circuit shown in FIG. Schematic diagrams, FIGS. 3A to 3L are shown in FIG.
Cross-sectional structure diagram for explaining the manufacturing process of the CMOS circuit,
4 and 5 are sectional structural views of a latch-up countermeasure CMOS circuit showing another embodiment of the present invention, and FIGS. 6A to 6M are diagrams of a conventional latch-up countermeasure CMOS circuit. FIG. 7 is a schematic diagram for explaining a parasitic transistor and a resistance component of the CMOS circuit shown in FIG. 6M. In the figure, 1 is a P-type silicon substrate, 2 is a P well, 3
Is an N well, 4, 5, 9 are n ⁺ diffusion layers, 6, 7, 8 are p ⁺ diffusion layers, 10
Is a gate oxide film, 11 is a gate electrode, 12 is a gate oxide film,
13 is a gate electrode, 14 is a field oxide film, 15 is a p ⁺ buried layer, 16 is a p ⁺ high concentration layer, 17 is an n ⁺ high concentration layer, 101 is a PNP transistor, 102 is a PNP transistor, 103 is an NPN transistor, 104 is an NPN transistor, 201 is a resistor, and 202 is a resistor. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A complementary field effect element having a first conductivity type well region and a second conductivity type well region formed adjacent to each other on a main surface of a first conductivity type semiconductor substrate, A region deeper than a region where the first conductivity type well region and the second conductivity type well region of the first conductivity type semiconductor substrate are formed, and a depth from a bottom surface of the first and second conductivity type well regions; Embedded in the semiconductor substrate at a predetermined depth from a main surface of the semiconductor substrate of the first conductivity type in a region having a depth separated by a predetermined distance in the direction, and the first conductivity type. A high-concentration buried layer of the same first conductivity type as the semiconductor substrate having a higher impurity concentration than the semiconductor substrate formed by ion implantation, extending over the entire semiconductor substrate in a direction along a main surface of the semiconductor substrate; The first conductive type Is formed by ion implantation in a boundary region between the well region of the second conductivity type and the well region of the second conductivity type, and is formed to extend from the main surface of the semiconductor substrate to the high concentration buried layer in the boundary region. A complementary field effect element including a high-concentration impurity layer. 2. A structure method of a complementary field effect element having a first conductivity type impurity layer and a second conductivity type impurity layer formed adjacent to each other on a main surface of a first conductivity type semiconductor substrate. A predetermined region from a main surface of the first conductivity type semiconductor substrate in a region deeper than a region where the first conductivity type impurity layer and the second conductivity type impurity layer of the first conductivity type semiconductor substrate are formed; Forming a high-concentration buried layer of a first conductivity type at a predetermined depth and extending in a direction along a main surface of the first conductivity type semiconductor substrate by ion implantation; Using a resist having the same pattern shape as one of the resist used when forming the conductive type impurity layer and the resist used when forming the second conductive type impurity layer, Of the first conductivity type By implanting ions with the same implantation strength as when forming the first-conductivity-type high-concentration buried layer in the boundary region between the region where the pure layer and the second-conductivity-type impurity layer are formed, high-concentration ion implantation is performed. Forming an impurity layer.