JPS61124165A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To integrate and to reduce a latchup by forming a conductive type well region to oppose from the surface of the second separate epitaxial layer to the third buried diffused region, and forming a MIS field effect transistor in the second layer. CONSTITUTION:An N type buried layer 2 and a P type buried layer 3 are formed in an N type silicon substrate 1, a P type epitaxial layer 4 is grown, an N type deep diffused layer 5 is diffused, and separated into the first separate epitaxial layer 6 and the second epitaxial layer 7. Further, an N type well layer 8 is formed from the surface of the layer 7 onto the layer 3. P type boron ions are implanted to the regions of source 17 and drain 18. N type phosphorous ions are implanted to the regions of the source 20 and the drain 21 of an N- channel MNOS memory transistor, an interlayer insulating film is then formed, a contacting hole, metal wiring layer and a protective film are formed to form a CMOS circuit. Thus, the separating diffusing depth from the epitaxial layer can be formed to be shallow, the lateral diffusion is suppressed, and the integration of the memory is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the manufacture of semiconductor devices with a metal-insulator-semiconductor (hereinafter referred to as MIS) type nonvolatile memory element that can achieve higher integration and higher performance. It is about the method.

Conventional technologyWith the advancement of LSI technology, the performance of semiconductor integrated circuits has improved,
As functionality continues to advance, electrically rewritable ROM (1!: EF
There is an increasing demand for a device that can coexist with control circuit functions such as a ROM (ROM) and a microcomputer. For example, as an MIS type nonvolatile memory element, a nonvolatile MNOS (metal-silicon nitride film-silicon oxide film-semiconductor) structure in which a silicon nitride film is formed on a thin silicon oxide film and a metal electrode is formed on top of the silicon nitride film is used. Memory transistors are well known, and a 1-chip microcontroller with built-in MNOS memory coexists on the same chip with a memory circuit section using MNOS memory transistors and a control circuit that controls the memory circuit shown on page 3. The need for computers is increasing.

In a semiconductor device in which a memory circuit section consisting of an MIS-type non-type gold volatile memory element and a peripheral circuit section consisting of an MIS-type field effect transistor coexist on the same substrate, the peripheral circuits other than the memory are placed on the same chip. Due to integration, the power consumption of the chip increases, which causes the temperature of the chip to rise, which adversely affects the memory retention characteristics of the nonvolatile memory transistors coexisting on the same chip.To prevent this, the peripheral circuitry should be designed as much as possible. cMos enables low power consumption
(complementary MO8).

Problems to be Solved by the Invention As mentioned above, in semiconductor devices in which a nonvolatile memory element and an 0M03 circuit coexist on the same chip, in recent years, as the scale of the system has increased, higher integration and higher performance have been required. In order to meet these demands, it has become necessary to miniaturize the dimensions of the memory circuit section and the CMO8 circuit section. However, in a semiconductor device in which a conventional nonvolatile memory element and a 0M08 circuit coexist on the same chip, the depletion layer of the 0M08 well region and the depletion layer of the substrate become close to each other, so that the well region and the substrate do not have the same potential. In order to achieve this, it is necessary to make the total thickness of the epitaxial layer sufficiently thick (usually about 16 μm), but increasing the thickness of the epitaxial layer increases the area required for separating the memory circuit section, resulting in an increase in the height of the memory circuit section. Integration becomes difficult. On the other hand, with the miniaturization of dimensions, cMosu paths become more susceptible to latch-up phenomena, and in conventional (3MO8 integrated circuits) a structure in which a guard band is provided is used as a measure to prevent latch-up. However, as miniaturization progresses and the epitaxial layer is made thinner to increase the degree of integration of the memory circuit, the parasitic thyristors in the vertical direction of the CMO8 circuit become more likely to operate. It is necessary to prevent this.

Therefore, in order to increase the integration and performance of semiconductor devices in which non-volatile memory elements and 0M08 circuits coexist on the same chip,
At the same time as making the epitaxial layer thinner, it has become necessary to take measures against latch-up.

The present invention has been made in view of the above problems, and an object thereof is to achieve high integration and reduce latch-up in a semiconductor device in which MIS type non-type gold volatile memory element 0M03 circuit coexists on the same chip. The present invention provides a method for manufacturing a semiconductor device for the purpose of.

Means for Solving the Problems In order to achieve the above object, the present invention provides a first semiconductor substrate of the same conductivity type on a -conductivity type semiconductor substrate. forming a second buried diffusion region and a third buried diffusion region of opposite conductivity type, forming an epitaxial layer of opposite conductivity type on the substrate, starting from the surface of the epitaxial layer to the first buried diffusion region; The first . of the same conductivity type reaching the second buried diffusion region. A first . separated by a second diffusion region. forming a second isolated epitaxial layer;
Step of forming IS type non-type gold volatile memory element, page 6 Forming a well region of the same conductivity type as the substrate so as to face the third buried diffusion region from the surface of the second isolation epitaxial layer. The method further includes a step of forming complementary pairs of MIS type field effect F fungistors in the same well region and in the second isolated epitaxial layer in areas other than the well region.

Effects According to the above structure, when the epitaxial layer is separated by the diffusion layer of the same conductivity type as the substrate, the depth of separation and diffusion of the epitaxial layer from the soil can be made shallow in order to form a buried layer in the region to be separated in advance. The area required to separate the transistors can be reduced, which improves the degree of integration of the memory section. Since a buried layer is formed, even if the epitaxial layer is thinned, the method of manufacturing a semiconductor device prevents the depletion layer of the single layer and the depletion layer of the substrate from coming close to each other and having the same potential.

76-7・ Example Hereinafter, specific examples will be described using the drawings.

FIGS. 1A to 1F are diagrams showing a cross-sectional structure of a semiconductor device in the order of steps in an embodiment of the manufacturing method of the present invention.

In FIG. 1(&), an n-type buried layer 2 and a p-type buried layer 3 are formed on an n-type silicon substrate 1 by an impurity diffusion technique using an oxide film as a mask. Note that the n-type buried layer 2
is formed in a region where an epitaxial layer 4, which will be described later, is separated into islands, and a p-type buried layer 3 is formed in a region where an n-type well layer 8, which will be described later, is formed. Next, dichlorosilane (8iH2
P-type epitaxial layer 4 is formed using thermal decomposition of C71z).
grow.

In this embodiment, the impurity concentration of the n-type silicon substrate 1 is approximately 1×10 15 CF3, and the p-type epitaxial layer 4 is formed with poron as an impurity of 1×10 15 (1 m
The thickness was set to 7 μm for a concentration of '-'. Next, as shown in FIG. 1(b), an n-type deep diffusion layer 5 is diffused into the epitaxial layer 4 in the same region as the n-type buried layer 2 by an impurity diffusion technique using an oxide film as a mask. is separated into an isolated epitaxial layer 6 and a second isolated epitaxial layer 7.

Furthermore, an n-type well layer 8 is formed from the surface of the second isolation epitaxial layer 7 to be located above the p-type buried layer 3 using ion implantation technology and thermal diffusion technology. In this example, the impurity surface concentration of the n-type well layer 8 is set to 1×10
cm, and the diffusion depth was approximately 6 μm. moreover,
When forming the n-type diffusion layer 5, the heat treatment conditions for forming the n-type well layer 8 are adjusted so that the n-type diffusion layer 6 and the n-type buried layer 2 overlap because the n-type buried layer 2 is also diffused in the upper part. It is also controlled and formed. Next, as shown in FIG. 1(Q), device isolation is performed using a field oxide film 9 using a selective oxidation (Locos) technique using a silicon nitride film as a mask. Thereafter, the silicon nitride film and the protective oxide film are removed, and a gate insulating film 13.15 is formed in a portion where a MO8 transistor (to be described later) will be formed. The portion of the gate insulating film to be formed is removed using lithography and etching techniques. In this example, a protective oxide film of 500 layers and a silicon nitride film of 12 layers were used, the field oxide film thickness was about 1 μm, and a silicon oxide film was used as a gate insulating film, and the film thickness was about 1000 layers. Then the first
As shown in Figure (d), after growing a silicon oxide film, a silicon nitride film, and a gate electrode layer, which are the gate insulating films of the part that forms an n-channel) V-type MNO5 type nonvolatile memory transistor, the lithography process is performed. Then, using an etching technique, the gate electrode layer is removed except for the portions that will become the gates of the MNO8 type memory transistor and the MO8 type transistor, and the portions that will be used as wiring, and the silicon nitride film is also removed. MN of isolation epitaxial layer 6
The part forming the O8 type nonvolatile memory transistor is
Silicon oxide film 10 which is a gate insulating film. A gate electrode 12 is provided on the silicon nitride film 11, and a p-type electrode is provided on the n-type well layer 8.
In a portion where a channel type MO8 type transistor is formed, a gate electrode 14 is provided on a silicon oxide film 13 which is a gate insulating film, and an isolation layer 10 is formed.

Except for the n-type well layer 8 of layer 7, n-channel type MO8
In a portion where a type transistor is to be formed, a gate electrode 16 is provided on a silicon oxide film 16 which is a gate insulating film.

In this embodiment, the thickness of the silicon oxide film was set to about 20 so that it could serve as a tunneling medium for a 10ii101i type memory transistor. Furthermore, a silicon nitride film 11 on the silicon oxide film 1o is formed using a vapor phase growth method based on a chemical reaction between silane (5iH4) and ammonia (NHs).
The gate electrodes 12, 14, and 16 were made of metal electrodes made of polycrystalline silicon, and the film thickness was about 4,000. Further, the thickness of the silicon oxide film 13.15 in the portion where the MO8 type transistor is formed was set to 1000.

Next, as shown in FIG. 1(6), P-type impurity ions are implanted into the source 17 of the p-channel/L/MO8 type transistor in the n-type well layer 8 using lithography technology and self-line technology. This is applied to the drain 18 region, and further, p-type impurity ion implantation is performed as a guard punt 19 around the area where the n-channel MO8) rungis 114-ivy other than the n-type well layer 8 of the isolation epitaxial layer 7 is formed.

Next, as shown in FIG. Source 22 and drain 2 of n-channel MOS transistors other than n-well layer 8 in layer 7
Apply to 3 areas. Furthermore, n-type impurity ions are implanted around the n-type well layer 8 of the isolation epitaxial layer 7 to form a guard band 24 . In this embodiment, p-channel MO
Source of S transistor 17. Boron ions (
B) was applied. Also, the n-channel) vMNO8 type memorite memory transistor 20, drain 21, the source 22 of the MOS) transistor. Phosphorus ions (P+) were applied as an n-type impurity to the drain 23 and guard band 24 regions. Next, an interlayer insulating film is applied, and n-chip/l/MOS
A nonvolatile memory element is created by forming contact holes, metal wiring layers, and protective films using vapor phase growth technology, lithography technology, and etching technology to complementarily connect transistors and p-channel/l/MO5) transistors. It is possible to configure an 0M08 circuit with

In this example, MH is used as the MIS type nonvolatile memory element.
We have described the case of an O8 type non-volatile volatile memory transistor, but instead of a silicon nitride film as the gate insulating film, a high dielectric constant film such as aluminum oxide (120s) + tanta oxide/L/(Ta20B) is used as the gate insulating film. It goes without saying that you may also use

FIG. 2 shows an equivalent circuit of the parasitic transistor in the 0M08 section of the semiconductor device of the present invention. In this figure, 25 is a parasitic NPN transistor; 26ti is a parasitic NPN transistor;
P N ) Resistance between base and emitter of transistor, 27
indicates a parasitic PNP transistor.

In the structure of this example, a p-type buried layer exists under the MOS transistor, and the base region of the parasitic 111PN transistor has a structure with a high impurity concentration. 1lfe is kept low. Furthermore, the p-type buried layer is parasitic)JP)i
) The resistance 26 between the base and emitter of the transistor is lowered to make the parasitic NPN transistor difficult to operate.

As described above, according to the structure of this embodiment, it is possible to miniaturize a semiconductor device equipped with both an MIS type nonvolatile memory element and an 0M08 circuit, and to reduce latch-up.
This greatly contributes to higher integration and higher performance.

Effects of the Invention In the structure of a semiconductor device obtained by the method described above, when the epitaxial layer is separated by a diffusion layer of the same conductivity type as the substrate, a buried layer is formed in advance in the region to be separated, so that the epitaxial The depth of isolation diffusion from the top of the layer can be made shallow, lateral diffusion can be suppressed, the area required for separating memory transistors can be reduced, and the degree of integration of the memory section can be improved. became. In addition, in the structure of the present invention, since the p-type buried layer is formed under the n-well layer, even if the epitaxial layer is thinned, the depletion layer of the n-type well layer and the depletion layer of the p-type substrate are close to each other. This makes it possible to prevent the potential from becoming the same.

[Brief explanation of drawings]

FIGS. 1(&) to (0) are cross-sectional views showing a process order structure of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining the present invention in detail. 1. ...N-type silicon substrate, 2...N-type buried layer, 3...P-type buried layer, 4...
...p-type epitaxial layer, 6...n-type diffusion layer, 6.7...separation epitaxial layer, 8. mountain...n-type well layer, 9... field oxide,
1o...River/Silicon oxide film, 11...Silicon nitride film, 12,14.16...Gate electrode,
13.15...Silicon oxide film, 17°18.
...source and drain, 19...p
type diffusion layer, 20.21...source and drain, 22.23...river source and drain, 24.
・River/n-type diffusion layer.

Claims (1)

[Claims] forming first and second buried diffusion regions of the same conductivity type and a third buried diffusion region of the opposite conductivity type in a semiconductor substrate of one conductivity type; forming an epitaxial layer of the opposite conductivity type on the substrate; separating the epitaxial layer into first and second separated epitaxial layers by first and second diffusion regions of the same conductivity type as the substrate, which reach the first and second buried diffusion regions from the surface of the epitaxial layer; , forming a metal-insulator-semiconductor type nonvolatile memory element in the first separated epitaxial layer;
A well region of the same conductivity type as the substrate is formed so as to face the third buried diffusion region from the surface of the isolation epitaxial layer, and a well region of the same conductivity type as the substrate is formed, and a well region is formed in the well region and the second isolation epitaxial layer other than the well region, respectively. A method of manufacturing a semiconductor device, comprising: forming a complementary pair of MIS field effect transistors.