JPS63102371A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area required for isolation when various elements coexist on a same chip by a method wherein an MIS nonvolatile memory device is formed in 1st well region and a same conductivity type MIS field effect transistor is formed in 2nd well region and an opposite conductivity type MIS field effect transistor is formed in an epitaxial layer. CONSTITUTION:A 1st P-type well layer 4 and a 2nd P-type well layers 5 which reach a buried layer 2 are formed from the surface of an epitaxial layer 3. Then, field oxide films 7 are formed by selective oxidation technology and, after the materials for gate insulating films and gate electrodes are applied to the whole surface, patterning is carried out to form the gate insulating films 8 and 10 and the gate electrodes 9 and 11 are formed. Then P-type impurity ions and N-type impurity ions are implanted to form N-type diffused layers 15, 16, 17 and 18 and P-type diffused layers 19 and 20. Finally, processes of forming layer insulating films, contacts, wirings and protective films are carried out to make an NMOS nonvolatile memory device and a CMOS device coexist on the same chip.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a Mis (metal-insulator-semiconductor) type nonvolatile memory element with a high degree of integration.

Conventional technology With the advancement of semiconductor process technology, the performance and functionality of semiconductor integrated circuits are increasing.
2. Description of the Related Art There is an increasing demand for a device that has the functions of an electrically rewritable ROM (EEPROM) using an S-type nonvolatile memory element and a control circuit such as a microcomputer. For example, an MNOS (metal-silicon nitride) is used as an MIS type non-volatile optical storage element, in which a thin oxide film is formed on a silicon substrate, a silicon nitride film is formed on top of that, and a gate electrode is further formed on top of that. Nonvolatile memory transistors with a film-silicon oxide film-semiconductor structure are well known, but it is possible to coexist a memory circuit section using this MNOS memory transistor and a control circuit section that controls this memory circuit on the same chip. There is an L-chip microcomputer with built-in MNOS memory.

In a semiconductor device in which a memory circuit section consisting of such an MIS-type non-type optical volatile storage element and a peripheral circuit section consisting of an MIS-type field effect transistor coexist on the same substrate, the peripheral circuits other than the memory are placed on the same chip. Because they are integrated on the same chip, the power consumption of the chip increases, which causes the temperature of the chip to rise, which has a negative impact on the memory retention characteristics of nonvolatile memory elements coexisting on the same chip.To prevent this, The peripheral circuit section is a CMO that can reduce power consumption as much as possible.
8 (complementary M OS).

In order to coexist a nonvolatile memory element and a CMO3 element on the same chip, it is necessary to electrically separate the nonvolatile memory element and the CMOS element. epitaxial layers of opposite conductivity type are formed on a semiconductor substrate of the same type, the epitaxial layers are separated by a diffusion layer of the same conductivity type, a nonvolatile memory element is formed in the separated epitaxial layer, while a CMOS element is Conventional methods have been to form and isolate epitaxial layers and well regions within the epitaxial layers.

Problems to be Solved by the Invention However, in conventional manufacturing methods, the epitaxial layer is The thickness is sufficiently thick (usually 15 to 20 μm), so it is necessary to diffuse the isolation diffusion layer that separates the nonvolatile memory elements very deeply, and the lateral diffusion of the isolation diffusion is also very deep. This has the disadvantage that the area required for isolation increases, and as a result, the degree of integration of the memory circuit section cannot be increased very much.

The object of the present invention is to
Means for solving problems necessary for separation of MIS type non-volatile optical storage elements when O3 circuits coexist on the same chip In order to achieve the above object, the present invention provides a single conductivity type semiconductor substrate forming a buried layer of the opposite conductivity type on the substrate; forming an epitaxial layer of the same conductivity type as the substrate on the substrate;
forming a second well region reaching the well region and the buried layer to separate the epitaxial layer; forming a MIS type nonvolatile memory element in the first well region; a step of forming an MIS field effect transistor of the same conductivity type in the well region of the well region, and a step of forming an MIS field effect transistor of the opposite conductivity type in the separated epitaxial layer.
A method of manufacturing a semiconductor device includes a step of forming an IS type field effect transistor.

Effect: According to the manufacturing method of the present invention, the nonvolatile memory element can be separated into the well region of the epitaxial layer, and the conventional separation and diffusion process from the surface of the epitaxial layer is not necessary, making the area required for separation extremely small. becomes possible.

Example Hereinafter, specific examples will be described using the drawings.

FIGS. 1a" to 1e are cross-sectional views in order of steps showing an embodiment of the manufacturing method of the present invention.

First, as shown in FIG. 1a, a P-type buried layer 2 is formed on an n-type silicon substrate 1 by ordinary selective diffusion technology, and then an n-type epitaxial layer is formed using thermal decomposition of dichlorosilane (Si82Ce2). Form layer 3. In this example, an n-type silicon substrate 1 is doped with an impurity concentration of 2X.
The n-type epitaxial layer 3 had a phosphorus concentration of about I x 10 "cm"-' and a thickness of 7 μm.

Further, the P-type buried layer 2 uses boron as an impurity, and has a concentration of about 1018 cm3.

Next, as shown in FIG. 1, a first P-type well layer 4 and a second P-type well layer 5 reaching the buried layer 2 are formed from the surface of the epitaxial layer 3. In this step, the epitaxial layer can be separated by the second P-type well layer 5 and the buried layer 2, and an n-type isolated epitaxial layer 6 can be formed. In this embodiment, the first well layer 4
and the second well layer 5 were formed at the same time, and both wells had an impurity surface temperature of about 1×10 5 C11 and a diffusion depth of about 5 μm. Furthermore, in the heat treatment for forming the well layer, the P-type buried layer 2 diffuses into the upper part, so the heat treatment conditions were controlled so that the well layer 5 and the P-type buried layer overlap sufficiently.

Next, as shown in FIG. 1C, a field oxide film 7 is formed by a selective oxidation technique using a silicon nitride film. In this example, the film thickness was 8000A. Next, materials for the gate insulating films and gate electrodes are deposited on the entire surface, and patterning is performed using photoetching technology to form gate insulating films 8 and 10 and gate electrodes 9 and 11. In this embodiment, silicon dioxide films were used as the gate insulating films 8 and 10, and the film thickness was set to 50 OA. In addition, the gate electrode 9,
As 11, a polysilicon film doped with phosphorus (approximately 10c+a) was used, and the film thickness was set to 5000 Å.

Next, as shown in FIG. 1d, a very thin silicon oxide film 12 is oxidized at 800° C. in an oxygen atmosphere, and then silane (SiH4) and ammonia (NH3) are added to the silicon oxide film 12. A silicon nitride film 13 is formed by a chemical reaction (vapor phase growth method), and phosphorus (1
A polysilicon film (about 0c+w) is deposited and patterned using a photoetching technique. In this example, the silicon oxide film 12 has a thickness of 20A so that it can serve as a tunneling medium, and the silicon nitride film 13 has a growth temperature of 750°C and a gas flow rate ratio of NHs/5iH.
It was grown at 500A under the condition of 4=50.

Next, as shown in Figure 1e, P
implanting type impurity ions and n-type impurity ions,
N-type diffusion layer 15.16.17゜18, P-type diffusion layer 19.
20, CMOS transistor and MNO
These were used as the source and drain of each S memory transistor. In this example, B+ ions were used as P-type impurity ions, and As+ ions were used as N-type impurity ions.

Finally, by performing interlayer insulating film formation, contact formation, wiring formation, and protective film formation steps, a semiconductor device in which an MNO8 type nonvolatile memory element and a CMO3 element coexist on the same chip can be manufactured.

Effects of the Invention As described above, according to the manufacturing method of the present invention, it is possible to significantly reduce the area required for separation (which requires a separation and diffusion process from the surface of the epitaxial layer in the conventional method), and it is possible to significantly reduce the area required for separation from the surface of the epitaxial layer. This greatly contributes to higher integration of semiconductor devices.

[Brief Description of the Drawings] Figures 1a-e are step-by-step cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and Figure 2 is a cross-sectional structure of a semiconductor device obtained by a conventional manufacturing method. It is a diagram. 1... N-type silicon substrate, 2... P-type buried layer, 3... N-type epitaxial layer, 4, 5
... P-type well layer, 6 ... Isolation epitaxial layer, 7 ... Field oxide film, 8 ...
...Gate insulating film, 9...Gate electrode, 1
0... Gate insulating film, 11... Gate electrode, 12... Silicon oxide film, 13...
...Silicon nitride film, 14...Gate electrode, 1
5-18...n-type diffusion layer, 19.20...
...P-type diffusion layer.

Claims (1)

[Claims] (1) A step of forming a buried layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, a step of forming an epitaxial layer of the same conductivity type on the substrate, and a first well region of an opposite conductivity type in the epitaxial layer. and forming a second well region that reaches the buried diffusion region and separates the epitaxial layer;
a step of forming an S-type nonvolatile memory element, a step of forming an MIS field effect transistor of the same conductivity type in the second well region, and a step of forming an MIS field effect transistor of the opposite conductivity type in the separated epitaxial layer. 1. A method of manufacturing a semiconductor device, comprising the step of forming an effect transistor.