JPH10275864A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having layers of a semiconductor material such as poly-Si containing impurities of different conductivity types and a metallic material such as solicited, without causing mutual diffusion of impurities and without decreasing the throughput. SOLUTION: A method for manufacturing a semiconductor device, having a wiring structure in which a semiconductor material layer 6 containing first and second impurities for imparting mutually different conductivities to semiconductor materials in the first and second regions and a metallic material layer 8 are provided, has (1) a step of introducing the first impurity into the semiconductor material layer 6 from above the semiconductor material layer 6 is the first region and introducing the second impurity into the semiconductor material layer 6 from above the metallic material 8 in the second region, and (2) a step of introducing the first impurity into the semiconductor material layer 6 from above the semiconductor material layer 6 is the first region and S introducing the second impurity into the semiconductor material layer 6, from above the metallic material layer 8 is the entire region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device comprising:
The present invention relates to a method for manufacturing a semiconductor device including a wiring structure in which a semiconductor material layer and a metal-based material layer are stacked, and the semiconductor material layer includes both first and second impurities having different conductivity types. . For example, in a wiring structure in which polysilicon and metal silicide are stacked, a so-called polycide structure, a wiring structure in which polysilicon and metal are stacked, or a wiring structure in which polysilicon and a metal compound are stacked, N-type impurities are added to polysilicon. It is an object of the present invention to provide a manufacturing method for a semiconductor device containing both a P-type impurity and a P-type impurity, which prevents inconvenience caused by both impurities diffusing into each other in a wiring layer. The present invention
For example, a dual gate using the stacked wiring structure as a gate electrode of a MOSFET (Dual Gate)
It can be suitably used as a method for forming a CMOS.

[0002]

2. Description of the Related Art For example, in a MOSFET having a structure in which both first and second impurities imparting different conductivity types are contained in, for example, polysilicon, first and second impurities are provided.
However, there is a problem that the MOSFET characteristics may fluctuate due to mutual diffusion of impurities, and the MOSFET characteristics may fluctuate due to penetration of impurities such as boron. Less than,
The problems of the prior art will be described in detail.

In recent years, further miniaturization and higher performance of semiconductor devices have been demanded. For example, NM
CMOS formed by both OSFET and PMOSFET
Is characterized by low power consumption and high speed, and is widely used as many LSI components such as memory logic.
With respect to MOS, the gate length of the FET is being miniaturized with higher integration in the future.

Heretofore, an N ⁺ type gate electrode has been used for a PMOSFET gate electrode in the same manner as an NMOSFET for reasons such as simplification of the process and high performance due to the buried channel type. However, from the deep submicron generation onward, it is difficult to suppress the short channel effect in the buried channel type, and therefore, the application of a P ⁺ type gate which is a surface channel type is effective.

[0005]

In order to form a gate of a different polarity in which an NMOS is an N ⁺ gate and a PMOS is a P ⁺ gate, for example, polysilicon constituting a gate electrode and arsenic or phosphorus for an N type are used. In many cases, ion implantation is performed separately by ion implantation, such as ion implantation of boron or BF ₂ for the P-type. However, when a wiring structure in which polysilicon and metal silicide are stacked on a gate electrode, a so-called polycide structure or a wiring structure in which polysilicon and metal are stacked, the diffusion rate of impurities in metal silicide is reduced to Si or SiO ₂ . Since it is much faster (diffusion coefficient is about four orders of magnitude faster), the P ⁺ and N ⁺ impurities interdiffuse, compensating for the impurities in the polysilicon. Due to this phenomenon, the Fermi level in the polysilicon fluctuates, or the gate electrode is depleted when a gate voltage is applied, so that the threshold voltage Vth fluctuates and the device characteristics may deteriorate.

Referring to FIG. 14, a method of forming a conventional dual gate CMOS will be described. In a W polycide structure including a tungsten silicide (WSix) film 8 as a refractory metal silicide and a polysilicon layer 6, an NMOS and a PMOS are used.
Are doped with N-type (for example, phosphorus) and P-type (for example, boron) impurities. When a high-temperature heat treatment (for example, activation annealing) is performed, phosphorus diffuses into tungsten silicide 8 as shown by arrow I, diffuses into polysilicon in P-type gate region 7B, and boron diffuses into tungsten silicide 8 as shown by arrow II. To the polysilicon of the N-type gate region 7A. Therefore, when the Fermi level in the gate electrode fluctuates, or when the gate electrode is depleted when a gate voltage is applied, the threshold voltage Vth fluctuates, and the device characteristics tend to deteriorate. Also,
If the tungsten silicide contains fluorine, the fluorine diffuses through the crystal grain boundaries of the polysilicon to reach the gate oxide film, and boron penetrates.

A technique has been reported in which the composition of tungsten silicide (WSix) is excessively Si in order to reduce the diffusion rate in tungsten silicide in order to suppress the interdiffusion of P ⁺ and N ⁺ impurities. This mechanism breaks the chain structure of tungsten by making the WSix composition silicon-rich and eliminates diffusion paths (T. Fjii, et. Al., "D.
ual (n ⁺ / P ⁺ ) Polycide Gate T
technology using Si-Rich W
Six to Exterminate Latera
l DopantDiffusion "in VLSI
Symp. Tech. Dig. , P. 117, (19
94)). However, when the composition ratio of silicon is increased,
This is not always advantageous because the resistance value of tungsten silicide increases, which causes an increase in wiring resistance and a delay in circuit operation.

Further, in order to prevent high-concentration impurities from diffusing into WSix, boron or phosphorus is ion-implanted into polysilicon, the impurities are diffused into polysilicon by annealing, and then WSix is deposited. But,
Proposed by the inventor. However, in this case, the throughput is lowered, for example, ion implantation into the polysilicon is performed separately in the N ⁺ region and the P ⁺ region, and when boron is used as the P ⁺ impurity, ion implantation with low acceleration energy is performed. And further improvement is desired.

In the prior art, since N ⁺ and P ⁺ impurities in polysilicon are activated during gate patterning, N ⁺ / P ⁺ is used during etching.
Have different etching rates, and a problem arises in that the Si substrate is dug or residues are generated. That is, FIG. 15 shows a change in the etching rate with respect to the sheet resistance. From this figure, when the impurity in the polysilicon is activated, the conductivity types of the N ⁺ and P ⁺ impurities are shown. Shows that the etching rate changes. This figure is
Phosphorus or boron is ion-implanted into polysilicon formed by LPCVD using SiH ₄ , and then
Samples having different sheet resistances were prepared at 00 ° C. with different heat treatment times, and their etching rates were examined. That is, the sample was placed in a container, Cl ₂ gas was introduced, and the sample was etched by irradiating ultraviolet rays of a Hg-Xe lamp. As a result, it was found that the higher the electron density in the conduction band, the higher the etching rate. Was. Processing shape is SEM
According to the observation, undercut occurs in the n-type,
In the case of the p-type, a phenomenon occurs in which only the light-irradiated portion is etched, and in any case, the behavior of the etching process differs depending on the conductivity type of the impurity.

[0010]

SUMMARY OF THE INVENTION The present invention has been proposed in view of the above problems, and has a structure in which a semiconductor material such as polysilicon and a metal material (metal silicide, metal, metal compound, etc.) are laminated. Therefore, in a wiring structure in which both impurities of different conductivity types (N ⁺ impurity and P ⁺ impurity) are included in a semiconductor material such as polysilicon, an impurity of any conductivity type, for example, N ⁺ impurity or P ⁺ By adopting a configuration in which either one of the impurities is introduced from a metal-based material (metal silicide, metal, metal compound, etc.), the problem due to the mutual diffusion of impurities is solved without lowering the throughput. is there.

A first method according to the method for manufacturing a semiconductor device of the present invention.
The invention has a wiring structure in which a semiconductor material layer and a metal-based material layer are stacked on a semiconductor substrate, and the semiconductor material layer includes a first impurity in a first region thereof. In a method for manufacturing a semiconductor device having a wiring structure in which a second region contains a second impurity, and the first and second impurities impart different conductivity types to the semiconductor material,
A step of introducing a first impurity into the semiconductor material layer from above the semiconductor material layer in the first region; and a step of introducing a second impurity into the semiconductor material layer from above the metal-based material layer in the second region. It is characterized by the following.

The second aspect of the present invention relates to a method of manufacturing a semiconductor device.
The invention has a wiring structure in which a semiconductor material layer and a metal-based material layer are stacked on a semiconductor substrate, and the semiconductor material layer includes a first impurity in a first region thereof. In a method for manufacturing a semiconductor device having a wiring structure in which a second region contains a second impurity, and the first and second impurities impart different conductivity types to the semiconductor material,
A step of introducing the first impurity into the semiconductor material layer from above the semiconductor material layer in the first region; and a step of introducing the second impurity into the semiconductor material layer from above the metal-based material layer in all regions. It is a feature.

[0013] In the manufacturing method according to the first aspect of the present invention, the step of doping the first impurity from the polysilicon in the first region and the step of doping the second impurity with the metal silicide, metal, or metal compound in the second region. And a step of doping from above.

In the manufacturing method according to the first invention, the step of doping the first impurity from the polysilicon in the first region and the step of doping the second impurity from the metal silicide, metal or metal compound in the entire region are performed. And a doping step.

In the embodiment of the present invention, a step of doping a first impurity from a semiconductor material such as polysilicon in a first region and a step of diffusing the first impurity into the polysilicon or the like by annealing are described. Can be employed.

The present invention can be implemented in a mode in which the first impurity is N-type and the second impurity is P-type.

In this case, it is possible to carry out the embodiment in which the second impurity is boron.

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, a semiconductor material such as polysilicon and a metal-based material are laminated, and for example, both N ⁺ and P ⁺ impurities are formed of a semiconductor such as polysilicon. In a wiring structure included in the material, a step of introducing (for example, doping) a first impurity from above a polysilicon or the like which is a semiconductor material layer of the first region, and a step of introducing a second impurity into a metal-based material of the second region. On the material layer (on the metal silicide, metal, or metal compound in the second region)
(For example, doping) into the semiconductor material layer from the semiconductor substrate, so that the threshold V
The acceleration energy can be increased when the second impurity is ion-implanted while suppressing the variation in th. Therefore, the ion implantation time can be reduced, and the throughput can be improved.

According to the method of manufacturing a semiconductor device according to the second aspect of the invention, the semiconductor device has a structure in which a semiconductor material such as polysilicon and a metal material are stacked, and the semiconductor material layer such as polysilicon has two layers.
In a structure formed of a plurality of layers or more, a step of introducing (for example, doping) a first impurity from a semiconductor material such as polysilicon in the first region and a step of introducing a second impurity to a metal-based material in the entire region ( Metal silicide and metal in all areas,
By doping from the metal compound), it is possible to increase the acceleration energy when ion-implanting the second impurity while suppressing the variation of the threshold value Vth due to impurity interdiffusion. In addition, when impurities are doped by ion implantation or another method, the number of photolithography steps can be reduced. Therefore, the ion implantation time and the number of steps can be reduced, and the throughput can be improved.

In a case where the method has a step of doping the first impurity from above the polysilicon in the first region and a step of diffusing the first impurity into the polysilicon by annealing, the first impurity is It is possible to suppress diffusion on the metal-based material, and it is possible to suppress fluctuation in threshold voltage Vth due to mutual diffusion of impurities.

According to the structure in which the first impurity is N-type and the second impurity is P-type, variation in threshold voltage Vth due to impurity interdiffusion can be suppressed, and N ⁺ A semiconductor material layer such as / P ⁺ polysilicon can be formed, and a high-performance dual gate (Dual Gate) CMOSFET can be formed.

When boron is used as the second impurity (P-type impurity), fluorine is not contained in the P ⁺ gate, so that it is possible to prevent boron from penetrating through the gate oxide film and suppress a variation in threshold voltage Vth. In addition, when boron ions are implanted, the acceleration energy can be increased, the ion implantation time can be reduced, and the throughput can be improved.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below, and specific embodiments will be described with reference to the drawings. Needless to say, the present invention is not limited by the specific embodiments described below.

First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, the present invention is embodied as a method for forming a dual gate (DualGate) CMOS having a polycide structure in which polysilicon and metal silicide are stacked, in particular, a tungsten polycide structure.

The process will be described below in the order of steps with reference to the drawings. (A) Steps of Field Oxidation and Well Formation Referring to FIG. A field oxide film 2 is formed on a semiconductor substrate, here, a Si substrate 1 by a LOCOS method (eg, an oxidized region forming method by wet oxidation at 950 ° C.).

Next, in the region where the NMOSFET is to be formed,
Ion implantation for forming a PWELL region and for forming a buried layer for preventing punch-through of a transistor and ion implantation for adjusting a threshold value Vth are performed. Thus, an NMOS channel region 3 is formed. Similarly, PM
In the region where the OSFET is to be formed, ion implantation for forming a NWELL region and forming a buried layer for preventing punch-through of the transistor and ion implantation for adjusting the threshold value Vth are performed. Thereby, the PMOS channel region 4
Is formed.

(B) Gate Oxidation, Polysilicon Deposition, and Step of Forming P ⁺ Region Referring to FIG. The gate oxide film 5 is formed to a thickness of 6 nm in this example by thermal oxidation, here, pyrogenic oxidation (H ₂ / O ₂ atmosphere, 850 ° C.).

In this example, polysilicon as a gate material is deposited by low-pressure CVD (for example, low-pressure CVD using SiH ₄ as a raw material gas at a deposition temperature of 580 to 620 ° C.) to have a thickness of 50 to 200 nm. Thus, a polysilicon film 6 is formed. Note that the polysilicon can also be formed of a-Si (amorphous silicon).

Next, P is applied by a resist mask (not shown) which has been patterned by photolithography.
B ⁺ is set to 1 to 10 only in the region where the MOSFET is formed.
Ion implantation is performed under the condition of E15 / cm ² . This allows
A P ⁺ gate region 7 is formed. Subsequently, 800 in N ₂
Anneal at 10 ° C. for 10 minutes to diffuse boron into the polysilicon. Annealing can also be performed by RTA.

(C) Silicide (WSix) deposition, N ⁺
Steps for Forming Region and Forming Offset Oxide Film Referring to FIG. Low pressure CVD (for example, WF ₆ / SiCl
Decompression C using ₂ H ₂ as source gas and deposition temperature at 580
VD), silicide, in this case WSix, is deposited here to 100 nm. Thereby, the silicide film 8 is formed.
To form

Next, the silicide film 8 (WSi in this example)
x) From the top, Phos ⁺ is applied to the entire surface from ¹ to 10E15 / c.
Ions are implanted under the condition of m ² . Reference numeral 9 denotes an N ⁺ region (in one region, a finally necessary phosphorus introduction region). However, here, ion implantation is performed on the entire surface.

Further, a CVD (for example, SiH
₄ / O ₂ as a source gas and a deposition temperature of 420 ° C.
VD), 150 nm of SiO ₂ is deposited here,
A W polycide wiring layer with an offset oxide film is formed. Reference numeral 10 indicates SiO ₂ forming an offset oxide film.
3 shows a membrane.

(D) Step of Forming Gate Electrode Referring to FIG. After resist patterning is performed by photolithography, a gate electrode pattern 11 is formed by anisotropic etching using the resist pattern as a mask. As the anisotropic etching method at this time, for example, etching using a fluorocarbon-based gas for SiO _{2 and} Cl ₂ / O ₂ for W polycide can be employed.

At this time, since the diffusion of phosphorus is not performed, the etching rate of the N ⁺ region does not become particularly high. Therefore, when etching W polycide,
Since the difference in the etching rate of N ⁺ / P ⁺ does not increase, the Si substrate 1 is not dug or the residue of polysilicon does not occur.

(E) Step of Forming MOSFET Referring to FIG. After the above, As ⁺
ion implantation under the conditions of keV, 5E13 / cm ² , NL
The DD region 12 is formed. BF ₂ ⁺ , for example 20k
ion implantation under the conditions of eV, 2E13 / cm ² , and PLD
A D region 13 is formed. Then, after depositing 150 nm of SiO ₂ by, for example, low-pressure CVD, the sidewalls 14 are formed by performing anisotropic etching.

Next, ions are implanted into the NMOS (for example, As ⁺ is implanted under the conditions of ²⁰ keV and 3E15 / cm ² ), an N-type source / drain region 15 is formed, and ions are implanted into the PMOS ( For example, BF ₂ ⁺
Is implanted under the conditions of ²⁰ keV and 3E15 / cm ² ) to form P-type source / drain regions 16.

Next, RTA (Rapid Therm)
(Anal), the impurities are activated at 1000 ° C. for 10 seconds to form a CMOSFET.
At the time of this RTA, a silicide film (here, WSix)
8 diffuses into the polysilicon to form the NMOSF.
An N ⁺ gate is formed in the ET region.

In the present embodiment, boron in the P ⁺ region is diffused into polysilicon before silicide (WSix) is deposited, so that diffusion of boron through silicide (WSix) can be suppressed. In addition, silicide (WSi
x) Phosphorus in the film 8 diffuses into the polysilicon, but if the boron concentration is set high, it does not become N ⁺ due to diffusion compensation. Therefore, variation in threshold value Vth due to mutual diffusion of impurities can be suppressed.

Further, since the phosphorus ion implantation is performed on the entire surface, the number of photolithography steps can be reduced as compared with the prior art.

In the above embodiment, phosphorus is doped by ion implantation. However, phosphorus may be introduced by other means, for example, solid phase diffusion from PSG or the like or vapor phase diffusion. Is also possible. Others
It goes without saying that each configuration may be implemented using other appropriate means.

Second Embodiment In the first embodiment, B ⁺ ions are implanted only into the polysilicon in the PMOS region and phosphorus is doped from above the tungsten silicide. Phos ⁺ is ion-implanted only in silicon,
It is also possible to dope boron from above the tungsten silicide.
Adopts such a form. Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. This embodiment also basically describes the present invention,
The present invention is embodied as a method for forming a polycide structure in which polysilicon and metal silicide are stacked, particularly a dual gate (Dual Gate) CMOS having a tungsten polycide structure.

The steps will be described below in order of steps with reference to the drawings. (A) Step of Field Oxidation and Well Formation This step is the same as that of the first embodiment (see FIG. 1).

(B) Step of Gate Oxidation, Deposition of Polysilicon, and Step of Forming N ⁺ Region Referring to FIG. The gate oxide film 5 is formed to a thickness of 6 nm in this example by thermal oxidation, here, pyrogenic oxidation (H ₂ / O ₂ atmosphere, 850 ° C.).

In this example, polysilicon as a gate material is deposited by low-pressure CVD (for example, low-pressure CVD using SiH ₄ as a raw material gas at a deposition temperature of 580 to 620 ° C.) to have a thickness of 50 to 200 nm. Thus, a polysilicon film 6 is formed. Note that the polysilicon can also be formed of a-Si (amorphous silicon).

Next, in this example, only a region where an NMOSFET is to be formed is formed using a resist mask (not shown) patterned by photolithography.
Phos ⁺ is ion-implanted under the condition of ¹ to 10E15 / cm ² . As a result, an N ⁺ gate region 7a is formed. Subsequently, annealing is performed at 800 ° C. for 10 minutes in N ₂ to diffuse phosphorus into the polysilicon. The annealing is R
TA can also be performed.

(C) Silicide (WSix) deposition, P ⁺
Steps of Forming Region and Forming Offset Oxide Film Referring to FIG. Low pressure CVD (for example, WF ₆ / SiCl
Decompression C using ₂ H ₂ as source gas and deposition temperature at 580
VD), silicide, in this case WSix, is deposited here to 100 nm. Thereby, the silicide film 8 is formed.
To form

On top of that, CVD (eg, SiH ₄ / O
Here, BSG is deposited to a thickness of 150 nm by CVD using ₂ / B ₂ H ₆ as a source gas and a deposition temperature of 420 ° C., and a W polycide wiring layer with an offset oxide film (in this example, an impurity-containing oxide film in particular). To form Symbol 10a
Indicates a BSG film that forms an offset oxide film also serving as an impurity diffusion source.

(D) Step of Forming Gate Electrode Referring to FIG. After resist patterning is performed by photolithography, a gate electrode pattern 11 is formed by anisotropic etching using the resist pattern as a mask. As the anisotropic etching method at this time, for example, etching using a fluorocarbon-based gas for SiO _{2 and} Cl ₂ / O ₂ for W polycide can be employed.

At this time, since boron is not diffused, the etching rate of the P ⁺ region does not become particularly slow. Therefore, when etching W polycide,
Since the difference in the etching rate of N ⁺ / P ⁺ does not increase, the Si substrate 1 is not dug or the residue of polysilicon does not occur.

(E) Step of forming MOSFET Referring to FIG. After the above, As ⁺
ion implantation under the conditions of keV, 5E13 / cm ² , NL
The DD region 12 is formed. BF ₂ ⁺ , for example 20k
ion implantation under the conditions of eV, 2E13 / cm ² , and PLD
A D region 13 is formed. Then, after depositing 150 nm of SiO ₂ by, for example, low-pressure CVD, the sidewalls 14 are formed by performing anisotropic etching.

Next, ions are implanted into the NMOS (for example, As ⁺ is implanted under the conditions of ²⁰ keV and 3E15 / cm ² ), an N-type source / drain region 15 is formed, and ions are implanted into the PMOS ( For example, BF ₂ ⁺
Is implanted under the conditions of ²⁰ keV and 3E15 / cm ² ) to form P-type source / drain regions 16.

Next, RTA (Rapid Therm)
(Anal), the impurities are activated at 1000 ° C. for 10 seconds to form a CMOSFET.
During this RTA, boron in the BSG, which is the offset oxide film 10a also serving as an impurity diffusion source, diffuses into the polysilicon film 6, and a P ⁺ gate is formed in the PMOSFET region.

In this embodiment, phosphorus in the N ⁺ region is
Since phosphorus is diffused into polysilicon before silicide (WSix) is deposited, diffusion of phosphorus into the P ⁺ region through silicide (WSix) can be suppressed. Further, boron in BSG diffuses into polysilicon, but if the concentration of phosphorus is set high, it does not become P ⁺ due to diffusion compensation. Therefore, the threshold voltage Vt due to mutual diffusion of impurities
The fluctuation of h can be suppressed.

In addition, in this embodiment, the same specific effects as those of the first embodiment can be obtained.

Third Embodiment In the second embodiment, boron is doped by solid-phase diffusion from an impurity-containing film, particularly an impurity-containing oxide film (specifically, BSG). On the other hand, in the third embodiment, boron is entirely implanted from above silicide, particularly tungsten silicide. Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. This embodiment also basically embodies the present invention as a method of forming a polycide structure in which polysilicon and metal silicide are stacked, particularly a dual gate (Dual Gate) CMOS having a tungsten polycide structure.

The steps will be described below in the order of steps with reference to the drawings. (A) Step of Field Oxidation and Well Formation This step is the same as that of the first embodiment (see FIG. 1).

(B) Step of Gate Oxidation, Deposition of Polysilicon, and Step of Forming N ⁺ Region Referring to FIG. The gate oxide film 5 is formed to a thickness of 6 nm in this example by thermal oxidation, here, pyrogenic oxidation (H ₂ / O ₂ atmosphere, 850 ° C.).

In this example, polysilicon as a gate material is deposited by low-pressure CVD (for example, low-pressure CVD using SiH ₄ as a raw material gas at a deposition temperature of 580 to 620 ° C.) to have a thickness of 50 to 200 nm. Thus, a polysilicon film 6 is formed. Note that the polysilicon can also be formed of a-Si (amorphous silicon).

Next, N is applied by a resist mask (not shown) patterned by photolithography.
Phos ⁺ is set to 1 only in the region where the MOSFET is formed.
Ions are implanted under the conditions of Ｅ10E15 / cm ² . As a result, an N ⁺ gate region 7b is formed. Subsequently, annealing is performed at 800 ° C. for 10 minutes in N ₂ to diffuse phosphorus into the polysilicon. Annealing can also be performed by RTA.

(C) Step of Depositing Silicide (WSix) and Forming Offset Oxide Film Referring to FIG. Low pressure CVD (for example, WF ₆ / SiC
Silicide, WSix in this example, is formed by low-pressure CVD using l ₂ H ₂ as a source gas and a deposition temperature of 580.
Here, it is deposited to a thickness of 100 nm. Thus, a silicide film 8 is formed.

Next, the silicide film 8 (WSi in this example)
over x), the entire surface of B ^+, ions are implanted under conditions of 1~10E15 / cm ^2. The P ⁺ region formed by the ion implantation is indicated by reference numeral 9b.

Further, a CVD (for example, SiH
₄ / O ₂ as a source gas and a deposition temperature of 420 ° C.
VD), 150 nm of SiO ₂ is deposited here,
A W polycide wiring layer with an offset oxide film is formed. Reference numeral 10 indicates SiO ₂ forming an offset oxide film.
3 shows a membrane.

(D) Step of Forming Gate Electrode Referring to FIG. After resist patterning is performed by photolithography, a gate electrode pattern 11 is formed by anisotropic etching using the resist pattern as a mask. As the anisotropic etching method at this time, for example, etching using a fluorocarbon-based gas for SiO _{2 and} Cl ₂ / O ₂ for W polycide can be employed.

At this time, since boron is not diffused, the etching rate of the P ⁺ region does not become particularly slow. Therefore, when etching W polycide,
Since the difference in the etching rate of N ⁺ / P ⁺ does not increase, the Si substrate 1 is not dug or the residue of polysilicon does not occur.

(E) Step of Forming MOSFET Referring to FIG. After the above, As ⁺
Ion implantation under the conditions of 0 keV and 5E13 / cm ² ,
An LDD region 12 is formed. BF ₂ ⁺ for example 20
ion implantation under the conditions of keV, 2E13 / cm ² , and PL
The DD region 13 is formed. Then, for example, low pressure CVD
After depositing 150 nm of SiO ₂ , the sidewalls 14 are formed by performing anisotropic etching.

Next, ions are implanted into the NMOS (for example, As ⁺ is implanted under the conditions of ²⁰ keV and 3E15 / cm ² ), an N-type source / drain region 15 is formed, and ions are implanted into the PMOS ( For example, BF ₂ ⁺
Is implanted under the conditions of ²⁰ keV and 3E15 / cm ² ) to form P-type source / drain regions 16.

Next, RTA (Rapid Therm)
(Anal), the impurities are activated at 1000 ° C. for 10 seconds to form a CMOSFET.
At the time of this RTA, a silicide film (here, WSix)
Boron in the P ⁺ region 9b (see FIG. 11) diffuses into the polysilicon, and a P ⁺ gate is formed in the PMOSFET region.

In this embodiment, phosphorus in the N ⁺ region is
Since phosphorus is diffused into polysilicon before silicide (WSix) is deposited, diffusion of phosphorus into the P ⁺ region through silicide (WSix) can be suppressed. Although boron in silicide (WSix) diffuses into polysilicon, if the concentration of phosphorus is set to be high, P ⁺ does not occur due to diffusion compensation. Therefore, variation in threshold value Vth due to mutual diffusion of impurities can be suppressed.

Further, when boron is doped by ion implantation, ions can be implanted from above silicide (WSix), so that higher acceleration energy can be achieved compared to the case where ions are implanted from above polysilicon. In addition, the ion implantation time can be reduced.

Fourth Embodiment In this embodiment, the metal-based material was replaced with silicide, and tungsten (W) was used as a metal. As a result, the same effects as those of the above embodiments can be obtained. In addition, when the same operation was performed using molybdenum (Mo), the same effect was obtained.

Embodiment 5 In this embodiment, the metal-based material was replaced with silicide, and a metal compound, titanium nitride (TiN), was used. As a result, the same effects as those of the above embodiments can be obtained.

[0072]

According to the method of manufacturing a semiconductor device according to the present invention, the semiconductor device has a structure in which polysilicon, metal silicide, a metal, and a metal compound are laminated and has different conductivity types (for example, N ⁺ impurity and N ⁺ impurity). When forming a semiconductor device having a structure in which both of the P ⁺ impurities are included in polysilicon, when forming an impurity (for example, N ⁺ or P ^+
+ During the photolithography step and the ion implantation step, the interdiffusion of impurities can be suppressed. Also, at the time of etching, since polysilicon (N ⁺ / P ⁺ polysilicon) into which impurities of different conductivity types are introduced does not exist at the same time, digging of the substrate due to a difference in the etching rate and residual polysilicon are reduced. This can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing steps of a first embodiment of the present invention in order (1).

FIG. 2 is a sectional view showing the steps of the first embodiment of the present invention in order (2).

FIG. 3 is a cross-sectional view sequentially showing the steps of Embodiment 1 of the present invention (3).

FIG. 4 is a cross-sectional view sequentially showing the steps of the first embodiment of the present invention (4).

FIG. 5 is a sectional view showing a step of the first embodiment of the present invention in order (5).

FIG. 6 is a sectional view showing the steps of Embodiment 2 of the present invention in order (1).

FIG. 7 is a cross-sectional view sequentially showing the steps of Embodiment 2 of the present invention (2).

FIG. 8 is a cross-sectional view sequentially showing the steps of Embodiment 2 of the present invention (3).

FIG. 9 is a cross-sectional view showing the steps of Embodiment 2 of the present invention in order (4).

FIG. 10 is a cross-sectional view sequentially showing the steps of Embodiment 3 of the present invention (1).

FIG. 11 is a cross-sectional view sequentially showing the steps of Embodiment 3 of the present invention (2).

FIG. 12 is a cross-sectional view sequentially showing the steps of Embodiment 3 of the present invention (3).

FIG. 13 is a sectional view showing a step of the third embodiment of the present invention in order (4).

FIG. 14 is a sectional view showing a process of the related art.

FIG. 15 is a diagram for explaining a problem of the related art, and is a diagram illustrating a change in an etching rate with respect to a sheet resistance.

[Explanation of symbols]

1 ... semiconductor substrate (substrate such as silicon), 2 ... isolation region (LOCOS SiO _2), 3... N-type M
OSFET area, 4 ... P-type MOSFET area, 5
..Gate insulating film (SiO ₂ ), 6... Semiconductor material layer (polysilicon film), 7... P ⁺ gate region, 7 a,
7b ··· N ⁺ gate region, 8 ··· metal material layer (silicide layer, WSix film), 9 ··· N ⁺ region, 9b ·
..P ⁺ region, 10 ... offset oxide film (Si
O ₂ ), 10a (offset oxide film (also serving as impurity diffusion source)) (BSG), 11 gate electrode pattern, 12, 13 LDD, 14 sidewall (SiO ₂ ), 15 , 16... Source / drain.

Claims (12)

[Claims] A wiring structure in which a semiconductor material layer and a metal-based material layer are stacked on a semiconductor substrate, wherein the semiconductor material layer includes a first impurity in a first region thereof; In the method for manufacturing a semiconductor device having a wiring structure in which a second impurity is contained in the second region, the first and second impurities impart different conductivity types to the semiconductor material. Introducing a second impurity into the semiconductor material layer from above the semiconductor material layer in the first region; and introducing a second impurity into the semiconductor material layer from above the metal-based material layer in the second region. A method for manufacturing a semiconductor device. 2. The metal-based material layer includes metal silicide, metal,
The method according to claim 1, wherein the layer is formed of a metal compound. 3. The method according to claim 1, wherein the semiconductor material layer is a polysilicon layer. 4. The method according to claim 1, further comprising the step of diffusing the first impurity introduced into the semiconductor material layer from above the semiconductor material layer in the first region into the semiconductor material layer by heat treatment. A method for manufacturing a semiconductor device. 5. The semiconductor device according to claim 1, wherein the first impurity imparts an N.sup. ⁺ Conductivity type to the semiconductor material, and the second impurity imparts a P.sup. ⁺ Conductivity type to the semiconductor material. The method for manufacturing a semiconductor device according to claim 1. 6. The method according to claim 1, wherein the second impurity is boron. 7. A wiring structure in which a semiconductor material layer and a metal-based material layer are stacked on a semiconductor substrate, and the semiconductor material layer includes a first impurity in a first region thereof. In the method for manufacturing a semiconductor device having a wiring structure in which a second impurity is contained in the second region, the first and second impurities impart different conductivity types to the semiconductor material. Introducing a second impurity into the semiconductor material layer from above the semiconductor material layer in the first region, and introducing a second impurity into the semiconductor material layer from above the metal-based material layer in all regions. Semiconductor device manufacturing method. 8. The metal-based material layer includes metal silicide, metal,
8. The method according to claim 7, wherein the layer is formed of a metal compound. 9. The method according to claim 7, wherein the semiconductor material layer is a polysilicon layer. 10. The method according to claim 7, further comprising the step of diffusing the first impurity introduced into the semiconductor material layer from above the semiconductor material layer in the first region into the semiconductor material layer by heat treatment. A method for manufacturing a semiconductor device. 11. The semiconductor device according to claim 1, wherein the first impurity imparts N-type conductivity to the semiconductor material, and the second impurity imparts P-type conductivity to the semiconductor material. Item 8. A method for manufacturing a semiconductor device according to item 7. 12. The method according to claim 7, wherein the second impurity is boron.