JPH11340424A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device which is capable of being treated at a high temperature over a long period and which has a high a small-sized high-resistance element, without having to add lithography process. SOLUTION: An element isolation film is formed on a wafer to isolate an NMOS transistor forming region, a PMOS transistor forming region and a diffused layer resistance forming region. Then, an insulation film comprises two films of a lower layer insulation film 113 and a upper layer insulation film 114. After an ion implantation mask is formed and the upper insulation film 114 is etched, an N<+> high concentration diffused layer 116 and a P<+> high concentration diffused layer 118 are formed through performing ion implantation. A heat treatment is performed, while the lower insulation film 113 covers the surface of the wafer. The lower insulation film 113 is etched, a high-melting point metal film is formed, and then heat treatment is performed. Thus, silicides 121, 119 and 120 are formed on the upper surface of a gate electrode 19, the N<+> high concentration diffused layer 116 and the P<+> high concentration diffused layer 118, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device in which a diffusion layer is silicided, and more particularly to a method for manufacturing a semiconductor device having a high resistance element with a small occupation area.

[0002]

2. Description of the Related Art In a semiconductor device, silicidation of a diffusion layer is one of the important factors for achieving higher performance and higher density. 18 to 23 are sectional views showing a method of manufacturing a conventional semiconductor device in which a diffusion layer is silicided in the order of steps. First, as shown in FIG.
An NMOS transistor formation region 41 on a semiconductor substrate 44;
An element isolation film 45 for isolating the PMOS transistor formation region 42 and the diffusion layer resistance formation region 43 is formed.

Next, a PMOS transistor forming region 4 is formed.
Then, an N well 46 is formed in Step 2. A P well 47 is formed in the NMOS transistor formation region 41 and the diffusion layer resistance formation region 43. Next, a gate insulating film 48 and a gate electrode 49 are formed in the NMOS transistor formation region 41 and the PMOS transistor formation region 42. Then NM
An N ^- low concentration diffusion layer 410 is formed in the OS transistor formation region 41 and the diffusion layer resistance formation region 43. In the PMOS transistor forming region 42, a P ^- low concentration diffusion layer 411 is provided.
To form Thereafter, the formed film is etched back to form a sidewall 412 on the side surface of the gate electrode 49.
To form

[0004] Thereafter, as shown in FIG.
Form 3

Thereafter, as shown in FIG. 20, a resist mask 414 for ion implantation for forming an N ⁺ high concentration diffusion layer (source / drain region) 415 is formed by lithography. Ion implantation is performed using the ion implantation resist mask 414 as a mask to form an N ⁺ high concentration diffusion layer 415. Resist mask 4 for ion implantation
14 is removed by ashing and wet processing.

Thereafter, as shown in FIG. 21, a resist mask 416 for ion implantation for forming a P ⁺ high concentration diffusion layer 417 is formed by a lithography technique. Ion implantation is performed by using the ion implantation resist mask 416 as a mask to form a P ⁺ high concentration diffusion layer (source / drain region) 417. Resist mask 4 for ion implantation
16 is removed by ashing and wet processing.

[0007] Thereafter, as shown in FIG.
In the state where 3 covers the surface of semiconductor substrate 44, a heat treatment for activating the implanted impurities is performed.

[0008] Thereafter, as shown in FIG.
3 is etched, a refractory metal is formed by a film forming technique such as sputtering, and a heat treatment for silicidizing the refractory metal is performed. Subsequently, the unreacted refractory metal is removed to form a gate electrode. 49, N ⁺ high concentration diffusion layer 415, P ⁺ high concentration diffusion layer 417 and silicide 4
18, 419 and 420 are formed.

When a semiconductor device is manufactured by the above method, since a silicide layer is formed on the N ⁺ high concentration diffusion layer and the P ⁺ high concentration diffusion layer, for example, the layer resistance value is several Ω / □. In order to form a high-resistance diffusion layer resistance element, a large-area diffusion-layer resistance formation region is required, and it is difficult to achieve high integration of a semiconductor element.

As a method of manufacturing a semiconductor device for forming a high-resistance diffusion layer resistance element with a small occupation area, for example,
A method of manufacturing a semiconductor device in which a mask for silicidation is formed after etching using an ion implantation mask as a mask and a silicide film is selectively formed on a high-concentration diffusion layer is disclosed (JP-A-8-97370). No.). This method forms a high-resistance diffusion layer resistance with a small occupation area without adding a lithography step.

[0011]

However, when a semiconductor device is manufactured by the above-described method, heat treatment for activating impurities implanted in a diffusion layer before forming silicide is performed at a high temperature for a long time. There is a problem that the diffused impurities are diffused outward and a contaminant in the heat treatment furnace is mixed into the semiconductor substrate. Further, in the case where heat treatment for activating impurities is performed after silicide formation, the heat resistance of silicide is low, aggregation of silicide occurs, and the resistance of the diffusion layer increases. It is impossible.

The present invention has been made in view of such a problem, and has a high-resistance resistance element with a small occupied area and capable of performing a long-time heat treatment at a high temperature without adding a lithography process. It is an object to provide a method for manufacturing a semiconductor device.

[0013]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an element isolation insulating film on a semiconductor substrate;
Forming a transistor formation region and a diffusion layer resistance formation region; forming a gate insulating film and a gate electrode in the NMOS transistor formation region and the PMOS transistor formation region; A step of selectively implanting N-type ions into a portion to be a resistance portion; a step of selectively implanting P-type ions into a portion to be a source / drain region of a PMOS transistor; and a side wall insulating film on a side surface of the gate electrode. Forming a lower insulating film and an upper insulating film on the entire surface, selectively removing the upper insulating film, and forming a high-concentration source / drain region and a resistor of the NMOS transistor through the lower insulating film. Selectively implanting N-type ions into a portion to be an electrode portion of the semiconductor device; Wherein P through the lower insulating film Shi removed by
Selectively implanting P-type ions into portions that become high-concentration source / drain regions of the MOS transistor; and selectively removing the lower insulating film using the upper insulating film as a mask and then depositing a high melting point metal film. And a step of performing a heat treatment to silicide the refractory metal film.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming an element isolation insulating film on a semiconductor substrate and forming an NMOS.
Partitioning a transistor formation region, a PMOS transistor formation region, and a diffusion layer resistance formation region;
A step of forming a gate insulating film and a gate electrode in a region where an S transistor is to be formed; a step of selectively implanting N-type ions into a portion to be a source / drain region of an NMOS transistor; Selectively implanting P-type ions into a portion to be a part, forming a sidewall insulating film on side surfaces of the gate electrode, forming a lower insulating film and an upper insulating film on the entire surface, Selectively removing a film and selectively implanting N-type ions into a portion to be a high-concentration source / drain region of the NMOS transistor via the lower insulating film; and selectively removing the upper insulating film. P-type ions are selectively injected into the high-concentration source / drain region of the PMOS transistor and a portion serving as an electrode portion of the resistor through the lower insulating film. And a step of selectively removing the lower insulating film using the upper insulating film as a mask and thereafter depositing a refractory metal film, and a step of performing heat treatment to silicide the refractory metal film. It is characterized by the following.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an element isolation insulating film on a semiconductor substrate;
A step of partitioning a transistor formation planned area, a PMOS transistor formation planned area and a diffusion layer resistance formation planned area; a step of forming a well region of the opposite conductivity type to the semiconductor substrate in the diffusion layer resistance formed area; Forming a gate insulating film and a gate electrode in the formation region and the PMOS transistor formation region, selectively implanting N-type ions into portions to be source / drain regions of the NMOS transistor,
P is added to the source / drain region of the S transistor.
Selectively implanting type ions, forming a sidewall insulating film on side surfaces of the gate electrode, forming a lower insulating film and an upper insulating film on the entire surface, and selectively removing the upper insulating film. Then, N is formed in a portion to be a high concentration source / drain region of the NMOS transistor via the lower insulating film.
Selectively implanting p-type ions, and selectively removing the upper insulating film and selectively implanting p-type ions into the high concentration source / drain regions of the PMOS transistor via the lower insulating film. And a step of selectively removing the lower insulating film using the upper insulating film as a mask and thereafter depositing a refractory metal film, and a step of performing heat treatment to silicide the refractory metal film. It is characterized by the following.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an element isolation insulating film on a semiconductor substrate;
Partitioning a transistor formation region, a PMOS transistor formation region, and a diffusion layer resistance formation region;
A step of forming a gate insulating film and a gate electrode in a region where an S transistor is to be formed, a step of selectively implanting N-type ions into a portion to be a source / drain region of an NMOS transistor, and a step of forming a source / drain region of a PMOS transistor Selectively implanting P-type ions into portions, forming sidewall insulating films on side surfaces of the gate electrode, forming a lower insulating film and an upper insulating film over the entire surface, and selecting the upper insulating film. Selectively removing N-type ions into the high concentration source / drain regions of the NMOS transistor through the lower insulating film, and selectively removing the upper insulating film to form the lower insulating film. Selectively injecting P-type ions into a portion to be a high-concentration source / drain region of the PMOS transistor through a film; Introducing an impurity into the semiconductor substrate in the diffusion layer resistor formation region through the step of, and applying a high melting point metal film after selectively removing the lower insulating film using the upper insulating film as a mask, Heat-treating the refractory metal film into silicide.

In each of the above inventions, the lower insulating film can be formed by an oxide film, and the upper insulating film can be formed by a nitride film.

A method of manufacturing a semiconductor device according to a fifth aspect of the present invention includes a step of forming a low-concentration diffusion layer serving as a diffusion layer resistance portion on a surface of a semiconductor substrate; a step of forming a lower insulating film and an upper insulating film; After selectively removing the upper insulating film, N-type ions are selectively implanted through the lower insulating film, and after selectively removing the upper insulating film, P-type ions are selected through the lower insulating film. NMO by selective injection
Forming a high-concentration source / drain diffusion layer of an S transistor and a PMOS transistor; forming a refractory metal film after selectively removing the lower insulating film using the upper insulating film as a mask; Silicidizing the refractory metal film.

The step of forming the low concentration diffusion layer serving as the diffusion layer resistance portion is the same as the step of forming the low concentration source / drain diffusion layer of the NMOS transistor or the low concentration source / drain diffusion layer of the PMOS transistor. It can be. Further, the low-concentration diffusion layer serving as the diffusion layer resistance section can be a well of a conductivity type opposite to that of the semiconductor substrate.

A method of manufacturing a semiconductor device according to a sixth aspect of the present invention includes a step of forming a lower insulating film and an upper insulating film; and a step of selectively removing the upper insulating film, and then removing N-type ions through the lower insulating film. And then selectively removing the upper insulating film, and then selectively implanting P-type ions through the lower insulating film, thereby forming high-concentration source / drain diffusion layers of the NMOS transistor and the PMOS transistor, respectively. Forming, a step of forming a low-concentration diffusion layer to be a diffusion layer resistance portion on the surface of the semiconductor substrate via the lower insulating film, and selectively removing the lower insulating film using the upper insulating film as a mask. A step of forming a refractory metal film later;
Heat-treating the refractory metal film into silicide.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings.
1 to 6 are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. As shown in FIG. 1, an element isolation film 15 for isolating an NMOS transistor formation region 11, a PMOS transistor formation region 12, and a diffusion layer resistance formation region 13 is formed on a semiconductor substrate 14, for example.
It is formed to a thickness of 400 nm by the LOCOS oxidation method. As the semiconductor substrate 14, for example, a P-type silicon substrate is used.

Next, the PMOS transistor formation region 1
An N well 16 is formed on the substrate 2 by ion implantation. This ion implantation condition is, for example, that phosphorus ions (P ⁺ )
And a dose of 1 × 10 at an energy of 800 keV.
¹³ doses / cm ² and energy of 300 keV, dose 5
× 10 ¹² / cm ² . The P well 1 is provided in the NMOS transistor formation region 11 and the diffusion layer resistance formation region 13.
7 is formed by ion implantation. This ion implantation condition uses, for example, boron ions (B ⁺ ) as impurities,
At an energy of 350 keV and a dose of 1 × 10 ¹³ / cm
And a dosage of 5 × 10 ¹² pieces / cm ² at ² and energy 100 keV.

Next, the NMOS transistor formation region 11
Then, a gate insulating film 18 and a gate electrode 19 are formed in the PMOS transistor formation region 12. Gate insulating film 18
Is formed to a thickness of about 10 nm by, for example, a thermal oxidation method. The gate electrode 19 has, for example, a thickness of 200 nm.
Use polysilicon.

Thereafter, the NMOS transistor forming region 1
1 and the diffusion layer resistance forming region 13 ^-Low concentration diffusion layer 11
0 is formed by ion implantation. This ion implantation condition
Means that, for example, phosphorus ions (P⁺) Use d
Energy 2 × 10 at 20 keV energy¹³Pieces / cm^Twoso
is there. In the PMOS transistor formation region 12, P^-Low
The concentration diffusion layer 111 is formed by ion implantation. This
The ON implantation condition is, for example, that boron ions
(B⁺) Using an energy of 30 keV and a dose of 3 ×
10¹³Pieces / cm^TwoIt is. After that, the formed film is etched
By backing, a side wall is formed on the side of the gate electrode 19.
Forming a rule 112. Side wall 112
For example, a silicon oxide film has a width of about 10 nm.

Thereafter, as shown in FIG.
13 and an upper insulating film 114 are formed. The lower insulating film 113 and the upper insulating film 114
It has the feature that the selectivity to etching is excellent,
For example, the lower insulating film 113 is formed using a silicon oxide film having a thickness of about 20 nm, and the upper insulating film 114 is formed using a silicon nitride film having a thickness of about 10 nm.

Thereafter, as shown in FIG. 3, a resist mask 115 for ion implantation for forming the N ⁺ high concentration diffusion layer 116 is formed by lithography. After etching the upper insulating film 114 using the ion implantation resist mask 115 as a mask, ion implantation is performed,
^{+ A} high concentration diffusion layer (source / drain region) 116 is formed. The ion implantation conditions include, for example, arsenic ions (As ⁺ ) as impurities, an energy of 70 keV, and a dose of 2 × 10 ¹⁵ / cm ² . The resist mask 115 for ion implantation is removed by ashing and wet processing.

Thereafter, as shown in FIG. 4, a resist mask 117 for ion implantation for forming the P ⁺ high concentration diffusion layer 118 is formed by lithography. After the upper insulating film 114 is etched using the ion implantation resist mask 117 as a mask, ion implantation is performed, and P ⁺
A high concentration diffusion layer (source / drain region) 118 is formed. This ion implantation condition is, for example, that boron difluoride (BF ²⁺ ) is used as an impurity and the energy is 50 ke.
V is a dose of 5 × 10 ¹⁵ / cm ² . The resist mask 117 for ion implantation is removed by ashing and wet processing.

Thereafter, as shown in FIG.
In the state where 13 covers the surface of the semiconductor substrate 14,
A heat treatment for activating the implanted impurities is performed. This heat treatment can be performed, for example, at 850 ° C. for 30 minutes in a nitrogen atmosphere. The lower insulating film 113 is a semiconductor substrate 14
By covering the surface, outward diffusion of the implanted impurities and contaminants from the heat treatment furnace are prevented from being mixed into the semiconductor substrate 14, and heat treatment at a high temperature for a long time can be performed.

Thereafter, as shown in FIG.
After the lower insulating film 113 is etched using the mask 14 as a mask, a high melting point metal is formed by a film forming technique such as sputtering, and a heat treatment for silicidizing the high melting point metal is performed. By removing the silicides 119 and 120 on the N ⁺ high concentration diffusion layer 116, the P ⁺ high concentration diffusion layer 118 and the gate electrode 19,
121 is formed. In this silicidation step, for example,
After using titanium as a high melting point metal and annealing at 650 ° C. for 30 seconds, unreacted high melting point metal is removed by wet treatment, and annealing at 800 ° C. for 10 seconds can be performed.

According to such a method, the diffusion layer is made of silicide.
When a semiconductor device is manufactured as^-Low concentration diffusion layer 1
Since no silicide layer is formed on
A high-resistance element can be obtained with a small occupation area.
On the gate electrode 19, N ⁺Over the high concentration diffusion layer 116
And P⁺A low resistance silicide layer on the high concentration diffusion layer 118
Since 121, 119 and 120 are formed, for example,
A low resistance diffusion layer resistance with a layer resistance of several Ω / □
Can also be.

FIGS. 7 to 11 are sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps. As shown in FIG. 7, an element isolation film 23 for isolating an N-well resistance formation region 21 is formed on a semiconductor substrate 22 by, for example, L
It is formed to a thickness of 400 nm by the OCOS oxidation method.
As the semiconductor substrate 22, for example, a P-type silicon substrate is used. Next, after the oxide film 24 is formed to a thickness of, for example, 20 nm by a thermal oxidation method, an N-well implantation resist mask 25 for forming the N-well 26 is formed by a lithography process, and the N-well 26 is formed by ion implantation. The ion implantation conditions include, for example, phosphorus ions (P ⁺ ) as impurities, an energy of 800 keV, a dose of 1 × 10 ¹³ ions / cm ^2, and an energy of 300 keV.
And the dose amount is 5 × 10 ¹² / cm ² .

Thereafter, as shown in FIG. 8, the lower insulating film 2
7 and an upper insulating film 28 are formed. The lower insulating film 27 and the upper insulating film 28 have a feature that they have excellent selectivity to etching. For example, the lower insulating film 27 is a silicon oxide film of about 20 nm, and the upper insulating film 28 is about 10 nm. Of silicon nitride film.

Thereafter, as shown in FIG. 9, a resist mask 29 for ion implantation for forming the N ⁺ high concentration diffusion layer 210 is formed by lithography. After etching the upper insulating film 28 using the resist mask 29 for ion implantation as a mask, ion implantation is performed to form an N ⁺ high concentration diffusion layer 210. The ion implantation conditions include, for example, arsenic ions (As ⁺ ) as impurities, an energy of 70 keV, and a dose of 2 × 10 ¹⁵ / cm ² . The resist mask 29 for ion implantation is removed by ashing and wet processing.

Thereafter, as shown in FIG. 10, in a state where the lower insulating film 27 covers the surface of the semiconductor substrate 22,
A heat treatment for activating the implanted impurities is performed. This heat treatment can be performed, for example, at 850 ° C. for 30 minutes in a nitrogen atmosphere. Since the lower insulating film 27 covers the surface of the semiconductor substrate 22, it is possible to prevent out-diffusion of impurities and contamination from a heat treatment furnace, and to perform heat treatment at a high temperature for a long time.

Thereafter, as shown in FIG. 11, after etching the lower insulating film 27 using the upper insulating film 28 as a mask, a high melting point metal is formed by a film forming technique such as sputtering, and the high melting point metal is silicided. a heat treatment for, followed by removing unreacted refractory metal, a silicide on top of the N ⁺ high concentration diffusion layer 210 211
To form In this silicidation step, for example, titanium is used as the high melting point metal, and after annealing at 650 ° C. for 30 seconds, the unreacted high melting point metal is removed by wet treatment.
Annealing can be performed at 800 ° C. for 10 seconds.

When a semiconductor device in which a diffusion layer is silicided by such a method is manufactured, since the well of the conductivity type opposite to that of the semiconductor substrate is used for the resistance portion, the effect of the first embodiment is obtained. Thus, there is an effect that the present invention can be applied to the manufacture of a general-purpose CMOS semiconductor device.

FIGS. 12 to 17 are sectional views showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention in the order of steps. As shown in FIG. 12, an element isolation film 35 for isolating an NMOS transistor formation region 31, a PMOS transistor formation region 32, and a diffusion layer resistance formation region 33 is formed on a semiconductor substrate 34 by, for example, 400n by LOCOS oxidation.
m. As the semiconductor substrate 34, for example, a P-type silicon substrate is used.

Next, the PMOS transistor formation region 3
Then, an N well 36 is formed by ion implantation. This ion implantation condition is, for example, that phosphorus ions (P ⁺ )
And a dose of 1 × 10 at an energy of 800 keV.
¹³ doses / cm ² and energy of 300 keV, dose 5
× 10 ¹² / cm ² . The P well 3 is formed in the NMOS transistor formation region 31 and the diffusion layer resistance formation region 33.
7 is formed by ion implantation. This ion implantation condition uses, for example, boron ions (B ⁺ ) as impurities,
At an energy of 350 keV and a dose of 1 × 10 ¹³ / cm
And a dosage of 5 × 10 ¹² pieces / cm ² at ² and energy 100 keV.

Next, the NMOS transistor formation region 31
Then, a gate insulating film 38 and a gate electrode 39 are formed in the PMOS transistor formation region 32. Gate insulating film 38
Is formed to a thickness of about 10 nm by, for example, a thermal oxidation method. The gate electrode 39 has a thickness of, for example, 200 nm.
Use polysilicon. Thereafter, an N ^- low concentration diffusion layer 310 is formed in the NMOS transistor formation region 31 by ion implantation. This ion implantation condition is, for example, that phosphorus ions (P ⁺ ) are used as impurities and the energy is 20 k.
The dose amount is 2 × 10 ¹³ / cm ² in eV. PMOS
The transistor formation region 32 includes a P ⁻ low concentration diffusion layer 31.
1 is formed by ion implantation. The ion implantation conditions are, for example, an energy of 30 keV using boron ions (B ⁺ ) as impurities and a dose of 3 × 10 ¹³ / cm ² . Thereafter, the formed film is etched back to form a sidewall 312 on the side surface of the gate electrode 39. The sidewall 312 is, for example, a silicon oxide film having a width of about 10 nm.

Thereafter, as shown in FIG. 13, an insulating film composed of two layers of a lower insulating film 313 and an upper insulating film 314 is formed. The lower insulating film 313 and the upper insulating film 314
Are characterized by having excellent selectivity to etching. For example, the lower insulating film 313 is formed of a silicon oxide film of about 20 nm, and the upper insulating film 314 is formed of a silicon nitride film of about 10 nm.

Thereafter, as shown in FIG. 14, a resist mask 315 for ion implantation for forming the N ⁺ high concentration diffusion layer 316 is formed by lithography. After etching the upper insulating film 314 using the ion implantation resist mask 315 as a mask, ion implantation is performed.
An N ⁺ high concentration diffusion layer 316 is formed. This ion implantation condition is, for example, that arsenic ions (As ⁺ ) are used as impurities, the energy is 70 keV, and the dose is 2 × 10 ¹⁵ / c.
m ² . The resist mask 115 for ion implantation is removed by ashing and wet processing.

Thereafter, as shown in FIG. 15, a resist mask 317 for ion implantation for forming the P ⁺ high concentration diffusion layer 318 is formed by lithography. After the upper insulating film 314 is etched using the resist mask 317 for ion implantation as a mask, ion implantation is performed.
^{+ A} high concentration diffusion layer 318 is formed. This ion implantation condition is, for example, that boron difluoride ion (BF ²⁺ )
At a dose of 5 × 10 ¹⁵ at an energy of 50 keV.
Pieces / cm ² . Resist mask 317 for ion implantation
Is removed by ashing and wet processing.

Thereafter, as shown in FIG. 16, a low concentration diffusion layer 319 is formed in the diffusion layer resistance formation region 33 by ion implantation. For the ion implantation, for example, phosphorus ions (P ⁺ ) are used as impurities, and the energy is 40 keV and the dose is 2 × 10 ¹³ / cm ² . In this ion implantation, N ⁺
Impurities are also implanted on the high-concentration diffusion layer 316 and the P ⁺ high-concentration diffusion layer 318, but have no effect because the implantation dose is small. Further, since the lower insulating film 313 covers the semiconductor surface, the semiconductor substrate 34 by ion implantation is formed.
No defects are introduced. The layer resistance of the low concentration diffusion layer 319 can be changed by changing the ion implantation conditions.

After that, the lower insulating film 313 is
4 While the surface is covered, heat treatment for activating the implanted impurities is performed. This heat treatment, for example,
This can be performed at 850 ° C. for 30 minutes in a nitrogen atmosphere.
Since the lower insulating film 313 covers the surface of the semiconductor substrate 34, outward diffusion of impurities and contamination from a heat treatment furnace can be prevented, and heat treatment at a high temperature for a long time can be performed.

Thereafter, as shown in FIG. 17, after the lower insulating film 313 is etched using the upper insulating film 314 as a mask, a high melting point metal is formed by a film forming technique such as sputtering, and the high melting point metal is silicided. Is performed, and then the unreacted high melting point metal is removed, whereby the N ⁺ high concentration diffusion layer 316 and the P ⁺ high concentration diffusion layer 318 are removed.
And silicides 320 and 32 on the gate electrode 39.
1, 322 are formed. In this silicidation step, for example, after using titanium as a high melting point metal, annealing at 650 ° C. for 30 seconds, unreacted high melting point metal is removed by wet treatment, and annealing is performed at 800 ° C. for 10 seconds. Can be.

When a semiconductor device in which a diffusion layer is silicided by such a method is manufactured, an ion implantation step is added before etching the lower insulating film in addition to the effect of the first embodiment, and the ion implantation conditions are increased. Is changed, a resistance element having a desired layer resistance can be formed. Further, since the insulating film covers the semiconductor substrate during ion implantation, no defect is introduced into the semiconductor substrate.

[0047]

As described in detail above, according to the present invention,
Since silicide is not formed in the resistance portion, a high-resistance resistance element can be formed with a small occupied area without adding a lithography step. In addition, since the insulating film covers the semiconductor substrate, when heat treatment is performed at a high temperature for a long period of time, outward diffusion of the implanted impurities and contaminants in the heat treatment furnace do not enter the semiconductor substrate. Further, by using a well of a conductivity type opposite to that of the semiconductor substrate for the resistance portion, there is an effect that this manufacturing method can be applied to all CMOS semiconductor devices. Further, an ion implantation step is added before etching the lower insulating film, and by changing the ion implantation conditions, a resistance element having a desired layer resistance can be formed. , No defects are introduced into the semiconductor substrate.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first example of the present invention.

FIG. 2 is a sectional view showing a step subsequent to FIG. 1;

FIG. 3 is a sectional view showing a step subsequent to FIG. 2;

FIG. 4 is a sectional view showing a step subsequent to FIG. 3;

FIG. 5 is a sectional view showing a step subsequent to that of FIG. 4;

FIG. 6 is a sectional view showing a step subsequent to FIG. 5;

FIG. 7 is a sectional view illustrating a method for manufacturing a semiconductor device according to a second example of the present invention.

FIG. 8 is a sectional view showing a step subsequent to FIG. 7;

FIG. 9 is a sectional view showing a step subsequent to FIG. 8;

FIG. 10 is a sectional view showing a step subsequent to that of FIG. 9;

FIG. 11 is a sectional view showing a step subsequent to that of FIG. 10;

FIG. 12 is a sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 13 is a sectional view showing a step subsequent to FIG. 14;

FIG. 14 is a sectional view showing a step subsequent to FIG. 15;

FIG. 15 is a sectional view showing a step subsequent to that of FIG. 16;

FIG. 16 is a sectional view showing a step subsequent to that of FIG. 17;

FIG. 17 is a sectional view showing a step subsequent to FIG. 18;

FIG. 18 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional example.

FIG. 19 is a sectional view showing a step subsequent to that of FIG. 18;

FIG. 20 is a sectional view showing a step subsequent to that of FIG. 19;

FIG. 21 is a sectional view showing a step subsequent to FIG. 20;

FIG. 22 is a sectional view showing a step subsequent to that of FIG. 21.

FIG. 23 is a sectional view showing a step subsequent to FIG. 22;

[Explanation of symbols]

11, 31, 41: NMOS transistor formation region 12, 32, 42: PMOS transistor formation region 13, 33, 43: Diffusion layer resistance formation region 14, 22, 34, 44: semiconductor substrate 15, 23, 35, 45: element Separation film 16, 26, 36, 46: N well 17, 37, 47: P well 18, 38, 48: Gate insulating film 19, 39, 49: Gate electrode 21: N well resistance formation region 24: Oxide film 25: N well implantation resist masks 27, 113, 313: lower insulating film 28, 114, 314: upper insulating film 29, 115, 315, 414: N ⁺ resist mask for high concentration diffusion layer implantation 110, 310, 410: N ⁻ low-concentration diffusion layer 111,311,411: P ^- low concentration diffusion layer 112,312,412: sidewalls 116,210,316, 15: N ⁺ high concentration diffusion layer 117,317,416: P ⁺ high concentration diffusion layer implanted resist mask 118,318,417: P ⁺ high concentration diffusion layer 119,120,121,211,320,321,3
22, 418, 419, 420: silicide 319: low concentration diffusion layer 413: insulating film

Claims (9)

[Claims] A step of forming an element isolation insulating film on a semiconductor substrate to divide an NMOS transistor formation area, a PMOS transistor formation area and a diffusion layer resistance formation area; and forming the NMOS transistor formation area and the PMOS transistor. A step of forming a gate insulating film and a gate electrode in a region to be formed; a step of selectively implanting N-type ions into a source / drain region of an NMOS transistor and a portion serving as a resistance portion; Selectively implanting P-type ions into a portion to be formed, forming a sidewall insulating film on a side surface of the gate electrode, forming a lower insulating film and an upper insulating film on the entire surface, Selectively removing the high-concentration source / drain of the NMOS transistor via the lower insulating film Selectively implanting N-type ions into a region and an electrode portion of a resistor; selectively removing the upper insulating film and removing the PMOS through the lower insulating film;
A step of selectively implanting P-type ions into a portion to be a high-concentration source / drain region of a transistor; and a step of selectively removing the lower insulating film using the upper insulating film as a mask and thereafter depositing a high melting point metal film. A method of manufacturing a semiconductor device, comprising: a step of heat-treating the refractory metal film by heat treatment. 2. A step of forming an element isolation insulating film on a semiconductor substrate to partition an NMOS transistor formation area, a PMOS transistor formation area and a diffusion layer resistance formation area, and said NMOS transistor formation area and a PMOS transistor. A step of forming a gate insulating film and a gate electrode in a region to be formed; a step of selectively implanting N-type ions into a portion to be a source / drain region of an NMOS transistor;
A step of selectively implanting P-type ions into a part to be a drain region and a resistance part; a step of forming a sidewall insulating film on a side surface of the gate electrode; and a step of forming a lower insulating film and an upper insulating film on the entire surface. Selectively removing the upper insulating film and selectively implanting N-type ions into a portion to be a high-concentration source / drain region of the NMOS transistor via the lower insulating film; and selecting the upper insulating film. And selectively implanting P-type ions into the high concentration source / drain region of the PMOS transistor and a portion to be an electrode portion of a resistor through the lower insulating film, and using the upper insulating film as a mask. A semiconductor device comprising a step of selectively removing the lower insulating film and thereafter depositing a refractory metal film, and a step of heat-treating the refractory metal film into a silicide. Manufacturing method. 3. A step of forming an element isolation insulating film on a semiconductor substrate to partition an NMOS transistor formation area, a PMOS transistor formation area and a diffusion layer resistance formation area, and forming the element in the diffusion layer resistance formation area. Forming a well region of the opposite conductivity type to the semiconductor substrate;
Forming a gate insulating film and a gate electrode in a region where a MOS transistor is to be formed and a region where a PMOS transistor is to be formed; selectively implanting N-type ions into a portion serving as a source / drain region of the NMOS transistor; A step of selectively implanting P-type ions into a portion to be a source / drain region; a step of forming a sidewall insulating film on a side surface of the gate electrode; and a step of forming a lower insulating film and an upper insulating film on the entire surface. The upper insulating film is selectively removed, and the N layer is removed through the lower insulating film.
Selectively implanting N-type ions into a portion to be a high-concentration source / drain region of the MOS transistor; selectively removing the upper insulating film to remove the high-concentration source / drain of the PMOS transistor via the lower insulating film; Selectively implanting P-type ions into a portion to be a drain region, selectively removing the lower insulating film using the upper insulating film as a mask, and then depositing a refractory metal film; Converting the high-melting-point metal film into a silicide. 4. A step of forming an element isolation insulating film on a semiconductor substrate to divide an NMOS transistor formation area, a PMOS transistor formation area and a diffusion layer resistance formation area, and said NMOS transistor formation area and a PMOS transistor. A step of forming a gate insulating film and a gate electrode in a region to be formed; a step of selectively implanting N-type ions into a portion to be a source / drain region of an NMOS transistor;
Selectively implanting P-type ions into a portion to be a drain region, forming a sidewall insulating film on a side surface of the gate electrode, forming a lower insulating film and an upper insulating film on the entire surface, The insulating film is selectively removed, and the high concentration source / source of the NMOS transistor is interposed via the lower insulating film.
A step of selectively implanting N-type ions into a portion to be a drain region; and a step of selectively removing the upper insulating film and forming a P-type ion into a portion to be a high-concentration source / drain region of the PMOS transistor through the lower insulating film. Selectively implanting type ions, introducing an impurity into the semiconductor substrate in the region where the diffusion layer resistance is to be formed through the lower insulating film, and selectively etching the lower insulating film using the upper insulating film as a mask. A method for manufacturing a semiconductor device, comprising: a step of applying a high-melting-point metal film after the above-mentioned removal; and a step of performing heat treatment to silicide the high-melting-point metal film. 5. The method of manufacturing a semiconductor device according to claim 1, wherein said lower insulating film is an oxide film, and said upper insulating film is a nitride film. 6. A step of forming a low-concentration diffusion layer serving as a diffusion layer resistance portion on a surface of a semiconductor substrate, a step of forming a lower insulating film and an upper insulating film, and after selectively removing the upper insulating film, N-type ions are selectively implanted through the lower insulating film, and the upper insulating film is selectively removed. Then, P-type ions are selectively implanted through the lower insulating film, thereby forming an NMOS transistor and a PMOS respectively. Forming a high-concentration source / drain diffusion layer of a transistor; forming a high-melting-point metal film after selectively removing the lower-layer insulating film using the upper-layer insulating film as a mask; Forming a film into a silicide. 7. The step of forming the low concentration diffusion layer serving as the diffusion layer resistance portion is the same as the step of forming the low concentration source / drain diffusion layer of the NMOS transistor or the low concentration source / drain diffusion layer of the PMOS transistor. 7. The method of manufacturing a semiconductor device according to claim 6, wherein 8. The semiconductor device according to claim 6, wherein the step of forming the low concentration diffusion layer serving as the diffusion layer resistance section is a step of forming a well of a conductivity type opposite to that of the semiconductor substrate. Manufacturing method. 9. A step of forming a lower insulating film and an upper insulating film, and after selectively removing the upper insulating film, selectively implanting N-type ions through the lower insulating film and further forming the upper insulating film. Is selectively removed, and P is interposed through the lower insulating film.
By selectively implanting the type ions, the high-concentration source
A step of forming a drain diffusion layer, a step of forming a low-concentration diffusion layer serving as a diffusion layer resistance section on the surface of the semiconductor substrate via the lower insulating film, and selectively forming the lower insulating film using the upper insulating film as a mask. Forming a high-melting-point metal film after the step of removing, and heat-treating the high-melting-point metal film into a silicide.