JPS6014471A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6014471A JPS6014471A JP12094583A JP12094583A JPS6014471A JP S6014471 A JPS6014471 A JP S6014471A JP 12094583 A JP12094583 A JP 12094583A JP 12094583 A JP12094583 A JP 12094583A JP S6014471 A JPS6014471 A JP S6014471A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- substrate
- groove
- polysilicon
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229920001296 polysiloxane Polymers 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
(技術分野)
この発明は半導体装置の製造方法、詳しくはシリコング
ー)MO8型半導体装置の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a silicon MO8 type semiconductor device.
(従来技術)
従来のシリコンf−)MO8型半導体装置のダート電極
・ソースドレイン拡散層の形成工程を第1図に示す。第
1図(a)において、11はシリコン基板であシ、まず
この基板11の表面部にLOCO8工程によシフイール
ド酸化膜12を選択的に形成する。次に、シリコン基板
11の表面が露出している部分、すなわちアクティブ領
域に第1図(b)に示すようにダート酸化膜13を酸化
によp形成し、さらに全面にr−)電極となるポリシリ
コン14’1cVDで堆積させる。その後、ポリシリコ
ン14をバターニングして、第1図(C)に示すように
ダート電極となる部分のみを残し、さらにダート酸化膜
13もバターニングして前記残存ポリシリコン14下の
必要部分のみを残す。しかる後、ソース・ドレイン拡散
層を形成するため、シリコン基板11に対するイオン注
入15e行う。そして、その後アニールを行うと、第1
図(d)に示すようにソース・ドレイン拡散層16が形
成される。(Prior Art) FIG. 1 shows a process for forming a dirt electrode/source/drain diffusion layer of a conventional silicon f-)MO8 type semiconductor device. In FIG. 1(a), reference numeral 11 is a silicon substrate. First, a field oxide film 12 is selectively formed on the surface of the substrate 11 by the LOCO8 process. Next, a dirt oxide film 13 is formed by oxidation on the exposed surface of the silicon substrate 11, that is, the active region, as shown in FIG. 1(b), and the entire surface becomes an r-) electrode. Polysilicon 14' is deposited at 1 cVD. Thereafter, the polysilicon 14 is buttered to leave only the portion that will become the dirt electrode as shown in FIG. leave. Thereafter, ion implantation 15e into the silicon substrate 11 is performed to form source/drain diffusion layers. Then, when annealing is performed after that, the first
As shown in Figure (d), source/drain diffusion layers 16 are formed.
この方法によシ、低抵抗で浅い接合を形成する場合、注
入するイオン種として、シリコン中への固溶度が高く、
かつ後のアニールに際してシリコン中での拡散速度の述
いものを選択する必要がある。その意味でnu・イオン
種としてはAsが適するが、p型イオン種としては適す
るイオン種がなく、浅い接合を形成するのが非常に困難
でちった。さらに、Asを用いたn型拡散層の深さもよ
シ浅くする必要があるが、従来の工程ではそれが非常に
困難である。When forming a shallow junction with low resistance using this method, the ion species to be implanted have high solid solubility in silicon.
In addition, it is necessary to select a description of the diffusion rate in silicon during the subsequent annealing. In this sense, As is suitable as a nu ion species, but there is no ion species suitable as a p-type ion species, making it extremely difficult to form a shallow junction. Furthermore, it is necessary to reduce the depth of the n-type diffusion layer using As, but this is extremely difficult with conventional processes.
(発明の目的)
この発明は上記の点に鑑みなされたもので、低抵抗で実
効的な接合深さの浅い接合を形成することができる半導
体装置の製造方法を提供することを目的とする。(Object of the Invention) The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can form a junction with low resistance and an effective shallow junction depth.
(実施例) 以下この発明の一実施例を第2図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
第2図(a)において、21はシリコン基板であり、ま
ずこの基板21の表面部にLOCO8工程によりフィー
ルド酸化膜22を選択的に形成する。In FIG. 2(a), 21 is a silicon substrate, and first, a field oxide film 22 is selectively formed on the surface of this substrate 21 by the LOCO8 process.
次に、シリコン基板21の表面が露出している部分の所
定個所、すなわちアクティブ領域中のダ一工程によシ第
2図(b)に示すように溝23を所定深さに形成する。Next, a groove 23 is formed at a predetermined depth in a predetermined portion of the exposed surface of the silicon substrate 21, that is, in the active region, by a die process, as shown in FIG. 2(b).
しかる後、r−)酸化を行って、溝23の内壁および基
板11の露出表面に第2図(c)に示ずようにケ゛−ト
酵化膜24全形成する。続いて、基板21上の全面、詳
しくは、前記ケ゛−1・酸化膜24で覆われた溝部なら
びに基板表面およびフィールド酸化膜22上に同じく第
2図(e)に示すようにポリシリコン25を形成する。Thereafter, r-) oxidation is carried out to completely form a Kate fermented film 24 on the inner wall of the groove 23 and the exposed surface of the substrate 11, as shown in FIG. 2(c). Subsequently, polysilicon 25 is deposited on the entire surface of the substrate 21, specifically, on the groove portion covered with the oxide film 24, the substrate surface, and the field oxide film 22, as shown in FIG. 2(e). Form.
しかる後。After that.
メカノケミカルポリッシング法により、第2図(d)に
示すごとく前記溝部にのみケ゛−ト電極としてポリシリ
コン25が残留するようにポリシリコン25を除去する
。続いて、ダート酸化膜24も、第2図(d)に示すご
とく溝部にのみ残すように不要部分を除去する。しかる
後、通常の方法によシイオン注入26とその後のアニー
ルを行う。これにより、第2図(d)に示すようにソー
ス・ドレイン拡散層27をシリコン基板21に形成する
。The polysilicon 25 is removed by mechanochemical polishing so that the polysilicon 25 remains only in the groove as a gate electrode, as shown in FIG. 2(d). Subsequently, unnecessary portions of the dirt oxide film 24 are also removed so that they remain only in the grooves, as shown in FIG. 2(d). Thereafter, silicon ion implantation 26 and subsequent annealing are performed in a conventional manner. As a result, a source/drain diffusion layer 27 is formed in the silicon substrate 21 as shown in FIG. 2(d).
なお、以上の方法においてメカノケミカルポリッシング
法とは、通常の研摩に際してエツチング液を用いてケミ
カルなニツチングと物理的すなオフちメカニカルな研摩
を同時に行う方法であり、佃[摩によるダメージの少な
い鏡面を得ることのできる方法である。In addition, in the above method, the mechanochemical polishing method is a method that simultaneously performs chemical nitching and physical polishing using an etching solution during normal polishing. This is a method that allows you to obtain
(発明の効果)
以上の一実施例から明らかなようにこの発明の方法では
、アクティブ領域中のダート領域となる部分の選択喰刻
とメカノケミカルボIJツシング法の併用によシ、半埋
込み型のケ゛−ト電極をJ形成する。したがって、ソー
ス・ト°レイン4広散層の形成に際し、実効的な接合深
さを浅く形成すること75;可能となる。同時に、実際
の接合は深いものを形成することができるため、低抵抗
な接合をフ杉成できる。(Effects of the Invention) As is clear from the above embodiment, the method of the present invention uses a combination of selective etching of the dirt region in the active region and the mechanochemical IJ tushing method. A gate electrode is formed. Therefore, when forming the diffusion layer of the source train 4, it becomes possible to form the effective junction depth 75 to be shallow. At the same time, since the actual bond can be formed deep, it is possible to form a low-resistance bond.
さらに、半埋込み型のダート電極の形成は、素子の平担
化の点でも有効な技術となる。また、実効的な接合深さ
を浅くすることは、MO8素子を小さくした時に生じる
ショートチャネル効果を抑制することと、ケ゛−1長が
短くたった時に生じるバンチスルーを防ぐことが可能と
なシ、超高密度のMO3ICの実現に資するところ大で
ある。Furthermore, forming a semi-buried dirt electrode is an effective technique in terms of flattening the device. In addition, reducing the effective junction depth can suppress the short channel effect that occurs when the MO8 element is made smaller, and prevent bunch-through that occurs when the cable length is shortened. This greatly contributes to the realization of ultra-high density MO3IC.
第1図は従来のシリコングーFMO8型半導体装置のダ
ート電極・ソースドレイン拡散層の形成工程を示す断面
図、第2図はこの発明の半導体装置の製造方法の一実施
例を示す断面図である。
21・・・シリコン基板、23・・・溝、24・・・r
−)酸化膜、25・・・ポリシリコン、26・・・イオ
ン注入。
27・・・ソース・ドレイン拡散層。
特許出願人 沖電気工業株式会社
第1図
第 2 図
−33:FIG. 1 is a cross-sectional view showing a step of forming a dirt electrode/source/drain diffusion layer of a conventional silicon FMO8 type semiconductor device, and FIG. 2 is a cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention. . 21...Silicon substrate, 23...Groove, 24...r
-) Oxide film, 25... polysilicon, 26... ion implantation. 27... Source/drain diffusion layer. Patent applicant Oki Electric Industry Co., Ltd. Figure 1 Figure 2-33:
Claims (1)
を形成する工程と、その溝の内壁および基板の表面にダ
ートe化膜を形成する工程と、そのダート酸化膜で覆わ
れた溝部および基板表面上にポリシリコンを形成する工
程と、そのポリシリコンをメカノケミカルポリッシング
によシ溝部にのみ残す工程と、その匈イオン注入とアニ
ールとによってソース・ドレイン拡散層をシリコングー
に形成する工程とを具備してなる半導体装置の製造方法
。A step of forming a groove to a predetermined depth in a portion of a silicon substrate that will become a dirt region, a step of forming a dirt e-oxide film on the inner wall of the groove and the surface of the substrate, and a step of forming a groove portion covered with the dirt oxide film and A process of forming polysilicon on the surface of the substrate, a process of leaving the polysilicon only in the trench by mechanochemical polishing, and a process of forming source/drain diffusion layers in silicone by ion implantation and annealing. A method of manufacturing a semiconductor device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12094583A JPS6014471A (en) | 1983-07-05 | 1983-07-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12094583A JPS6014471A (en) | 1983-07-05 | 1983-07-05 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6014471A true JPS6014471A (en) | 1985-01-25 |
Family
ID=14798855
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12094583A Pending JPS6014471A (en) | 1983-07-05 | 1983-07-05 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6014471A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01179359A (en) * | 1988-01-05 | 1989-07-17 | Nec Corp | Manufacture of semiconductor device |
JPH01179362A (en) * | 1988-01-05 | 1989-07-17 | Nec Corp | Manufacture of semiconductor device |
JPH01179361A (en) * | 1988-01-05 | 1989-07-17 | Nec Corp | Manufacture of semiconductor device |
JPH01179360A (en) * | 1988-01-05 | 1989-07-17 | Nec Corp | Manufacture of semiconductor device |
EP0655786A2 (en) * | 1993-11-30 | 1995-05-31 | Sony Corporation | Gate electrode formed in trench and method of making the same |
JP2011049410A (en) * | 2009-08-28 | 2011-03-10 | National Institute Of Advanced Industrial Science & Technology | Inverter circuit and logic gate circuit using silicon carbide insulated gate field effect transistor |
-
1983
- 1983-07-05 JP JP12094583A patent/JPS6014471A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01179359A (en) * | 1988-01-05 | 1989-07-17 | Nec Corp | Manufacture of semiconductor device |
JPH01179362A (en) * | 1988-01-05 | 1989-07-17 | Nec Corp | Manufacture of semiconductor device |
JPH01179361A (en) * | 1988-01-05 | 1989-07-17 | Nec Corp | Manufacture of semiconductor device |
JPH01179360A (en) * | 1988-01-05 | 1989-07-17 | Nec Corp | Manufacture of semiconductor device |
EP0655786A2 (en) * | 1993-11-30 | 1995-05-31 | Sony Corporation | Gate electrode formed in trench and method of making the same |
EP0655786A3 (en) * | 1993-11-30 | 1996-02-28 | Sony Corp | Gate electrode formed in trench and method of making the same. |
JP2011049410A (en) * | 2009-08-28 | 2011-03-10 | National Institute Of Advanced Industrial Science & Technology | Inverter circuit and logic gate circuit using silicon carbide insulated gate field effect transistor |
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