JPH06132501A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent characteristics deterioration such as short-channel effect, etc., of an element caused by the heat treatment during anti-fuse film formation. CONSTITUTION:After a thin insulating film 7 is formed in a specified area, an upper electrode 3 is formed thereon, an impurity is injected on a substrate through the film 7, and then the injected impurity is diffused to form a lower electrode 8 as an impurity diffusion layer under the electrode 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, a semiconductor device in which a thin insulating film that insulates the upper electrode and the lower electrode from each other is formed on a substrate and the thin insulating film is electrically broken to electrically connect the upper electrode and the lower electrode to allow writing Regarding the method.

[0002]

2. Description of the Related Art Generally, an antifuse ROM using an antifuse film, which is a thin insulating film, is a lower electrode (impurity diffusion layer) which is electrically insulated from each other above and below the antifuse film. By applying a high potential to the upper electrode (conductive film), the intervening antifuse film is destroyed, and the two electrodes are electrically connected to each other, whereby a programmable ROM dedicated to writing can be obtained.

A conventional anti-fuse ROM is shown in FIGS.
The structure is as shown in. 7 shows a structure of a cross section taken along the line AA 'in FIG. 6, and FIG. 8 shows an enlarged view of the vicinity of the antifuse film for electrically insulating the upper electrode and the lower electrode in the structure shown in FIG. There is. The method for creating this ROM is the following method. That is, the element isolation region 16 and the gate electrode 14 are formed on the substrate with the gate insulating film interposed therebetween. An interlayer insulating film 15 is deposited thereon by a CVD method, and n ⁺ or p ⁺ impurities are ion-implanted,
By annealing at ˜900 ° C., impurities diffuse and lower electrodes 18 and 20 are formed. Next, a region where the anti-fuse film 17 is to be formed is etched to make a hole, the anti-fuse film 17 is formed by the CVD method or the thermal oxidation method, and the electrode polysilicon 1 serving as an upper electrode is formed thereon.
3 is deposited, an interlayer insulating film 19 is further deposited, the interlayer insulating film 19 in a region for forming an electrode is etched, and the electrode 12 is wired.

[0004]

However, since the conventional process for forming the antifuse film is after the lower electrode is formed, heat treatment at 900 ° C. or higher is applied during the formation of the antifuse film. The impurities diffused into the lower electrode are further diffused outward, the distance between the source region and the drain region is narrowed, and the short channel effect of the element or the like occurs, which causes the deterioration of the transistor characteristics.

[0005]

Thus, according to the present invention, a thin insulating film for insulating the upper electrode and the lower electrode is formed on the substrate and the thin insulating film is electrically destroyed. When forming a semiconductor device in which the upper electrode and the lower electrode can be electrically connected to each other for writing, a thin insulating film is formed in a predetermined region, an upper electrode is formed on the thin insulating film, and then a thin insulating film is formed on the substrate. A method for manufacturing a semiconductor device is provided, which comprises implanting impurities, then diffusing the implanted impurities, and forming a lower electrode as an impurity diffusion layer below the upper electrode.

In short, according to the present invention, an antifuse film is first formed on a substrate, then an upper electrode is formed, and then impurities are injected and heat treatment is performed to form a lower electrode. Is diffused under the upper electrode,
It has a structure in which the lower electrode and the upper electrode overlap with each other with the antifuse insulating film interposed therebetween. In the present invention, since the anti-fuse film is formed prior to the formation of the source / drain regions, it is possible to prevent unnecessary diffusion of the source / drain regions.

The substrate used in the present invention is not particularly limited, but a silicon substrate can usually be used. Next, an antifuse film which is a thin insulating film is deposited on this substrate. The antifuse film can be formed by a usual method. For example, as an antifuse film, Si ₃ N ₄ /
When a SiO ₂ film is used, it can be formed by a method of depositing Si ₃ N ₄ by a CVD method and performing an oxidation treatment to form a SiO ₂ film on the Si ₃ N ₄ . Further, an upper electrode made of polysilicon or the like is formed thereon. Next, in order to form the source and drain regions as the lower electrode in the substrate surface layer, impurities such as boron, phosphorus, and arsenic are ion-implanted, and then annealed to diffuse the impurities. Can be formed. At this time, the condition of the annealing treatment is 800 to 900 ° C., and depending on the treatment temperature,
Impurities can diffuse under the upper electrode to form the lower electrode. Further, an antifuse element of the present invention can be obtained by depositing a wiring layer or the like on the above element by a known method.

In the present invention, since the ion implantation into the source / drain formation region is performed after the upper electrode is formed, the upper electrode is formed in a shape excluding the ion-implanted portion. Since the ion implantation is performed through the thin antifuse insulating film, the implantation conditions are the same as those in the conventional method. Polysilicon is often used for the upper electrode, but any commonly used material such as silicide of a refractory metal may be used.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of forming an anti-fuse ROM according to the present invention will be described in detail with reference to FIG. First, the element isolation region 6 and the gate electrode 4 are formed on the silicon substrate by a known method (FIG. 5A). As the interlayer insulating film 5, SiO ₂ is used as C
A film having a thickness of about 0.1 μm is laminated by the VD method. Next, the substrate is exposed by etching the region in which the antifuse film is to be formed (FIG. 5B).

Next, a Si ₃ N ₄ film is formed to a thickness of 0.0 by the CVD method.
The antifuse film 7 is obtained by stacking the layers with a thickness of 08 μm and further oxidizing them to form a SiO ₂ film with a thickness of 0.003 μm on the Si ₃ N ₄ film (FIG. 5C). Further, a polysilicon film having a thickness of 0.25 μm is stacked and etched to form a polysilicon electrode 3 (FIG. 5D).

Next, As is set to 80 KeV, 5 × 10 ¹⁵ cm ^-2
By ion implantation at 800 ° C. and then annealing at 800 ° C., As diffuses under the polysilicon electrode, and lower electrodes 8 and 9 are formed (FIG. 5E). Then NS
G or BPSG is formed by CVD to a film thickness of 0.8 μm
Laminated with NSG or BPS on polysilicon electrode
G is removed by etching, and Al is laminated as a wiring layer to obtain the shapes shown in FIGS. 1 and 2. FIG. 2 shows a sectional structure between AA ′ in FIG.

The overlapping portion of the upper electrode and the lower electrode partially overlaps with each other via the anti-fuse film 7, as shown in FIGS. In this embodiment, the overlapping width is finally 0.2.
It becomes about 0.5 μm.

[0013]

The deterioration such as the short channel effect of the transistor is deteriorated by the heat treatment after ion implantation into the source and drain regions. Therefore, when the anti-fuse film is formed, the cell structure is changed, and by stacking the source and drain regions before ion implantation, deterioration of characteristics such as a short channel effect can be suppressed.

[Brief description of drawings]

FIG. 1 is a schematic plan view of a ROM of the present invention.

FIG. 2 is a schematic cross-sectional view taken along the line AA ′ of the ROM of FIG.

FIG. 3 is a schematic enlarged view of the ROM of FIG.

FIG. 4 is a schematic enlarged view of the ROM of FIG.

FIG. 5 is a schematic explanatory view of the manufacturing process of the ROM of the present invention.

FIG. 6 is a plan view of a conventional ROM.

FIG. 7 is a schematic cross-sectional view taken along the line AA ′ of the conventional ROM.

FIG. 8 is an enlarged view of the ROM of FIG. 7.

[Explanation of symbols]

 1 Contact Area 2 Al Wiring 3 Polysilicon Electrode (Upper Electrode) 4 Gate Electrode 5 Interlayer Insulation Film 6 Element Isolation Area 7 Antifuse Film (Thin Insulation Film) 8 Lower Electrode 9 Lower Electrode

Claims (1)

[Claims] 1. A semiconductor device in which a thin insulating film that insulates an upper electrode and a lower electrode is formed on a substrate, and the thin insulating film is electrically broken to electrically connect the upper electrode and the lower electrode to allow writing. At the time of forming, a thin insulating film is formed in the predetermined region, an upper electrode is formed on the thin insulating film, impurities are implanted into the substrate through the thin insulating film, and then the implanted impurities are diffused. And forming a lower electrode as an impurity diffusion layer below the upper electrode.