JPS6489360A - Semiconductor storage device and manufacture thereof - Google Patents
Semiconductor storage device and manufacture thereofInfo
- Publication number
- JPS6489360A JPS6489360A JP62245488A JP24548887A JPS6489360A JP S6489360 A JPS6489360 A JP S6489360A JP 62245488 A JP62245488 A JP 62245488A JP 24548887 A JP24548887 A JP 24548887A JP S6489360 A JPS6489360 A JP S6489360A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- groove
- oxide film
- type impurity
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Abstract
PURPOSE:To perform a high integration by forming a groove on a field region, employing it as a capacitor, and connecting the source region of a transistor to the charge storage region of a capacitor. CONSTITUTION:An N-type impurity layer 10 and a field oxide film 2 are sequentially formed on a P-type semiconductor substrate 1. The film 2 is penetrated through a field region, and a groove 3 of the state that the substrate 1 is dug is formed. An N-type impurity layer 4 is formed only on the inner wall of the groove 3, and a first gate oxide film 5 is then formed. Then, after a polysilicon 6 is patterned, a second gate oxide film 7 is formed, and a polysilicon 8 is patterned. N-type impurity layers 9a, 9b are formed by ion implanting. An insulating film 12 is formed, a hole is opened on the layer 9a, a polysilicide (wiring layer) 11 is formed, connected to the layer 9b and wired.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62245488A JPH07105476B2 (en) | 1987-09-29 | 1987-09-29 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62245488A JPH07105476B2 (en) | 1987-09-29 | 1987-09-29 | Semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6489360A true JPS6489360A (en) | 1989-04-03 |
JPH07105476B2 JPH07105476B2 (en) | 1995-11-13 |
Family
ID=17134406
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62245488A Expired - Fee Related JPH07105476B2 (en) | 1987-09-29 | 1987-09-29 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07105476B2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59184555A (en) * | 1983-04-02 | 1984-10-19 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit device and manufacture thereof |
JPS61179568A (en) * | 1984-12-29 | 1986-08-12 | Fujitsu Ltd | Manufacture of semiconductor memory device |
-
1987
- 1987-09-29 JP JP62245488A patent/JPH07105476B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59184555A (en) * | 1983-04-02 | 1984-10-19 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit device and manufacture thereof |
JPS61179568A (en) * | 1984-12-29 | 1986-08-12 | Fujitsu Ltd | Manufacture of semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPH07105476B2 (en) | 1995-11-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |