JPH07105476B2 - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH07105476B2 JPH07105476B2 JP62245488A JP24548887A JPH07105476B2 JP H07105476 B2 JPH07105476 B2 JP H07105476B2 JP 62245488 A JP62245488 A JP 62245488A JP 24548887 A JP24548887 A JP 24548887A JP H07105476 B2 JPH07105476 B2 JP H07105476B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- insulating film
- impurity layer
- semiconductor substrate
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は半導体装置に関するもので、特にダイナミック
メモリセルの微細化に使用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device, and is particularly used for miniaturization of a dynamic memory cell.
（従来の技術） この種の従来技術を第３図により説明する。例えばＰ型
基板21にフィールド酸化膜22を形成し、フィールド領域
の外側に溝23を形成する。この溝23の内壁にＮ型不純物
層24を形成し、更に第１のゲート酸化膜25を形成する。
溝23を埋め込む状態で第１のゲート電極（つまりキャパ
シタ電極）26例えばポリシリコンを形成したのち、第２
のゲート酸化膜27を形成し、その上に第２のゲート電極
28例えばポリシリコンを形成する。その後、例えばAsの
イオン注入法によりＮ型不純物層29a,29bを形成し、該
層29bと接続する状態で配線材料31例えばポリサイドを
形成する。(Prior Art) This kind of prior art will be described with reference to FIG. For example, the field oxide film 22 is formed on the P-type substrate 21, and the groove 23 is formed outside the field region. An N-type impurity layer 24 is formed on the inner wall of the groove 23, and a first gate oxide film 25 is further formed.
After forming the first gate electrode (that is, the capacitor electrode) 26, for example, polysilicon in the state of filling the groove 23, the second gate electrode (that is, the capacitor electrode) 26 is formed.
Forming a gate oxide film 27 on the second gate electrode
28 For example, polysilicon is formed. After that, the N-type impurity layers 29a and 29b are formed by, for example, an As ion implantation method, and the wiring material 31 such as polycide is formed in a state of being connected to the layers 29b.
（発明が解決しようとする問題点） 第４図は第３図のパターン平面図である。この図を見て
も分かる通り、フィールド領域の外側に溝23を形成する
と、フィールド領域との余裕α（32で示される）が必要
になり、メモリセルの短辺方向は、基沿の径をx,フィー
ルドの幅をｙとすると、「ｘ＋ｙ＋２α」となる。この
記憶装置の高集積化の最大の難関は、上記メモリセルの
短辺方向の縮少であると考えられる。(Problems to be Solved by the Invention) FIG. 4 is a pattern plan view of FIG. As can be seen from this figure, when the groove 23 is formed outside the field region, a margin α (shown by 32) with the field region is required, and the short side direction of the memory cell has a diameter along the base line. If x and the width of the field are y, then "x + y + 2α" is obtained. It is considered that the biggest difficulty in high integration of this memory device is reduction of the memory cell in the short side direction.
本発明の目的は、上記問題点を改善し、高集積化に適し
た半導体記憶装置を提供することにある。An object of the present invention is to provide a semiconductor memory device that solves the above problems and is suitable for high integration.
［発明の構成］ （問題点を解決するための手段と作用） 本発明の半導体記憶装置は、第１導電型の半導体基体
と、この半導体基体上に形成されたフィールド絶縁膜
と、このフィールド絶縁膜を貫きかつ前記半導体基体を
掘って形成された溝と、この溝の内壁に形成され一方の
キャパシタ電極を形成する第２導電型の第１の不純物層
と、上記溝の内壁に形成された第１の絶縁膜と、上記溝
を埋め込みかつ上記フィールド絶縁膜上に形成された他
方のキャパシタ電極と、上記半導体基体上に形成された
第２の絶縁膜と、この第２の絶縁膜上に形成されたゲー
ト電極を有し、かつ上記半導体上に形成された第２導電
型の第２の不純物層をソース、ドレインとして有するMO
Sトランジスタと、MOSトランジスタのソース、ドレイン
の一方と上記第１の不純物層とを接続するように形成さ
れた第２の導電型の第３の不純物層と、上記MOSトラジ
スタのソース、ドレインの他方と接続するように形成さ
れた配線層とを具備したことをとしている。[Configuration of Invention] (Means and Actions for Solving Problems) A semiconductor memory device of the present invention is a semiconductor substrate of the first conductivity type, a field insulating film formed on the semiconductor substrate, and the field insulating film. A groove formed by penetrating the film and digging the semiconductor substrate, a second conductivity type first impurity layer formed on the inner wall of the groove to form one capacitor electrode, and formed on the inner wall of the groove A first insulating film, the other capacitor electrode that fills the trench and is formed on the field insulating film, a second insulating film formed on the semiconductor substrate, and a second insulating film on the second insulating film. MO having the formed gate electrode and having the second impurity layer of the second conductivity type formed on the semiconductor as the source and the drain
An S transistor, a third impurity layer of the second conductivity type formed so as to connect one of the source and drain of the MOS transistor to the first impurity layer, and the other of the source and drain of the MOS transistor. And a wiring layer formed so as to be connected to.
即ち本発明は、フィールド領域に溝を形成し、これをキ
ャパシタとして用い、トランジスタのソース領域とキャ
パシタの電荷蓄積領域を接続して、タイナミックメモリ
セルとしての機能をもたせ、本発明の目的である高集積
化を達成しようとするものである。That is, the present invention is to form a groove in the field region, use this as a capacitor, connect the source region of the transistor and the charge storage region of the capacitor to have a function as a dynamic memory cell, and it is an object of the present invention. It is intended to achieve high integration.
（実施例） 以下図面を参照して本発明の一実施例を説明する。まず
Ｐ型５Ωの半導体基板１上にAsイオンを、ドーズ量４×
1012cm-2の条件でイオン注入し、Ｎ型不純物層10を形成
する（第１図（ａ））。次に950℃程度のアニールによ
り、イオン注入のダメージを回復させた後、フィールド
酸化膜２を形成する。この時、先に形成した不純物層10
の一部が、フィールド酸化膜２の外側にくるようにする
（第１図（ｂ））。次にフィールド領域に、フィールド
酸化膜２を貫ぬきかつ基板１を堀った状態の溝３を形成
する。この時の溝形成は、RIE（Reactive Ion Etchin
g）法を用い、マスク材として、SiO2あるいはSiO2/SiN
の二層膜内などをCVD法により形成しておく。次に溝内
壁部のみに、Asイオン注入法などを用いてＮ型不純物層
４を形成する。次にアニールにより、イオン注入のダメ
ージを回復させた後、第１のゲート酸化膜５を形成する
（第１図（ｃ））。次に第１のポリシリコン６をパター
ン形成した後、第２のゲート酸化膜７を形成し、第２の
ポリシリコン８をパターン形成する。その後Asイオン
を、ドーズ量５×1015cm-2の条件でイオン注入し、Ｎ型
不純物層9a,9bを形成する（第１図（ｄ））。その後に
層間絶縁膜12を形成し、Ｎ型不純物層9b上に穴を開け、
ポリサイド（配線層）11を形成し、Ｎ型不純物層9bと接
続させて配線するものである（第１図（ｅ））。Embodiment An embodiment of the present invention will be described below with reference to the drawings. First, As ions were placed on the P-type 5Ω semiconductor substrate 1 with a dose amount of 4 ×.
Ions are implanted under the condition of 10 12 cm -2 to form an N-type impurity layer 10 (FIG. 1 (a)). Next, the field oxide film 2 is formed after the damage due to the ion implantation is recovered by annealing at about 950 ° C. At this time, the impurity layer 10 previously formed
Is partially located outside the field oxide film 2 (FIG. 1 (b)). Next, in the field region, a groove 3 is formed, which penetrates the field oxide film 2 and dug the substrate 1. Groove formation at this time is performed by RIE (Reactive Ion Etchin
g) method, using SiO 2 or SiO 2 / SiN as mask material
The inside of the two-layer film is formed by the CVD method. Next, the N-type impurity layer 4 is formed only on the inner wall of the groove by using the As ion implantation method or the like. Next, the damage of the ion implantation is recovered by annealing, and then the first gate oxide film 5 is formed (FIG. 1 (c)). Next, after patterning the first polysilicon 6, the second gate oxide film 7 is formed and the second polysilicon 8 is patterned. After that, As ions are ion-implanted under the condition of a dose amount of 5 × 10 15 cm −2 to form N-type impurity layers 9a and 9b (FIG. 1 (d)). After that, an interlayer insulating film 12 is formed, a hole is opened on the N-type impurity layer 9b,
A polycide (wiring layer) 11 is formed and connected to the N-type impurity layer 9b for wiring (FIG. 1 (e)).
このような方法で形成されたメモリセルの構造は、第１
図（ｅ）の如くＰ型半導体基板１上にフィールド絶縁膜
２を形成し、この絶縁膜２を貫きかつ基板１を堀った状
態の溝３を形成し、この溝３の内壁にＮ型不純物層４を
形成し、また溝３の内壁に誘電体層５を形成し、溝３を
埋め込む状態でフィールド絶縁膜２上にゲート電極（つ
まり本発明でいうキャパシタ電極）６を形成し、基板１
上に誘電体層７を形成し、この誘電体層７上にゲート電
極８を形成し、基板１上にＮ型不純物層9a,9b（ソー
ス，ドレイン）を形成し、不純物層9aと不純物層４を接
続する状態でＮ型不純物層10を形成し、不純物層9bと接
続する状態で配線層11を形成した構成となっている。The structure of the memory cell formed by such a method is
As shown in FIG. 2E, a field insulating film 2 is formed on a P-type semiconductor substrate 1, a groove 3 is formed so as to penetrate the insulating film 2 and the substrate 1 is dug, and an N-type is formed on the inner wall of the groove 3. The impurity layer 4 is formed, the dielectric layer 5 is formed on the inner wall of the groove 3, and the gate electrode (that is, the capacitor electrode in the present invention) 6 is formed on the field insulating film 2 in a state where the groove 3 is filled. 1
A dielectric layer 7 is formed on the dielectric layer 7, a gate electrode 8 is formed on the dielectric layer 7, N-type impurity layers 9a and 9b (source, drain) are formed on the substrate 1, and the impurity layer 9a and the impurity layer are formed. In this structure, the N-type impurity layer 10 is formed in the state of connecting 4 and the wiring layer 11 is formed in the state of connecting to the impurity layer 9b.
第２図は第１図（ｅ）のパターン平面図である。この第
２図と第４図とを比較すれば分かるように、第４図の従
来例ではメモリーセルの短辺方向は、「ｘ＋ｙ＋２α」
となってしまうが、本発明の第２図では、フィールド領
域と溝の余裕αが不要なので「ｘ＋ｙ」となる。従って
セル面積の縮少が可能となり、LSIの高集積化に役立つ
ものである。FIG. 2 is a pattern plan view of FIG. 1 (e). As can be seen by comparing FIG. 2 and FIG. 4, in the conventional example of FIG. 4, the short side direction of the memory cell is “x + y + 2α”.
However, in FIG. 2 of the present invention, the margin .alpha. Between the field region and the groove is unnecessary, so that "x + y" is obtained. Therefore, the cell area can be reduced, which is useful for high integration of LSI.
「発明の効果」 以上説明した如く本発明によれば、ダイナミックメモリ
セルの短辺方向の縮少化が可能となるので、高集積化さ
れた半導体記憶装置が得られるものである。[Advantages of the Invention] As described above, according to the present invention, since it is possible to reduce the dynamic memory cells in the short side direction, it is possible to obtain a highly integrated semiconductor memory device.
第１図は本発明の一実施例の製造工程を示す断面図、第
２図はそのパターン平面図、第３図は従来装置の断面
図、第４図はそのパターン平面図である。 １……Ｐ型基板、２……フィールド酸化膜、３……溝、
４……Ｎ型の第１の不純物層、５……第１の誘電体層、
６……第１のゲート電極、７……第２の誘電体層、８…
第２のゲート電極、9a,9b……Ｎ型の第２の不純物層、1
0……Ｎ型の第３の不純物層、11……配線層、12……層
間絶縁膜。FIG. 1 is a sectional view showing a manufacturing process of an embodiment of the present invention, FIG. 2 is a pattern plan view thereof, FIG. 3 is a sectional view of a conventional device, and FIG. 4 is a pattern plan view thereof. 1 ... P-type substrate, 2 ... field oxide film, 3 ... groove,
4 ... N-type first impurity layer, 5 ... first dielectric layer,
6 ... First gate electrode, 7 ... Second dielectric layer, 8 ...
Second gate electrode, 9a, 9b ... N-type second impurity layer, 1
0 ... N-type third impurity layer, 11 ... Wiring layer, 12 ... Interlayer insulating film.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/04 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 27/04
Claims (1)
体上に形成されたフィールド絶縁膜と、このフィールド
絶縁膜を貫きかつ前記半導体基体を掘って形成された溝
と、この溝の内壁に形成され一方のキャパシタ電極を形
成する第２導電型の第１の不純物層と、上記溝の内壁に
形成された第１の絶縁膜と、上記溝を埋め込みかつ上記
フィールド絶縁膜上に形成された他方のキャパシタ電極
と、上記半導体基体上に形成された第２の絶縁膜と、こ
の第２の絶縁膜上に形成されたゲート電極を有し、かつ
上記半導体基体上に形成された第２導電型の第２の不純
物層をソース、ドレインとして有するMOSトランジスタ
と、このMOSトランジスタのソース、ドレインの一方と
上記第１の不純物層とを接続するように形成された第２
導電型の第３の不純物層と、上記MOSトランジスタのソ
ース、ドレインの他方と接続するように形成された配線
層とを具備したことを特徴とする半導体記憶装置。1. A semiconductor substrate of the first conductivity type, a field insulating film formed on the semiconductor substrate, a groove penetrating the field insulating film and digging the semiconductor substrate, and an inner wall of the groove. A first impurity layer of the second conductivity type which is formed on one side to form one of the capacitor electrodes, a first insulating film formed on the inner wall of the groove, and the groove which fills the groove and is formed on the field insulating film. The other capacitor electrode, a second insulating film formed on the semiconductor substrate, and a gate electrode formed on the second insulating film, and a second electrode formed on the semiconductor substrate. A MOS transistor having a conductive type second impurity layer as a source and a drain, and a second transistor formed so as to connect one of the source and the drain of the MOS transistor to the first impurity layer.
A semiconductor memory device comprising: a conductive third impurity layer; and a wiring layer formed so as to be connected to the other of the source and the drain of the MOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62245488A JPH07105476B2 (en) | 1987-09-29 | 1987-09-29 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62245488A JPH07105476B2 (en) | 1987-09-29 | 1987-09-29 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6489360A JPS6489360A (en) | 1989-04-03 |
| JPH07105476B2 true JPH07105476B2 (en) | 1995-11-13 |
Family
ID=17134406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62245488A Expired - Fee Related JPH07105476B2 (en) | 1987-09-29 | 1987-09-29 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07105476B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59184555A (en) * | 1983-04-02 | 1984-10-19 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit device and manufacture thereof |
| JPS61179568A (en) * | 1984-12-29 | 1986-08-12 | Fujitsu Ltd | Manufacture of semiconductor memory device |
-
1987
- 1987-09-29 JP JP62245488A patent/JPH07105476B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6489360A (en) | 1989-04-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |