JP3096043B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a method for forming a contact in a MOSFET, a DRAM, or the like.

(Prior Art) In recent years, with the advance of semiconductor technology, particularly the advance of microfabrication technology, the so-called MOS type DRAM has been rapidly advanced in integration and capacity.

With this high integration, the area of a capacitor for storing information (charge) has been reduced, and as a result, a memory error has been read out erroneously, or a memory error such as the destruction of the memory content due to α rays has become a problem. Has become.

As one of methods for solving such a problem and achieving higher integration and higher capacity, a MOS capacitor is stacked on a memory cell region, and one electrode of the capacitor is formed on a semiconductor substrate. A memory cell structure called a stacked memory cell has been proposed in which the area occupied by the capacitor is substantially increased by conducting one electrode of the switching transistor to increase the capacitance of the MOS capacitor. ing.

As shown in FIGS. 4 (a) to 4 (c), this stacked memory cell has one memory cell region in which an element is isolated by an element isolation insulating film 102 formed in a p-type silicon substrate 101. Inside, source / drain regions 104a and 104b composed of n-type diffusion layers and source / drain regions 104a and 104b
A MOSFET as a switching transistor is formed by forming a gate electrode 106 with a gate insulating film 105 interposed therebetween, and a gate electrode 106 of the MOSFET and a MOSFET of an adjacent memory cell are formed thereon so as to contact the source region 104a of the MOSFET. A capacitor is formed by sandwiching a capacitor insulating film 111 between a first capacitor electrode 110 and a second capacitor electrode 112 formed on the gate electrode (word line) via an insulating film 107.

With such a structure, the capacitance can be increased without increasing the element area.

However, the DR of such a stacked memory cell structure
Also in AM, as the device becomes finer due to the higher integration, the distance between the storage node contact and the gate electrode (indicated by l1 in FIG. 4A) and the distance between the bit line contact and the gate electrode are increased. The distance between them (Fig. 4 (a) shows l2
) Has been forced to shrink. Therefore, a short circuit between the storage node and the gate electrode and between the bit line and the gate electrode is likely to occur, which causes a decrease in reliability.

Therefore, in order to prevent a short circuit between the storage node and the gate electrode and between the bit line and the gate electrode, at least one of the storage node contact and / or the bit line contact is provided despite the reduction of the memory cell occupation area. Forming a first interlayer insulating film on the gate electrode, forming a first contact, embedding a conductor in the first contact, and forming a second interlayer insulating film on the upper layer; A structure has been proposed in which a portion of the second interlayer insulating film is selectively etched to form a second contact so as to expose the conductor (Japanese Patent Application No. 1-233815).

That is, FIGS. 5A to 5D are plan views showing two bits adjacent to each other in the bit line direction of a DRAM as an example of the stacked memory cell structure, and are sectional views taken along line AA ′ of FIG. B
A cross-sectional view taken along the line -B 'and a line CC' are shown.

In this DRAM, the top and side walls of the gate electrode 206 of the MOSFET are covered with an insulating film 207 and an insulating film 208, and the bit line contact and the storage node contact are in contact with the source / drain regions 204a and 204b and from the gate electrode. Is formed so as to be in contact with the polycrystalline silicon layer 216 as a buried layer formed so as to be buried to a high position, and is formed in a state very close to the gate electrode. Is the same as that of the conventional DRAM having the stacked memory cell structure shown in FIG.

According to this structure, the storage node contact and the bit line contact are preliminarily buried to a position higher than the gate electrode.
The second contact can be formed by appropriately setting the height of the polycrystalline silicon layer and the height of the gate electrode in accordance with the etching rate of the interlayer insulating film. Can be completely prevented even if it is formed shifted from the polycrystalline silicon layer.

For this reason, even when a contact having a high aspect ratio like the bit line contact in this example is formed, scuffing of the substrate due to over-etching can be prevented, and a highly reliable memory cell can be obtained.

In addition, a short circuit with the gate electrode due to misalignment in the photolithography technique can be prevented, and a margin of a pattern in consideration of misalignment can be omitted. Therefore, miniaturization of a memory cell can be achieved.

(Problems to be Solved by the Invention) However, even in such a structure, short-circuiting can be prevented only with respect to the second contact, and when the third contact is formed thereafter. There is still a risk of short circuit.

For example, if the second contact is a bit line contact, it is possible to prevent a short circuit with the gate electrode when opening the bit line contact for the reason described above. In the case where an electrode is formed, a second interlayer insulating film is formed, and then a third contact as a storage node contact is opened in the buried layer (polycrystalline silicon layer), the polycrystalline silicon Since the layer is located lower than the bit line electrode, there is a problem that a short circuit occurs between the storage node contact and the bit line.

The present invention has been made in view of the above circumstances, and prevents a short circuit between a bit line and a gate electrode, a storage node electrode and a bit line, and a storage node electrode and a gate electrode, despite the reduction of the memory cell occupation area. It is another object of the present invention to provide a small and highly reliable memory cell.

(Means for Solving the Problems) In order to achieve the above object, an invention according to claim 1 covers a source / drain region and a gate electrode formed on a surface of a substrate of one conductivity type and an upper layer of the gate electrode. An interlayer insulating film, a first contact formed in the interlayer insulating film, and exposing the source / drain region;
A first and a second buried conductor layer buried to a position higher than the gate electrode, and a bit disposed at a position lower than the first buried conductor layer in the interlayer insulating film. A second contact formed in the interlayer insulating film to connect the bit line to the second buried conductor layer; a capacitor formed in an upper layer of the interlayer insulating film; And a third contact that is formed on the surface of the capacitor and connects the capacitor and the first buried conductor layer.

Further, the invention according to claim 2 includes a source / drain region and a gate electrode formed on a surface of a substrate of one conductivity type;
An interlayer insulating film covering an upper layer of the gate electrode, a first contact formed in the interlayer insulating film and exposing the source / drain region, and a first contact in the first contact.
First and second buried conductor layers buried to a position higher than the gate electrode; a capacitor disposed in the interlayer insulating film at a position lower than the first buried conductor layer; A second contact formed in the film and connecting the capacitor and the second buried conductor layer; a bit line formed in an upper layer of the interlayer insulating film; formed on a surface of the interlayer insulating film; A third contact for connecting the bit line and the first buried conductor layer.

Further, the invention according to claim 3 includes a step of forming a source / drain region and a gate electrode formed on a surface of a substrate of one conductivity type; a step of forming an interlayer insulating film on the gate electrode; Forming a first contact in the film exposing the source / drain region;
Embedding first and second buried conductor layers in the first contact to a position higher than the gate electrode; and forming a bit line in the interlayer insulating film at a position lower than the first buried conductor layer. Disposing; forming a second contact in the interlayer insulating film for connecting the bit line to the second buried conductor layer; forming a capacitor on the interlayer insulating film And a step of forming a third contact connecting the capacitor and the first buried conductor layer on the surface of the interlayer insulating film.

Further, the invention according to claim 4 includes a step of forming a source / drain region and a gate electrode formed on a surface of a substrate of one conductivity type; a step of forming an interlayer insulating film on the gate electrode; Forming a first contact in the film exposing the source / drain region;
Burying the first and second buried conductor layers in the first contact to a position higher than the gate electrode; and locating a capacitor in the interlayer insulating film at a position lower than the first buried conductor layer. Arranging, forming a second contact in the interlayer insulating film connecting the capacitor and the second buried conductor layer, and forming a bit line on the interlayer insulating film And forming a third contact connecting the bit line and the first buried conductor layer on the surface of the interlayer insulating film.

(Operation) According to the above configuration, at the time of opening a contact formed later among the capacitor or bit line contacts, the already formed capacitor or bit line is below the height of the first buried conductor layer. However, there is no possibility that a short circuit will occur between them. In addition, there is no concern about occurrence of a short circuit with a gate electrode formed below the gate electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1 (a) to 1 (c) show two adjacent DRAMs having a stacked memory cell structure in the bit line direction according to the embodiment of the present invention.
A plan view showing a bit portion, a cross-sectional view taken along line AA 'of FIG.
FIG.

In this DRAM, the top and side walls of the gate electrode 6 of the MOSFET are covered with an insulating film 7 and an insulating film 8, and the bit line contact and the straight node contact make contact with the source / drain regions 4a and 4b and the gate electrode 6a. The bit line is formed so as to be in contact with the polycrystalline silicon layer 16 as a buried layer formed so as to be buried to a higher position, and the bit line is buried in the groove 17, and is located at a position lower than the polycrystalline silicon layer 16. To be located
It is characterized in that it is formed in a state very close to the gate electrode, and the other parts are the same as those of the conventional DRAM of the stacked memory cell structure shown in FIG.

That is, the source / drain regions constituting the source / drain regions are formed in the active regions separated by the element isolation insulating film 2 formed in the p-type silicon substrate 1 having a specific resistance of about 5Ω · cm.
A MOSFET is formed by the shaped diffusion layers 4a and 4b and a gate electrode 6 formed between the source / drain regions via a gate insulating film 5, and is formed in an interlayer insulating film 13 formed thereover. Via the first contact 14
A polycrystalline silicon layer 16 as a buried layer is formed so as to be in contact with n-type diffusion layers 4a and 4b, so that polycrystalline silicon layer 16 is in contact with polycrystalline silicon layer 16 and at a lower position than polycrystalline silicon layer 16. Then, a polycrystalline silicon layer 23 is buried in a groove 17 formed in the interlayer insulating film 13 to form a bit line. Further, a storage node electrode 26 is formed so as to be in contact with the polycrystalline silicon layer 16, and a capacitor insulating film 27 is interposed between the storage node electrode 26 and the upper plate electrode 28 to form a capacitor.

The gate electrodes 6 are continuously arranged in one direction of the memory array to form a word line.

Next, a method of manufacturing the DRAM will be described with reference to the drawings.

2 (a) to 2 (j) are diagrams showing the manufacturing process of this DRAM, and FIGS. 2 (a), 2 (c), 2 (e), 2 (g) FIG. 2 (i) shows A- of FIG. 1 (a).
FIGS. 2 (b), 2 (d), 2 (f), 2 (h), and 2 (j) are sectional views taken along the line BB 'of FIG.

First, as shown in FIGS. 2 (a) and 2 (b), an element isolation insulating film 2 and a punch-through are formed on the surface of a p-type silicon substrate 1 having a specific resistance of about 5 Ω · cm by a normal LOCOS method. After forming a p-type diffusion layer 3 for a stopper, a gate insulating film 5 made of a silicon oxide film having a thickness of about 10 nm is formed by a thermal oxidation method, and then a polycrystalline silicon film, a metal film, or a gate electrode material is formed. A polycide film is deposited on the entire surface, and an insulating film such as a silicon oxide film is deposited thereon by a CVD method to a thickness of about 100 to 300 nm by a CVD method, and the gate electrode 6 and the gate electrode 6 The upper insulating film 7 is simultaneously patterned.

Then, using this gate electrode 6 as a mask, As ions are ion-implanted to form source / drain regions 4a and 4b composed of n-type diffusion layers, thereby forming a MOSFET as a switching transistor. The depth of this diffusion layer is, for example, 150 n
m. Thereafter, an insulating film made of a silicon oxide layer having a thickness of about 100 nm or less is deposited on the entire surface by a CVD method, and the entire surface is etched by a reactive ion etching method.
The side wall insulating film 8 is left on the side surface of the gate electrode 6 in a self-aligned manner.

Next, as shown in FIGS. 2 (c) and 2 (d), a silicon oxide film having a thickness of about 20 nm is formed on the upper layer by a thermal oxidation method, and the interlayer insulating film is formed on the entire surface by a CVD method. A silicon oxide film 13 is deposited as a film, and then the interlayer insulating film 13 is patterned by a photolithography method and reactive ion etching to form a first storage node contact 14 and a first bit line contact 15 at the same time. I do. At this time, after patterning the resist using the photolithography method, it is possible to form a wide contact hole only in an upper portion by performing isotropic etching and then performing anisotropic etching. Also, after patterning the resist using a photolithographic method, anisotropic etching is performed, and after opening the contact, the upper part is expanded by further performing isotropic etching,
It is also possible to form a wide contact hole only in the upper part.

After this, a high concentration phosphorus-doped polycrystalline silicon film
16 is deposited so that the film thickness is at least 1/2 of the short side of the contact holes 14 and 15 (here, deposited to be at least 1/2 of the short side is because the contact holes are completely buried. ),
Thereafter, the entire surface is etched until the surface of the interlayer insulating film is exposed, so that the polycrystalline silicon film 16 remains only in the contact. Here, the doping of the polycrystalline silicon film is performed by depositing a thin polycrystalline silicon film of about 500 mm, ion-implanting, for example, As ions, and further forming the polycrystalline silicon film so as to be at least half of the short side of the contact hole. It is also possible to adopt a method in which a film is deposited again, As ions are implanted, a silicon oxide film is deposited by a CVD method, and heat treatment is performed.

Furthermore, in this step, a method of embedding the polycrystalline silicon film on the entire surface and then performing etch back was used. For example, a polycrystalline silicon film or a monocrystalline silicon film is selectively grown only in the contact hole. May be adopted.

Thereafter, a groove 17 is formed at the bit line forming position by a photolithography method and reactive ion etching. At this time, the depth of the groove is set to be higher than the gate electrode. Here, R is a mask pattern for forming a groove.

Then, as shown in FIGS. 2 (e) and 2 (f), the entire surface is oxidized to cover the surface of the polycrystalline silicon layer 16 with an oxide film. Accordingly, even when the polysilicon layer of the storage node contact portion is exposed due to misalignment during the formation of the trench 17 for forming the bit line, a short circuit with the bit line is prevented.

Thereafter, a second bit line contact is formed, a polycrystalline silicon layer 22 serving as a bit line electrode is deposited so that the bit line groove 17 is sufficiently filled, and conduction with the diffusion layer 4a is established.

Thereafter, as shown in FIG. 2 (g) and FIG. 2 (h), the entire surface is etched back to a position lower than the polycrystalline silicon layer 16 which is a buried layer, and further, the resistance of the bit line is reduced. For this purpose, a tungsten layer 23 is grown only on the bit line 22 by a selective epitaxial growth method, and a second interlayer insulating film 24 is deposited and planarized to form a second storage node contact.
Here, R is a mask pattern for forming the second storage node contact.

Further, as shown in FIGS. 2 (i) and 2 (j), the second storage node contact
After forming 25, a polycrystalline silicon film is deposited on the entire surface, and after doping, patterning is performed by photolithography and reactive ion etching to form a polycrystalline silicon layer 16.
The storage node electrode 26 is formed so as to be electrically connected to.
Then, a silicon nitride film having a thickness of 10 nm is deposited on the upper layer by a CVD method, and then oxidized in a water vapor atmosphere at about 900 ° C. for about 30 minutes to form a silicon oxide film. The capacitor insulating film 27 composed of the two-layer film is formed. Then, a polycrystalline silicon film is further deposited on this upper layer, and after doping, patterning is performed by a photolithography method and reactive ion etching to form a plate electrode.

Thereafter, a silicon oxide film is formed as a protective film, and the DRAM as shown in FIGS. 1A to 1C is completed.

According to this method, when forming the second storage node contact, the second storage node contact may be formed so as to be in contact with the polycrystalline silicon film buried up to a position higher than the gate electrode in advance, and the bit line already formed Is formed in the groove and located at a position lower than the polycrystalline silicon film, so that there is no possibility of short-circuit with the bit line.

In addition, since the storage node contact and the bit line contact need only be formed so as to be in contact with the polycrystalline silicon film buried beforehand to a position higher than the gate electrode, there is no risk of short-circuit with the gate electrode. . Further, the etching time required for forming the contact can be reduced.

Therefore, even when a contact having a high aspect ratio such as the bit line contact in this embodiment is formed, the substrate can be prevented from being scrambled due to over-etching, and a highly reliable memory cell can be obtained. .

In addition, a short circuit between the bit line and the storage node electrode, and each of the bit line and the storage node electrode and the gate electrode due to misalignment in the photolithography technology can be prevented, and a margin of a pattern considering the misalignment can be omitted. Therefore, miniaturization of the memory cell can be achieved.

Furthermore, if a capacitor is formed on the bit line in this manner, the structure is such that the bit line is covered with a plate electrode and shielded, so that even if the cell is miniaturized, malfunction due to interference between adjacent bit lines may occur. Generation can be prevented.

In these embodiments, the storage node contact is formed after the bit is formed. However, as shown in FIGS. 3A to 3C, the storage node contact is formed as an example. It is also possible to form a bit line later.

 In addition, the reference numerals of the respective units are based on the above-described embodiment.

In addition, in the above embodiment, the DRAM having the stacked memory cell structure has been described, but this method is not limited to the DRAM having the stacked memory cell structure, and includes a step of forming a contact having a high aspect ratio. This is also an effective method for forming other devices including the same.

〔The invention's effect〕

As described above, according to the semiconductor memory device of the present invention, after the first interlayer insulating film is formed on the gate electrode, the first contact is formed on the storage node contact and the bit line contact. This first
And a groove for burying either the storage node electrode or the bit line and a groove that is connected to the groove and contacts the conductive layer in the corresponding one of the first contacts. 2 and a storage node electrode or a bit line is buried in the trench, and the conductor of the other one of the storage node contact or the bit line contact is filled with the storage node electrode or the bit already buried. Because it is located above the line, the storage node electrode or bit line that has already been formed, when opening the contact formed after the storage node contact or bit line contact, Because they are below the height, short-circuits with them may occur. No risk of, it is possible to improve the miniaturization and reliability.

[Brief description of the drawings]

FIGS. 1A to 1C show a DRAM having a stacked memory cell structure according to an embodiment of the present invention, and FIGS. 2A to 2C.
FIG. 3 (j) is a manufacturing process diagram of the DRAM having the stacked memory cell structure, and FIGS. 3 (a) to 3 (c) are diagrams showing the DRAM having the stacked memory cell structure according to another embodiment of the present invention. , FIG. 4 and FIG. 5 each show a DR of a conventional stacked memory cell structure.
It is a figure which shows AM. 1 ... p-type silicon substrate, 2 ... element isolation insulating film, 3
... channel stopper, 4a, 4b ... source / drain regions, 5 ... gate insulating film, 6 ... gate electrode, 7 ... insulating film, 8 ... side wall insulating film, 9 ... silicon oxide film, 10 ...
... silicon nitride film, 11 ... polycrystalline silicon film, 12 ... silicon oxide film, 13 ... interlayer insulating film, 14 ... first storage node contact, 15 ... first bit line contact, 16 ... Polycrystalline silicon film, 17 groove, 18 insulating film, 19 second storage node contact, 22
Bit line, 23 ... tungsten layer, 24 ... insulating film, 25 ...
... second bit line contact, 26 ... storage node electrode, 27 ... capacitor insulating film, 28 ... plate electrode,
101 ... p-type silicon substrate, 102 ... element isolation insulating film,
103 ... 104a, 104b ... n-type diffusion layer, 105 ... gate insulating film, 106 ... gate electrode, 107 ... insulating film, 108 ... storage node contact, 110 ... storage node electrode, 111 ... capacitor Insulating film, 112 ... plate electrode.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazumasa Sunouchi 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Inc. (72) Inventor Satoshi Inoue 1, Komukai Toshiba-cho, Kochi-ku, Kawasaki-shi, Kanagawa Inside Toshiba Research Institute, Inc. (72) Inventor Akihiro Nitayama 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki, Kanagawa Prefecture Inside Toshiba Research Institute, Inc. (56) References JP-A-3-167874 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (4)

(57) [Claims] A source formed on a surface of a substrate of one conductivity type;
A drain region and a gate electrode; an interlayer insulating film covering an upper layer of the gate electrode; a first contact formed in the interlayer insulating film to expose the source / drain region; First and second buried conductor layers buried to a position higher than the gate electrode; a bit line disposed in the interlayer insulating film at a position lower than the first buried conductor layer; The bit line and the second layer are formed in an insulating film.
A second contact connecting the embedded conductive layer to the first conductive layer; a capacitor formed on the interlayer insulating film; and a capacitor formed on the surface of the interlayer insulating film and connecting the capacitor to the first embedded conductive layer. And a third contact. 2. A source formed on a surface of a substrate of one conductivity type.
A drain region and a gate electrode; an interlayer insulating film covering an upper layer of the gate electrode; a first contact formed in the interlayer insulating film to expose the source / drain region; First and second buried conductor layers buried to a position higher than the gate electrode; a capacitor disposed in the interlayer insulating film at a position lower than the first buried conductor layer; A second contact formed in the film and connecting the capacitor and the second buried conductor layer, a bit line formed in an upper layer of the interlayer insulating film, and formed on a surface of the interlayer insulating film; A semiconductor memory device comprising: a third contact connecting the bit line and the first buried conductor layer. A source formed on a surface of the substrate of one conductivity type;
Forming a drain region and a gate electrode; forming an interlayer insulating film on the gate electrode; forming a first contact in the interlayer insulating film that exposes the source / drain region; Embedding first and second buried conductor layers in the first contact to a position higher than the gate electrode; and forming a bit line in the interlayer insulating film at a position lower than the first buried conductor layer. Disposing; forming a second contact in the interlayer insulating film for connecting the bit line to the second buried conductor layer; forming a capacitor in an upper layer of the interlayer insulating film And forming a third contact on the surface of the interlayer insulating film, the third contact connecting the capacitor and the first buried conductor layer. Production method. 4. A source formed on the surface of a substrate of one conductivity type.
Forming a drain region and a gate electrode; forming an interlayer insulating film on the gate electrode; forming a first contact in the interlayer insulating film that exposes the source / drain region; Burying first and second buried conductor layers in the first contact to a position higher than the gate electrode; and placing a capacitor in the interlayer insulating film at a position lower than the first buried conductor layer. Disposing; forming a second contact in the interlayer insulating film for connecting the capacitor and the second buried conductor layer; and forming a bit line on the interlayer insulating film. Forming a third contact connecting the bit line and the first buried conductor layer on the surface of the interlayer insulating film. Production method.