JPH03283658A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To attain miniaturization by a method wherein a conductor of one remainder of storage node contacts or bit line contacts is positioned above a storage node electrode and others which are buried. CONSTITUTION:On the occasion of formation of a storage node contact 14, it is brought into contact with the upper side of a polycrystalline Si film which is buried beforehand up to a higher position than a gate electrode 6, and a bit line 22 already formed is positioned in a groove. Since this bit line 22 is provided at a lower position than the polycrystalline Si film, occurrence of short circuit with the bit line 22 is prevented. By bringing a storage node contact 19 and a bit line contact into contact with the upper side of the polycrystalline Si film buried beforehand up to the position higher than the gate electrode 6, besides, the possibility of occurrence of short circuit with the gate electrode 6 is eliminated. According to this constitution, a miniaturized semiconductor storage device can be obtained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device and a method for manufacturing the same;
In particular, it relates to a method of forming contacts in MOSFETs, DRAMs, etc.

(Prior Art) In recent years, due to advances in semiconductor technology, particularly advances in microfabrication technology, so-called MOS type DRAMs are rapidly becoming more highly integrated and have larger capacities.

With this increase in integration, the area of capacitors that store information (charge) has decreased, resulting in problems such as erroneous reading of memory contents or soft errors in which memory contents are destroyed by A-rays, etc. It has become.

One way to solve these problems and achieve higher integration and larger capacity is to stack MOS capacitors on the memory cell area, and connect one electrode of the capacitor with a MOS capacitor formed on the semiconductor substrate. A memory cell structure called a stacked memory cell has been proposed in which the area occupied by the capacitor is substantially expanded and the capacitance of the MOS capacitor is increased by making the MOS capacitor electrically conductive with one electrode of the switching transistor. ing.

This stacked memory cell is shown in FIGS. 4(a) to 4(C).
), source/drain regions 104a and 104b made of n-swelled diffusion layers are provided in one memory cell region separated by an element isolation insulating film 102 formed in a p-type silicon substrate 101; A gate electrode 1 ( ) 6 is formed between the source/drain regions 104 a and 104 b via a gate insulating film 105 to constitute a MOSFET as a switching transistor.
A first capacitor electrode 11 is formed on the gate electrode 106 of the MOSFET and the gate electrode (word line) of the MOSFET of the adjacent memory cell via an insulating film 107 so as to contact the source region 104a of the OSFET.
0 and a capacitor insulating film 111 is sandwiched between a second capacitor electrode 112 to form a capacitor.

With such a structure, the capacitance can be increased without increasing the element area.

However, the DR of such a stacked memory cell structure
Even in AM, as elements become finer due to higher integration, the distance between the storage node contact and the gate electrode (indicated by J!■ in Fig. 4(a)) and the distance between the bit line contact and the gate electrode become smaller. (Figure 4 (a)
) and 12) have also had to be reduced.

This often leads to short circuits between the storage node and the gate electrode and between the bit line and the gate electrode, which causes a decrease in reliability.

Therefore, despite the reduction in the area occupied by memory cells,
In order to prevent short circuits between the storage node and the gate electrode and between the bit line and the gate electrode, at least one of the storage node contact and/or the bit line contact has a first interlayer insulating film on the gate electrode. After the formation, a first contact is formed and a conductor is embedded in this first contact, and a second interlayer insulating film is further formed on this first contact, and a part of this second interlayer insulating film is selected. Japanese Patent Application No. 1-233815 has proposed a structure in which a second contact is formed by etching the conductor to expose the conductor.

That is, FIGS. 5(a) to 5(d) are a plan view showing two bits adjacent in the bit line direction of a DRAM having an example of this stacked memory cell structure, and a sectional view taken along the line AA',
A BB' sectional view and a cc' sectional view are shown.

In this DRAM, the top and sidewalls of the gate electrode 206 of the MOSFET are covered with an insulating film 207 and an insulating film 208, and the bit line contacts and storage node contacts are formed in source/drain regions 204a and 204b.
When in contact with the polycrystalline silicon layer 216 as a buried layer, which is formed to be buried to a higher level than the gate electrode, the polycrystalline silicon layer 216 is formed in extremely close proximity to the gate electrode. Other parts are similar to the conventional DRAM having a stacked memory cell structure shown in FIG.

According to this structure, the storage node contact and the bit line contact need only be formed so as to be in contact with the polycrystalline silicon film (conductor layer) buried in advance to a higher position than the gate electrode. If the height of the silicon layer and the height of the gate electrode are set appropriately depending on the etching rate of the interlayer insulating film, even if the second contact is formed offset from this polycrystalline silicon layer, Short-circuiting between the gate electrode and the second contact can be completely prevented.

Therefore, like the bit line contact in this example,
Even when forming a contact having a high aspect ratio, it is possible to prevent the plate from gouging due to over-etching, and a highly reliable memory cell can be obtained.

In addition, it is possible to prevent short circuits with the gate electrode due to misalignment in photolithography technology, and it is possible to eliminate margins in the pattern that take misalignment into account.
It becomes possible to miniaturize memory cells.

(Issue [1] to be solved by the invention) However, even when such a structure is adopted, Sii
It is only possible to prevent short circuits with respect to the second contact; there is still a risk of short circuits during the subsequent formation of the third contact.

For example, when the second contact is connected to the bit line contact, it is true that when the bit line contact is opened, short circuit with the gate electrode can be prevented for the reasons mentioned above, but after that, the bit line contact is closed. An electrode is formed, a second interlayer insulating film is formed, and then a storage node contact and a third contact are formed in the buried layer (polycrystalline silicon layer). Since the polycrystalline silicon layer is located at a lower level than the bit line electrode, there is a problem in that a short circuit occurs between the storage node contact and the bit line.

The present invention has been made in view of the above-mentioned circumstances, and does not struggle with reducing the area occupied by memory cells, and is capable of connecting bit lines and gate electrodes, storage node electrodes and bit lines, and storage node electrodes and gate electrodes. The purpose is to prevent short circuits and provide a small and highly reliable memory cell.

(Means for Solving Il[1) Therefore, in the present invention, after forming a first interlayer insulating film on the gate electrode, a first contact is formed in the formation portion of the storage node contact and the bit line contact. A conductive material is buried in the first contact of the lever, and a groove for burying either a storage node electrode or a bit line is connected to the groove, and the conductive material is embedded in the corresponding contact among the first contacts. forming a second contact in contact with the body, embedding a storage node electrode or a bit line in the trench, the conductor of the remaining one of the storage node contact or the bit line contact being already embedded; It is located in a layer above the storage node electrode or bit line.

(Function) According to the above configuration, when forming a hole for a storage node contact or a bit line contact to be formed later, the storage node electrode or bit line that has already been formed is placed below the height of the buried conductor layer. Therefore, there is no risk of short-circuiting with these. Further, there is no fear of short-circuiting with the gate electrode formed in an upper layer.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1<a> to FIG. 1(c) are a plan view showing two bits adjacent in the bit line direction of a DRAM having a stacked memory cell structure according to an embodiment of the present invention, a sectional view taken along line A-A, and B. -B'
A cross-sectional view is shown.

, :(7) In DRAM, the gate electrode 6 of MOSFET
The top and side walls are covered with an insulating film 7 and an insulating film 8, and a bit line contact and a storage node contact are formed to contact the source/drain regions 4a and 4b and to be buried to a level higher than the gate electrode 6. Polycrystalline silicon layer 1 as a buried layer
6, and the bit line is buried in the trench 17 and is formed in close proximity to the gate electrode so as to be located at a lower position than the polycrystalline silicon layer 16. Other parts are similar to the conventional DRAM having a stacked memory cell structure shown in FIG.

That is, in the active region separated by the element isolation insulating film 2 formed in the p-type silicon substrate 1 with a specific resistance of about 5 Ω·C-, the n-
A MOSFET is constituted by the expansion diffusion layers 4a and 4b and a gate electrode 6 formed between these source and drain regions with a gate insulating film 5 interposed therebetween. A polycrystalline silicon layer 16 as a buried layer is formed so as to be in contact with the n-swelled diffusion layers 4a and 4b via the first contact 14. A groove 17 is formed in the interlayer insulating film 13 at a position lower than the polycrystalline silicon layer 16.
A polycrystalline silicon layer 23 is embedded therein to constitute a bit line.

A storage node electrode 26 is further formed in contact with this polycrystalline silicon layer 16, and a capacitor is formed by interposing a capacitor insulating film 27 between it and the upper plate electrode 28.

The gate electrodes 6 are continuously arranged in one direction of the memory array to form word lines.

Next, a method for manufacturing this DRAM will be explained with reference to the drawings.

FIGS. 2(a) to 2(0) and FIGS. 2(^) to 2(E) are diagrams showing the second process of manufacturing this DRAM, and in each figure, (a) to (a ) is A in Figure 1(a)
-A' sectional views, (A) to (1) correspond to BB' sectional views.

As shown in Figure 2 (a) and Figure 2 (^),
After forming an element isolation insulating film 2 and a PU diffusion layer 3 for a punch-through stopper on the surface of a pm silicon substrate 1 with a resistivity of about 5 Ω·C by the usual LOCO3 method,
After forming a gate insulating film 5 made of a silicon oxide film with a thickness of approximately Ion- by a thermal oxidation method, a polycrystalline silicon film, a metal film, or a polycide film as a gate electrode material is deposited on the entire surface, and then CVD is applied to the upper layer. An insulating film such as a silicon oxide film is deposited to a thickness of about 100 to 300 ns by a method, and the gate electrode 6 and the insulating film 7 on the gate electrode 6 are simultaneously patterned using photolithography and anisotropic etching.

Using this gate electrode 6 as a mask, As ions are implanted to form source/drain regions 4a and 4b consisting of n-type diffusion layers, thereby forming a MOSFET as a switching transistor. The depth of this diffusion layer is
For example, it is set to about 150 n-. Thereafter, an insulating film made of a silicon oxide layer with a film thickness of about 100 ns or less is deposited on the entire surface using the CVD method, and the entire surface is etched using the reactive ion etching method to insulate the side walls in a self-aligned manner on the side surfaces of the gate electrode 6. The membrane 8 is left behind.

Next, as shown in FIGS. 2(b) and 2(B), a silicon oxide film with a thickness of about 20 nm is formed on this upper layer by thermal oxidation, and then interlayer insulation is formed by CVD over the entire surface. A silicon oxide film 13 is deposited as a film, and then this interlayer insulating film 13 is patterned by photolithography and reactive ion etching to simultaneously form a first storage node contact 14 and a first bit line contact 15. do. At this time, after patterning the resist using photolithography, isotropic etching is performed.
Furthermore, by performing anisotropic etching, it is also possible to form a wide contact hole only in the upper portion. In addition, after patterning the resist using photolithography, anisotropic etching is performed to open the contacts, and then isotropic etching is performed to widen the upper blade part and create a wide contact hole only in the upper part. It is also possible to form

After this, highly phosphorus-doped polycrystalline silicon Wk
16 is deposited so that the film thickness is 1/2 or more of the short side of the contact hole 14.15.The reason why it is deposited so that the film thickness is 172 or more of the short side is to completely fill the contact hole.) Then, by etching the entire surface of the interlayer insulating film until the surface is exposed, the polycrystalline silicon film 16 is etched.
remains only within the contact. Here, the doping of this polycrystalline silicon film is carried out by depositing a thin polycrystalline silicon film of about 500 layers, then implanting, for example, As ions into the polycrystalline silicon film so that the polycrystalline silicon film becomes more than 1/2 of the short side of the contact hole. It is also possible to deposit a silicon film again, implant As ions, deposit a silicon oxide film by CVD, and perform heat treatment.

Furthermore, in the second step, a method was used in which a polycrystalline silicon film was buried over the entire surface and then etched back. You may take the method of growing it.

Thereafter, a groove 17 is formed at the bit line forming position by photolithography and reactive ion etching. At this time, the depth of the groove is set to be above the gate electrode. Here, R is a mask pattern for forming grooves.

Then, as shown in FIGS. 2(C) and 2(C), the entire surface is oxidized to cover the surface of the polycrystalline silicon layer 16 with an oxide film. Thereby, even if the polycrystalline silicon layer of the storage node contact portion is exposed due to misalignment during the formation of the trench 17 for forming the bit line, a short circuit with the bit line can be prevented.

Thereafter, a second bit line contact is formed, and a polycrystalline silicon layer 22, which will become a bit line electrode, is deposited so that the bit line 17 is sufficiently filled to establish electrical conduction with the diffusion layer 4a.

After that, as shown in FIG. 2(d) and FIG. 2(D>), the entire surface is etched back to a position lower than the buried layer polycrystalline silicon layer 16, and furthermore, the resistance of the bit line is lowered. Therefore, a tungsten layer 23 is grown only on the bit line 22 by selective epitaxial growth, and a second interlayer insulating film 24 is deposited and planarized to form a second storage node contact.

Here, R is a mask pattern for forming the second storage node contact.

Furthermore, as shown in FIG. 2(e) and FIG. 2(E), in this way the second storage node contact 2
After forming the polycrystalline silicon layer 16, a polycrystalline silicon film is deposited on the entire surface, doped, and then patterned by photolithography and reactive ion etching to form the polycrystalline silicon layer 16.
A storage node electrode 26 is formed so as to be electrically conductive. Then, after depositing a silicon nitride film with a thickness of 10 nm on this upper layer by the CVD method, oxidation is performed for about 30 minutes in a water vapor atmosphere at about 900°C to form a silicon oxide film.
A capacitor insulating film 27 consisting of a two-layer film of a silicon nitride film and a silicon oxide film is formed.

Then, a polycrystalline silicon film is further deposited on this upper layer,
After doping, the plate electrode 28 is patterned by photolithography and reactive ion etching.
form.

After this, a silicon oxide film is formed as a protective film, and the first
The RAM is completed as shown in FIGS. 1A to 1C.

According to this method, when forming the second storage node contact, it is only necessary to form the second storage node contact so as to contact the polycrystalline silicon film buried in advance to a higher position than the gate electrode, and the second storage node contact may be formed in contact with the already formed bit line. is formed in the trench and is located at a lower position than this polycrystalline silicon film, so there is no risk of short-circuiting with the bit line.

In addition, since the storage node contact and the bit line contact only need to be formed in contact with the polycrystalline silicon film that has been buried to a higher level than the gate electrode, there is no risk of short-circuiting with the gate electrode. . Furthermore, the etching time required for contact formation can be shortened.

Therefore, even when forming a contact with a high aspect ratio such as the bit line contact in this embodiment, it is possible to prevent the substrate from gouging due to overetching, resulting in a highly reliable memory cell. be able to.

In addition, it is possible to prevent short circuits between the bit line and the storage node electrode, and between the bit line and the storage node electrode and the gate electrode due to misalignment in photolithography technology, and it is possible to eliminate margins in the pattern that take misalignment into account. Therefore, it becomes possible to miniaturize memory cells.

Furthermore, by forming a capacitor on the bit line in this way, the bit line is covered with a plate electrode and shielded, which prevents malfunctions due to interference between adjacent bit lines even when cells are miniaturized. Occurrence can be prevented.

Note that in these examples, the storage node contact is formed after the bit formation, but the third
It is also possible to form the bit lines after forming the storage node contacts, as shown in examples in FIGS. 3(a) to 3(c).

Note that the reference numerals of each part correspond to those in the above embodiment.

In addition, although the above embodiment describes a DRAM having a stacked memory cell structure, this method is not limited to a DRAM having a stacked memory cell structure, and can include the step of forming a contact with a high aspect ratio. It is also an effective method for forming other devices including.

〔Effect of the invention〕

As described above, according to the conductive memory device of the present invention, after the first interlayer insulating film is formed on the gate electrode, the storage node contact and the bit line contact are formed in the region where the storage node contact and the bit line contact are formed. forming a first contact and burying a conductor in the first contact; a trench for burying either a storage node electrode or a bit line;
A second contact is formed in contact with the conductor in the corresponding six contacts, a storage node electrode or a bit line is buried in this groove, and the second contact is formed in the groove of the remaining one of the storage node contact or the bit line contact. Because the conductor is located above the storage node electrode or bit line that has already been buried, when the storage node contact or bit line contact is to be formed later, Since the storage node electrode or bit line is located below the height of the buried conductor layer, there is no risk of short-circuiting with these, making it possible to achieve miniaturization and improve reliability.

[Brief explanation of the drawing]

1(a) to 1(e) are diagrams showing a DRAM with a stacked memory cell structure according to an embodiment of the present invention, FIG. 2(a), and FIG. 2(A) to FIG. 2(e). , FIG. 2(C) is a manufacturing process diagram of a DRAM with the same stacked memory cell structure, and FIG. 3(a)
FIGS. 3(e) to 3(e) are diagrams showing DRAMs with a stacked memory cell structure according to other embodiments of the present invention, and FIGS. 4 and 5 are diagrams showing DRAMs with a stacked memory cell structure of conventional examples, respectively. be. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Element isolation insulating film, 3... Channel stopper, 4a, 4b... Source/drain region, 5... Gate insulating film, 6... Gate Electrode, 7... Insulating film, 8... Side wall insulating film, 9...
・Silicon oxide film, 10...Silicon nitride film, 11.
...Polycrystalline silicon film, 12...Silicon oxide film, 1
3... Interlayer insulating film, 14... First storage node contact, 1510. a first bit line contact;
]6... Polycrystalline silicon film, 17... Groove, 18...
・Insulating film, 1991. second storage node contact, 22... bit line, 23... tungsten layer,
24... Insulating film, 25... Second bit line contact, 26... Storage node electrode, 27... Capacitor insulating film, 28... Plate electrode, 101...
P-type silicon substrate, 102...element Tf min Jl absolute RIII, 103-104 a, 104 b -
... n-swelling diffusion layer, 105 ... gate insulating film, 106
...Gate electrode, 107...Insulating film, 108...
Storage node contact, 11o...Storage node electrode, 111...Capacitor insulating film, 112.
...Plate electrode. (b) (C) (0) (b) (C) Figure 2 (A) (B) 2 (d) (D) (b) Figure 3 (Part 1) 3 (C) Figure 3 (- i!-kari

Claims (2)

[Claims] (1) A MOSFET consisting of a source/drain region and a gate electrode formed on the surface of a substrate of one conductivity type, an interlayer insulating film of Node 1 covering the upper layer of the gate electrode, and the first interlayer insulating film. a first contact formed in a storage node contact and bit line contact forming area; a conductor layer buried in the first contact to a level higher than the gate electrode; a groove formed in the first interlayer insulating film at a position corresponding to one of the grooves; and a groove connected to the groove and the conductor layer in the corresponding contact among the first contacts. a second contact formed in the groove, and a capacitor comprising a storage node electrode, a capacitor insulating film, and a plate electrode embedded in the groove and the second contact so that the height thereof is lower than that of the conductor layer; a bit line, a second interlayer insulating film formed on this upper layer, and a second interlayer insulating film formed so as to contact the remaining one of the storage node contact and the bit line contact with the conductor layer. and the remaining one of a capacitor or a bit line formed of a storage node electrode, a capacitor insulating film, and a plate electrode formed to be connected to the third contact. A semiconductor memory device with a stacked capacitor structure. (2) An M consisting of a source/drain region and a gate electrode in an element isolation region formed on the surface of a substrate of one conductivity type.
a MOSFET formation step of forming an OSFET; a first interlayer insulating film forming step of forming a first interlayer insulating film on the gate electrode; and formation of a storage node contact and a bit line contact of the first interlayer insulating film. Part 1
a first contact formation step of forming a contact; a conductor layer embedding step of embedding a conductor layer in the first contact so as to be connected to the source/drain region; , a trench forming step of forming a trench for burying either the storage node electrode or the bit line; and forming a second contact that contacts the conductor layer in the corresponding contact among the first contacts. a second contact forming step; forming a capacitor or bit line including a storage node electrode, a capacitor insulating film, and a plate electrode so that the height thereof is lower than that of the conductor layer in the groove and the second contact; A capacitor or bit line forming step; A second interlayer insulating film forming step for forming a second interlayer insulating film formed on this upper layer; A storage node contact or a bit line contact for this second interlayer insulating film. a third contact forming step of forming a third contact that contacts the remaining one of the conductor layers; and a storage node electrode and a capacitor connected to the conductor layer exposed in the third contact. 1. A method of manufacturing a semiconductor memory device having a stacked capacitor structure, comprising a bit line or capacitor forming step of forming the remaining one of the capacitor or bit line consisting of an insulating film and a plate electrode.