JPS57106150A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57106150A
JPS57106150A JP18346280A JP18346280A JPS57106150A JP S57106150 A JPS57106150 A JP S57106150A JP 18346280 A JP18346280 A JP 18346280A JP 18346280 A JP18346280 A JP 18346280A JP S57106150 A JPS57106150 A JP S57106150A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
substrate
forming
crossover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18346280A
Other languages
Japanese (ja)
Inventor
Kazunari Shirai
Izumi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18346280A priority Critical patent/JPS57106150A/en
Publication of JPS57106150A publication Critical patent/JPS57106150A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a crossover or connection between two points on a substrate in a semiconductor device having semiconductor elements such as MOS or the like by performing the steps of forming a transistor. CONSTITUTION:A hole is opened at the field insulating layer on an Si substrate. Impurity ions are implanted thereon with a photoresist 7 as a mask to form a diffused layer 9. An SiO2 film 8 is formed by a gate oxidation. A polysilicon layer 2 is grown, and is etched to form an upper layer wire. When a diffused layer 3 is formed by source and drain diffusions, the layers 3 are conducted with the diffused layer 9 conducted previously, thereby forming a depletion type transistor structure with the layer 2 as a gate. Thus, a crossover structure can be formed.
JP18346280A 1980-12-24 1980-12-24 Manufacture of semiconductor device Pending JPS57106150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18346280A JPS57106150A (en) 1980-12-24 1980-12-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18346280A JPS57106150A (en) 1980-12-24 1980-12-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57106150A true JPS57106150A (en) 1982-07-01

Family

ID=16136195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18346280A Pending JPS57106150A (en) 1980-12-24 1980-12-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57106150A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006252A (en) * 1996-06-28 1998-03-30 김주용 Semiconductor device manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5460875A (en) * 1977-10-24 1979-05-16 Nec Corp Semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5460875A (en) * 1977-10-24 1979-05-16 Nec Corp Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006252A (en) * 1996-06-28 1998-03-30 김주용 Semiconductor device manufacturing method

Similar Documents

Publication Publication Date Title
US4074301A (en) Field inversion control for n-channel device integrated circuits
JPS6225452A (en) Manufacture of cmos transistor
JPS5736842A (en) Semiconductor integrated circuit device
JPS5660063A (en) Manufacture of semiconductor device
JPS5650535A (en) Manufacture of semiconductor device
JPS57106150A (en) Manufacture of semiconductor device
JPS5917865B2 (en) hand tai souchi no seizou houhou
JPS5583267A (en) Method of fabricating semiconductor device
JPS5768075A (en) Manufacture of integrated circuit device
JPS63128626A (en) Method of forming contact of semiconductor integrated circuit device
JPS5538019A (en) Manufacturing of semiconductor device
JPS55107229A (en) Method of manufacturing semiconductor device
JPS577153A (en) Preparation of semiconductor device
EP0002107A3 (en) Method of making a planar semiconductor device
JPS5739579A (en) Mos semiconductor device and manufacture thereof
JPS61131476A (en) Semiconductor device
JPS63160277A (en) Manufacture of semiconductor element
JPS561572A (en) Manufacture of semiconductor device
JPS62112376A (en) Semiconductor device
JPS5721855A (en) Manufacture of complementary mos semiconductor device
JPS5797674A (en) Manufacture of mos semiconductor device
JPS54104782A (en) Mos type semiconductor device
JPS56135971A (en) Manufacture of mos type semiconductor device
JPS5791521A (en) Manufacture of semiconductor device
JPS6465874A (en) Manufacture of semiconductor device