KR890004767B1 - Semiconductor memory device - Google Patents

Abstract

Memory cells are formed by islands in a P-type silicon layer(22) doped with boron and surrounded by holes in a field oxide film(23). Trenched capacitors(25a,25b) are formed at the EDSN of memory cells. A groove(26a) is formed which extends from the surface down into the P-type silicon layer. The first electrode(29) is poly-silicon and extends from the base of the groove to a level above that of the top of the groove, through a capacitor insulation film(30A). The first impurity-diffused semiconductor region(27A), which provides the second electrode of the capacitor, is surrounded by the boron-doped silicon layer(22). The capacitor insulation film(30A) forms the dielectric of the capacitor.

Description

Semiconductor memory

1 is a cross-sectional view showing a conventional dynamic MOS memory.

2 is a cross-sectional view of a dynamic MOS memory showing one embodiment of the present invention.

3 is a plan view of main parts of FIG.

4 is a cross-sectional view taken along line IV-IV of FIG.

5 (a), 5 (b), and 5 (c) are cross-sectional views showing the steps for forming the spherical capacitor of the present embodiment.

* Explanation of symbols for main parts of the drawings

1: P-type board 2: Goal

3: Capacitor Electrode 4: Capacitor Insulation Film

5: old capacitor 6: source area

7: drain region 8: gate oxide film

9, 9 ': gate electrode 10: transfer transistor

21 silicon substrate 22 well region

23: field oxide film 24a to 24c: active region (memory cell region)

25a ~ 25e: Older capacitors 26a ~ 26b: Goal

27a to 27b: P type diffusion region (impurity diffusion region of the second conductivity type)

28a to 28b: n-type diffusion region (impurity diffusion region of first conductivity type)

29a ~ 29b: Director

30: electrode made of first layer polycrystalline silicon

31a to 31b: silicon oxide film, (capacitor insulating film)

32: oxide film 33: boron-treated silicon oxide film

34: phosphorous silicon oxide film 35a to 35e: transfer transistor

36a to 36c: n ⁺ type source region 37a, 37b: n ⁺ type drain region

38a, 38b: gate oxide film

39a to 39e: gate electrode made of second layer polycrystalline silicon

40a, 40b: oxide film 41: interlayer insulating film

42, 42 ': Bit line 43a ~ 43c: Collector hole

44: protective insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an improved structure of a rectangular capacitor of a storage unit.

In semiconductor memory devices based on dynamic memory, the memory capacity has increased by four times in three years due to advances in microfabrication technology. The memory cell area is rapidly decreasing due to the increase in the capacity of the memory, but the value of the memory capacitor needs to be kept at a large value of several tens of fF due to the soft-error prevention and the S / N ratio for the sense amplifier detection. There is.

By the way, in order to make the capacitor value per unit area larger than before, the insulating film of the MOS structure which comprises a storage capacitor is thinned, or the insulating film material is changed from a silicon oxide film to a silicon nitride film.

However, since these memory capacitors form the MOS structure using the surface of the semiconductor substrate, it is limited in itself to obtain a large capacitor value as the cell area becomes smaller.

Recently, H, Sunami et al. Described the "Megabit Dynamic MOS Memory" in "International electric device meeting technical digest", December 1982, 806-808. In pleated capacitor cells (ccc) ", a MOS memory having a spherical capacitor of the structure shown in FIG. That is, 1 of FIG. 1 is a P-type silicon substrate, and the valley 2 is provided deep (for example, about 3-5 micrometers) from the surface of this board | substrate 1 inside. The capacitor electrode 3 made of the first layer polycrystalline silicon is provided in the valley 2 via the capacitor insulating film 4. This capacitor insulating film 4 is composed of a three-layer film of silicon oxide (SiO 2) / silicon nitride (Si 3 N 4) / silicon oxide (SiO 2). The spherical capacitor 5 is composed of the substrate 1, the valleys 2, the capacitor insulating film 4, and the capacitor electrode 3. On the surface of the silicon substrate 1 adjacent to the spherical capacitor 5, n + type source and drain regions 6 and 7 electrically separated from each other are provided. On a part of the substrate 1 slightly covering the source and drain regions 6 and 7, a gate electrode 9 made of a second layer polycrystalline silicon is provided via a gate oxide film 8. The transfer transistor 10 is constituted by the source, drain regions 6 and 7, the gate oxide film 8 and the gate electrode 9. The source region 9 is in contact with the insulating film 4 of the spherical capacitor 5, and the drain region 7 is connected to a bit line, which is not shown in the figure. 9 'in the figure is a gate electrode of an adjacent memory cell.

However, the MOS memory of FIG. 1 described above shortens the distance of the old capacitors between the memory cells due to the interference of information caused by the punchthrough phenomenon between one old capacitor and the other old capacitor as described in the literature. There was a point in that it was impossible to achieve a high density memory cell. That is, in general, the junction capacitance of the drain of the transfer transistor constituting the memory cell is required to be reduced in order to reduce the bit line capacitance. For this reason, although the density | concentration of a P-type silicon substrate needs to be reduced, the depletion layer will become wider and it will be easy to produce a phenomenon by punching in the board | substrate vicinity of the capacitor of a MOS structure. This punch draw phenomenon can be prevented by implanting impurity ions near the surface of a general silicon substrate. However, in the spherical capacitor 5 formed by forming the deep valleys 2 in the silicon substrate 1 as shown in FIG. 1, it is difficult to inject impurities into the deep portions of the silicon substrate 1, so that the adjacent portions are adjacent to each other. There was a significant drawback that a punch draw occurred at the bottom of the old capacitor, which could not be prevented. Therefore, in the conventional structure, it is necessary to keep the distance between the old capacitors between the memory cells far, and it is extremely difficult to realize a high density memory cell.

In addition, in the structure of FIG. 1, since the depletion layer is extended by the spherical capacitor 5 in the deep portion of the silicon substrate 1, the charges generated by the incidence of the α line are easily collected by the penneling phenomenon. There was a drawback of being soft against soft errors.

SUMMARY OF THE INVENTION In view of the above, the present invention provides a semiconductor memory device having an older capacitor having a larger capacitor value per unit area, a shorter distance between the older capacitors, and greater resistance to soft errors. There is an object of the invention.

The present invention provides a semiconductor layer of a first conductivity type, a well region of a second conductivity type selectively embedded in a surface layer of the semiconductor, a valley provided from the surface of the well region to the semiconductor layer, and the valley inner surface. A dopant diffusion region of the second conductivity type provided in the well region and the semiconductor layer of the diffusion region, and a first conductive type impurity having a smaller junction depth than that of the diffusion region provided in the impurity diffusion region on the inner surface of the bone; The electrode is formed by attaching a capacitor insulating film slightly over the opening, and has the structure of the electrode as the first capacitor electrode and the impurity diffusion region second capacitor electrode of the first conductivity type.

In the present invention having such a structure, the first conductive type impurity diffusion region prevents the phenomenon of punching between adjacent spherical capacitors, thereby enabling a high density memory cell, and furthermore, the second conductive type impurity diffusion region. Semiconductor memory having a structure in which a capacitor value per unit area is increased by the junction capacitance between the first conductivity type impurity diffusion region and the well region and the second conductivity type impurity diffusion region improve the tolerance of soft errors. You can get the device.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

FIG. 2 is a sectional view showing a part of the dynamic MOS memory, FIG. 3 is a plan view showing the main part of FIG. 2, and FIG. 4 is a sectional view taken along IV-IV of FIG. 21 is an n-type silicon substrate as a first conductive semiconductor layer containing 8 x 10 ¹⁴ / cm 3 phosphorous donor impurities. The surface layer of the silicon substrate 21 has, for example, a p-type well region having a depth of 2 μm containing 1 × 410 ¹⁶ / cm 3 acceptor impurities (boron, etc.) (well region: shaped like a well). (22) is selectively buried. In this well region 22, for example, a field oxide film 23 having a thickness of about 0.6 mu m is provided, and the well region 22 is separated into a field oxide film 23 as shown in FIG. A plurality of active regions (memory cell regions) 24a to 24c are sparsely formed. Spherical capacitors 25a to 25d are provided at a part of the active regions 24a and 24b and at both ends of the active region 24c. In addition, the spherical capacitors 25a and 25b are disposed adjacent to each other. The spherical capacitors 25a have depths 3 to 5 provided from the surface of the well region 22 to the silicon substrate 21 as shown in FIG. It is equipped with a valley 26a of 탆.

In the well region 22 and the silicon substrate 21 on the inner surface of the bone 26a, a P-type diffusion region 27a serving as a second conductivity type impurity diffusion region is formed. The P-type diffusion region 27a is 0.5 mu m deep and is higher than the concentration of the well region 22 described above, but has a concentration of about 2 x 10 ¹⁷ / cm 3. In the P-type diffusion region 27a in the valley 26a, an n-type diffusion region 28a serving as a first conductivity type impurity diffusion region shallower than the P-type diffusion region 27a is formed. This n-type expanded region 28a has a depth of 0.2 占 퐉 and a concentration of 1x10 ¹⁸ / cm 3, for example. The extension part 29a is formed in the side surface on the opposite side of the said spherical capacitor 25b of this n type diffused area 28a. In the valley 26a, the electrode 30 made of the first layer of polycrystalline silicon is slightly attached to the periphery of the opening of the valley 26a, for example, with a silicon oxide film 31a having a thickness of 200 mW as a capacitor insulating film. have. In this spherical capacitor 25a, the electrode 30 serves as a first capacitor electrode, and the n-type diffusion region 28a functions as a second capacitor electrode. In addition, the electrode 30 serves as a common electrode of each of the rectangular capacitors 25a to 25d. On the other hand, the spherical capacitor 25b is composed of a valley 26b, a P-type diffusion region 27b, an n-type diffusion region 28b, an electrode 30, and a silicon oxide film 31b. The spherical capacitors 25c and 25d are not shown in detail but have the same structure as the spherical capacitors 25a and 25d. In addition, a spherical capacitor 25e having the same structure is provided at the end portion of the P-type well region 22.

Here, the manufacturing method of a spherical capacitor is briefly demonstrated with reference to FIG. 5 (a), FIG. 5 (b), and FIG. 5 (c). First, the P type well region 22 is selectively formed on the surface layer of the n-type silicon substrate 21, and then the field oxide film 23 is formed on the surface of the well region 22 to form the active regions 24a, 24b, and 24c. (Not shown), then the active regions 24a and 24b (24c are not shown), and then an oxide film 31 having a thickness of 1000 Å is formed on the surface of the active regions 24a and 24b. do.

Then, a photo resist is applied and the well region 22 is formed by reactive ion etching using a resist pattern as a mask on the bone formation portion of the oxide film 32 by photolithography. On the surface, the silicon substrate 21 is selectively etched to form valleys 26a and 26b having a depth of 3 to 5 mu m (FIG. 5). Thereafter, the resist pattern is peeled off.

Subsequently, the oxide film 32 corresponding to a part of the source region of the transfer transistor is selectively removed by a photolithography method, and then a silicon oxide film (or a polycrystalline silicon film) subjected to a P-type impurity, for example, boron, on the front surface 33 ) Is deposited by a CVD method, and the boron-treated silicon oxide film 33 is used as a diffusion source, and boron is formed into the P-type well region 22 and n-type silicon substrate 21 on the inner surface of the bones 26a and 26b. Thermal diffusion to form the P-type diffusion regions 27a and 27b. (FIG. 5 (b)) Subsequently, the boron-treated silicon oxide film 33 is removed, and a silicon oxide film (or an arsenic-treated silicon oxide film, phosphorus or arsenic-treated polycrystalline silicon film) treated with phosphorus on the entire surface ( 34 was deposited by CVD, and then the phosphorus was thermally diffused into the P-type diffusion regions 27a and 27b using the phosphorus-treated silicon oxide film 34 as a diffusion source to form P-type diffusion regions 27a and 27b. N-type diffusion regions 28a and 28b and extension portions 29a and 29b are formed respectively (figure 5 (c)). Thereafter, although not shown, the phosphorus-treated silicon oxide film is removed, the oxide film is also removed, and the thermal oxidation process is further performed to form a silicon oxide film on the exposed well region and the substrate surface including the bone inner surface, and then on the front surface. A first layer polycrystalline silicon film is deposited and patterned to form electrodes over the periphery of the opening in the bone, and the silicon oxide film is selectively etched using this electrode as a mask to form a silicon oxide film for a capacitor.

In addition, transfer transistors 35a to 35e are formed in each of the active regions 24a to 24c adjacent to the rectangular capacitors 25a to 25d. The transfer transistor 35a is an n + type source and drain region containing, for example, 10 ²⁰ / cm 3 acceptor impurities, which are electrically separated from each other on the surface of the active region 24a adjacent to the spherical capacitor 25a. An electrode 39a made of a second layer polycrystalline silicon provided through a gate oxide film 38a at a portion of the active region 24a including a portion between the portions 36a and 37a and the source and drain regions 36a and 37a. It consists of. The n + type source region 36a is connected to the extension portion 29a of the n type diffusion region 28a constituting the spherical capacitor 25a. On the other hand, the transfer transistor 35b is composed of an n + type source, drain regions 36b and 37b, a gate oxide film 38b and a gate electrode 39b, and the source region 36b is formed of the spherical capacitor 25b. Is connected to the extending portion 29b of the n-type diffusion region 28b. The transfer transistors 35c and 35d are composed of a source, a drain region, a gate oxide film (all of which are not shown), and gate electrodes 39c and 39d, like the transfer transistors 35a and 35b described above. . A transfer transistor 35e is formed in one portion of the well region 22, and the transfer transistor 35e includes an n + type source region 36e and an n + type drain region (the transfer transistor 35b). A gate electrode 39e provided through a gate oxide film 38e on a portion of the well region 22 which includes a portion of the drain region 37b) and a portion between the source and train regions 36e and 36b. . Gate electrodes 39a and 39b of the transfer transistors 35a and 35b cross the electrodes 30 of the spherical capacitors 25c and 25d via an oxide film (not shown), and also the transfer transistors. The gate electrodes 39c and 39d of (35c) and 35d cross the electrodes 30 of the spherical capacitors 25a and 25b via the oxide films 40a and 40b.

In addition, an interlayer insulating film 41 is coated on the well region 22 and the silicon substrate 21 including the respective rectangular capacitors 25a to 25e and the transfer transistors 35a to 35e. Above 41, bit lines 42 and 42 'made of aluminum are provided in a direction crossing the gate electrodes 39a to 39e. One bit line 42 is connected to the drain region 37a of the transfer transistor 35a and the common drain region 37b of the transfer transistor 35b and 35e via contact holes 43a and 43b, respectively. It is. The other bit line 42 'is connected to a common drain region (not shown) of the transfer transistors 35c and 35d via a contact hole. A protective insulating film 44 is coated on the interlayer insulating film 41 including these bit lines 42 and 42 ′.

Therefore, according to the semiconductor memory device of the present invention, about 2 x 10 ¹⁷ / cm 3 outside the n-type diffusion regions 28a and 28b constituting each gear node of the spherical capacitor (for example, 25a 25b). Since the P-type diffusion regions 27a and 27b having impurity concentrations are formed, the depletion of the depletion layer to the P-type well region 22 around the tops of the spherical capacitors 25a and 25b is used to expand the P-type diffusion regions 27a. It is possible to reliably suppress the presence of) 27b. In fact, the depletion layer extending between the P-type diffusion regions 27a and 27b and the n-type diffusion regions 28a and 28b when the potential of the memory node is 5 V relative to the P-type well region 22 is about 0.2 탆. to be. As a result, even if the distance A between the spherical capacitors 25a and 25b is close to 0.6 [mu] m where the P-type diffusion regions 27a and 27b overlap, the punch-through phenomenon between them can be prevented. In the structure of the spherical capacitor 5 shown in FIG. 1, when the distance between the spherical capacitors is about 2 mu m, the phenomenon has already been punched. This is a three times improvement in distance. Moreover, in the present invention, the contact capacity of the bit line does not increase at all. Therefore, the high density memory cell can be realized by preventing the phenomenon caused by the punching between the spherical capacitors.

Further, the valleys 26a to 26e constituting the spherical capacitors 25a to 25e can be deeper than the length of the well region 22 on the surface of the well region 22 (26c to 26e are not shown in the figure). . Furthermore, for example, in the spherical capacitor 25a, the p-type junction capacitance between the P-type diffusion region 27a and the n-type diffusion region 28a is the n-type diffusion region 28a in which the silicon oxide film 31a is mediated. Since it overlaps with the capacitance between the electrode and the electrode 30, the spherical capacitor 25a having a high capacitor value per unit area can be realized, and further, the memory cell can be made higher in density. In fact, it can be seen that the capacitance value of the pn junction capacitance using the silicon oxide film 31a of 200 으로서 as the capacitor insulating film is about 30%.

In addition, since the P-type well region 22 is provided on the surface of the n-type silicon substrate 21, and the outermost P-type diffusion region 27a of the spherical capacitor 25a is provided, those P-type wells Since the region 22 and the P-type diffusion region 27a form a potential barrier around the storage node with respect to the capacitor generated according to the locus of the? Particles, a semiconductor memory device excellent in resistance to soft errors can be realized.

In addition, although the silicon oxide film was used as an insulating film for capacitors in the said Example, it is not limited to this. For example, a silicon oxide film may be a composite film in which a silicon nitride film is sandwiched, a silicon nitride film, or a two-layer film of silicon oxide film and tantalum oxide.

In the above embodiment, an n-type silicon substrate is used as the semiconductor layer, but a P-type silicon substrate may be used. In this case, the impurity diffusion region of the second conductivity type is n-type, the impurity diffusion region of the first conductivity type is p-type, and is composed of a transfer transistor P-channel MOS transistor.

In the above embodiment, the dynamic MOS memory has been described as an example, but the same can be applied to the static MOS memory. In this case, for example, the above-described spherical capacitor may be provided in the top positive node of the flip-flop type cell.

As described above, the present invention has a spherical capacitor having a large capacitor value per unit area, and also allows the density of the memory cell to be increased by significantly shortening the distance of the spherical capacitor in a range where no phenomenon occurs. It is possible to improve the resistance to the semiconductor device, and furthermore, to achieve a high density, high reliability semiconductor memory device.

Claims (4)

In a semiconductor memory device having a spherical capacitor, the semiconductor layer 21 of the first conductivity type and the surface of the well region 22 selectively embedded in the surface layer of the semiconductor layer 21 as the second conductivity type are described above. Diffusion of the second conductivity type impurity formed in the valleys 26a and 26b formed over the middle of the semiconductor layer 21, the well region 22 in the inner surface of the valleys 26a and 26b and the semiconductor layer 21. The first conductivity type impurity diffusion regions 28a and 28b having a shallower junction depth than the second conductivity type impurity diffusion regions 27a and 27b on the inner surfaces of the regions 27a and 27b and the valleys 26a and 26b, An electrode 30 provided from the inner surfaces of the valleys 26a and 26b to at least the periphery of the opening via the capacitor insulating films 31a and 31b, and the electrode 30 as the first capacitor electrode. Using the first conductivity type impurity diffusion regions 28a and 28b as the second capacitor electrode. A semiconductor memory device characterized in that it is used. The concentration of the semiconductor layer 21, the well region 22, the impurity diffusion regions 27a and 27b of the second conductivity type, the impurity diffusion regions 28a and 28b of the first conductivity type, and the like, respectively. If expressed as n1, n2, n3 and n4, their concentration relation is n1 <n2

and n3 &lt; n4. 2. The semiconductor memory device according to claim 1, wherein the impurity diffusion regions (27a, 27b, 28a, 28b) of the second capacitor and the first conductivity type of the spherical capacitor are formed by a double diffusion method. 2. The source and drain regions 36a, 37a, 36b, and 37b of the first conductivity type, which are provided on the surface of the well region 22 of the second conductivity type, and are electrically separated from each other. The transfer transistors 35a and 35b constituted by the electrodes 39a and 39b provided in the well region 22 including the regions 36a, 37a, 36b and 37b via the gate insulating films 38a and 38b. And one side of the source region and the drain region 36a, 37a, 36b, 37b is connected to the first conductivity type impurity diffusion regions 28a, 28b of the spherical capacitor, and the other is connected to the bit line 42. Semiconductor memory device characterized in that the connection

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