JPS60152059A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten a distance between groove-shaped capacitors remarkably by forming a first conduction type impurity diffusion region having junction depth shallower than a second conduction type impurity diffusion region shaped in an impurity diffusion region in the inner surface of a groove section formed while reaching in a semiconductor layer from the surface of a well region. CONSTITUTION:A P type well region 22 is buried selectively to the surface layer of a semiconductor substrate 21. A groove-shaped capacitor 25a has a groove section 26a shaped while reaching into the substrate 21 from the surface of the region 22. A P type diffusion region 27a is formed to the region 22 in the inner surface of the groove section 26a and the substrate 21. An N type diffusion region 28a shallower than the region 27a is formed in the region 27a. An electrode 30 is shaped extending over the periphery of an opening section for the groove section 26a through an insulating film 31a for the capacitor. The electrode 30 and the region 28a function as first and second capacitor electrodes. Accordingly, a distance between groove-shaped capacitors is shortened remarkably without generating a punch-through phenomenon, and the density of a memory cell can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the structure of a trench-type capacitor as a memory portion is improved.

[Technical background of the invention and its problems]

Semiconductor storage devices, including dynamic memory,
Its storage capacity is f! With the advancement of llB processing technology, approximately 3
It is increasing at a rate of four times per year. The memory cell area continues to be rapidly reduced as storage capacity increases, but the storage capacitor value of the memory cell is being adjusted to prevent soft errors and to ensure the S/N ratio for sensing by the sense amplifier. Therefore, it is necessary to maintain a large value of several tens of fF.

Incidentally, conventionally, in order to increase the capacitor value per unit area, the insulating film of the MO3 structure constituting the storage capacitor has been made thinner, or the insulating film material has been changed from silicon oxide film to silicon nitride film. however,
Since these storage capacitors form a MOS structure using the surface of a semiconductor substrate, there is a natural limit to obtaining a large capacitor value as the cell area becomes smaller.

For this reason, recently, H. Sunami et al.
A Corrugated Capacitor Ce
1l (CCC) for Meaabit Dynami
c MOS MemoryS″, (internati
nal l:1etric [)evices Me
ettng Technical o+pest 5g
1l performance number 26°9, DO1806-808 DeC1
In 1982, he announced a MOS memory having a trench capacitor with the structure shown in FIG. That is, reference numeral 1 in FIG. 1 is, for example, a p-type silicon substrate, and a deep groove 2 (for example, about 3 to 5 μm) is provided inside the substrate 1 from its surface. A capacitor electrode 3 made of a first layer of polycrystalline silicon is provided from within the trench 2 to the periphery of the opening with a capacitor insulating film 4 interposed therebetween. This capacitor insulation N
@4 is 5i02/5j3N.

/810. It consists of a three-layer film. Such a substrate 1, groove part 2
, the capacitor insulating film 4 and the capacitor electrode 3 constitute a trench capacitor 5-. Further, n+ type source and drain regions 6.7 electrically isolated from each other are provided on the surface of the silicon substrate 1 adjacent to the trench capacitor 5-. A gate electrode 9 made of a second layer of polycrystalline silicon is provided on a portion of the substrate 1 including at least between the source and drain regions 6 and 7 with a gate oxide film 8 interposed therebetween. The source and drain regions 6.7, gate oxide film 8, and gate electrode 9 constitute a transfer transistor 10. Furthermore, the source region 6 is in contact with the insulating film 4 of the trench capacitor 5-, and the train region 7 is connected to a bit line (not shown). Note that 9' in the figure is the gate electrode of an adjacent memory cell.

However, as described in the literature, the MOS memory shown in FIG. The disadvantage is that the distance between the trench capacitors between cells cannot be shortened, and high-density memory cells cannot be realized. That is, in general, the junction capacitance of the drain of a transfer transistor constituting a memory cell is required to be reduced in order to reduce the bit line capacitance. For this reason, it is necessary to lower the concentration of the p-type silicon substrate, but this spreads a depletion layer in the substrate near the capacitor of the MOS structure, making it easier to cause a punch-through phenomenon.

Such punch-through phenomenon can generally be prevented by implanting impurity ions from near the surface of the silicon substrate. However, in the trench type capacitor L which is made by forming a trench 2 in a silicon substrate 1 as shown in FIG. 1, it is difficult to implant impurity ions deep into the silicon substrate 1. There is a serious drawback in that a punch-through phenomenon occurs near the bottom of the groove-type capacitor, and it cannot be prevented.

Therefore, in the conventional structure, it is necessary to leave a long distance between the trench capacitors between memory cells, making it extremely difficult to realize a high density memory cell.

In addition, in the structure shown in FIG. 1, a depletion layer is extended by the trench capacitor 5- deep in the silicon substrate 1, and the charge generated by the incidence of α rays is likely to be collected by the funneling phenomenon. It had the disadvantage of being weak.

(Objective of the Invention) It is an object of the present invention to provide a semiconductor memory device that includes trench capacitors with a large capacitor value per unit area, can significantly shorten the distance between the trench capacitors, and has excellent soft error resistance. That is.

[Summary of the invention]

The present invention includes a semiconductor layer of a first conductivity type, a well region of a second conductivity type selectively buried in a surface layer of the semiconductor layer,
A trench provided reaching from the surface of the well region into the semiconductor layer, an impurity diffusion region of the second conductivity type provided in the well region and the semiconductor layer on the inner surface of the trench, and an impurity diffusion region provided on the inner surface of the trench. an impurity diffusion region of a first conductivity type having a junction depth shallower than that of the diffusion region; and an electrode provided from within the groove portion to at least the periphery of the opening via a capacitor insulating film; The present invention is characterized by comprising a trench type capacitor having a structure in which the impurity diffusion region of the first conductivity type is used as a first capacitor electrode and the impurity diffusion region of the first conductivity type is used as a second capacitor electrode. In such a structure, the impurity diffusion region of the first conductivity type prevents the punch-through phenomenon between adjacent trench capacitors and enables high-density memory cells, and the impurity diffusion region of the second conductivity type and the first A semiconductor memory device having a structure in which the capacitor value per unit area is increased by the junction capacitance between the conductivity type impurity diffusion region, and the soft error resistance is further improved by the well region and the 2'4 conductivity type impurity diffusion region. can be obtained.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

2 is a sectional view showing a part of the dynamic MOS memory, FIG. 3 is a plan view showing the main part of FIG. 2, and FIG. 4 is a sectional view taken along IV-IV in FIG. 3. 21 in the diagram is the first
The substrate is an n-type silicon substrate containing a donor impurity such as phosphorus at 8×10 2 /cm 3 as a conductive type semiconductor layer. The surface layer of this silicon substrate 21 has, for example, 1xio
A p-type well region 22 containing acceptor impurities (such as boron) of /cm3 and having a depth of 2 μm is selectively buried.

This well region 22 is provided with a field oxide film 23 having a thickness of, for example, about 0.6 μm.
2 includes a plurality of island-shaped active regions (memory cell regions) 248 separated by the field oxide film 23 as shown in FIG.
~24c is formed. These active regions 24a, 2
Groove capacitors 25a to 25d are provided at a portion of the active region 4b and at both ends of the active region 24c, respectively, and the trench capacitors 25a and 25b are arranged adjacent to each other. As shown in FIG. 4, the trench type capacitor 11L includes a trench 26a extending from the surface of the well region 22 into the silicon substrate 21 and having a depth of, for example, 3 to 5 μm. An n-type diffusion region 27a serving as a second conductivity type impurity diffusion region is formed in the well region 22 and the silicon substrate 21 on the inner surface of the groove portion 26a. This n-type diffusion region 27a has a depth of, for example, 0.5 μm, and a concentration higher than that of the well region 22, for example, 2×10 2 /cm 3 . Further, an n-type diffusion region 28a as a first conductivity type impurity diffusion region shallower than the n-type diffusion region 27a is formed in the n-type diffusion region 27a on the inner surface of the groove portion 26a. This n-type diffusion region 28a has a depth of 0.2 μm.
The density is, for example, 1×10″/an 3. The trench type capacitor 1 in this n-type diffusion region 28a
An extending portion 29a is formed on the side surface opposite to 1. An electrode 3 made of a first layer of polycrystalline silicon extends from inside the groove 26a to at least around the opening of the groove 26a.
.degree. is provided through a silicon oxide film 31a having a thickness of, for example, 200 mm as a capacitor insulating film. In such a trench capacitor 25a, the electrode 30 is the first
The n-type diffusion region 28a functions as a second capacitor electrode. Note that the electrode 30 serves as a common electrode for each of the trench capacitors L1L to 25d. On the other hand, the groove-type capacitor 25b has a groove portion 26b,
It is composed of an n-type diffusion region 27b, an n-type diffusion region 28b, an electrode 3o, and a silicon oxide film 31b.

Although the trench type capacitor 25C125d is not shown in detail, it has a similar structure to the trench capacitor 25a125b. Note that a trench capacitor 1 having a similar structure is also provided at the end of the p-type well region 22.

Here, Fig. 5(a) shows a method for manufacturing a trench type capacitor.
This will be briefly explained with reference to C). First, after selectively forming a p-type well region 22 on the surface layer of an n-type silicon substrate 21, field oxidation I
II 23 and an island-shaped active region 24a,
24b (24c is not shown), an oxide film 31 with a thickness of approximately 1,000 yen is formed on the surfaces of the active regions 24a and 24b.
form. Subsequently, a photoresist is applied and a resist pattern (not shown) is formed on the groove portion of the oxide film 32 by photolithography, and then the surface of the well region 22 is etched by reactive ion etching using the resist pattern as a mask. It reaches into the silicon substrate 21 and is selectively etched to form grooves 26a, 2 with a depth of 3 to 5 μm, for example.
6b (as shown in FIG. 5(a)). After that, the resist pattern was peeled off.

Next, after selectively removing the oxide film 32 corresponding to part of the source region of the transfer transistor 1 to the transistor by photolithography, a silicon oxide film doped with p-type impurity (as shown) is formed on the entire surface. (or polycrystalline silicon film) 33
The boron-doped silicon oxide film 33 is deposited by the VD method, and boron is thermally diffused into the p-type well regions 22 and the n-type silicon substrate 21 on the inner surfaces of the grooves 26a and 26b to form n-type diffusion regions 27a, 27b (as shown in FIG. 5(b)). Subsequently, the boron-doped silicon oxide film 33 is removed, and a phosphorus-doped silicon oxide film (or an arsenic-doped silicon oxide film, or a polycrystalline silicon film doped with arsenic) 34 is deposited on the entire surface by the CVD method. Using the phosphorus-doped silicon oxide film 34 as a diffusion source, phosphorus is thermally diffused into the p-type diffusion regions 27a and 27b to form n-type diffusion regions 28 in the same diffusion regions 27a and 27b, respectively.
a, 28b and extending portions 29a, 29b (fifth
Figure (C) (Illustrated). After this, although not shown, the phosphorus-doped silicon oxide film is removed, the oxide film is also removed, and thermal oxidation treatment is performed again to form a silicon oxide film on the exposed well region including the inner surface of the trench and on the substrate surface. Subsequently, a first layer polycrystalline silicon film is deposited on the entire surface, and this is patterned to form an electrode from inside the trench to at least around the opening, and using this electrode as a mask, the silicon oxide film is selectively deposited. Etching is performed to form a silicon oxide film for a capacitor.

Furthermore, a transfer transistor 358 is provided in each active region 24a to 24G adjacent to each trench type capacitor 25a to 25d.
~35d is formed. The transfer transistor 35a is located in the active region 24' adjacent to the trench capacitor 25L.
For example, 1
A second layer is provided via a gate oxide film 38a over the n+ type source and drain regions 36a and 37a containing adapter impurities of 0.020 cm3 and the active region 24a portion including at least the area between these source and drain regions 36a and 37c. Gate electrode QQp, L- made of layered polycrystalline silicon
σUpper i Kashiwa Tisu Bend n”ff1-North area 3
6a is connected to an extension 29a of the n-type diffusion region 28a constituting the trench capacitor 25a. On the other hand, the transfer transistor i includes n+ type source and drain regions 36b and 37b, a gate oxide film 38b, and a gate electrode 3.
9b, and the source area hil'36
b is connected to an extension 29b of the n-type diffusion region 28b constituting the trench capacitor 25b. Further, the transfer transistors 35c and LL are made up of a source, a train region, a gate oxide film (none of which are shown), and electrodes 390 and 396, similar to the transfer transistors 35a1 and 12-. . Note that a transfer transistor 35e is formed at the end of the well region 22, and the transfer transistor 35e has an n+ type source region 36e and an n type drain region (the drain region of the transfer transistor 35). 37b), and an electrode 39e provided on the well region 22 via a gate oxide film 38e on a portion of the well region 22 including at least between these source and drain regions 36e and 37b.

Gate electrode 39 of the transfer transistors 35a, 35 and beyond
a and 39b cross over the electrode 30 of the trench type capacitor 25C125d via an oxide film (not shown), and connect to the electrode 39c of the transfer transistor 35G and 35d.
139d is the electrode 3 of the trench type capacitors 25a and 25b.
It crosses over the oxide films 40a and 40b.

Furthermore, a well region 22 including the trench capacitors 25a to 25e and the transfer transistors 35a to 35e.
An interlayer insulating film 41 is coated on the silicon substrate 21, and on the interlayer insulating film 41, pins 1 to 42 and 42' made of Afl are connected to each of the gate electrodes 39a to 39.
It is provided in a direction perpendicular to e. One bit line 4
2 is the above-mentioned transfer] Drain region 3 of transistor 35a
7a, and are connected to a common train region 37b of transfer transistors 35b and 35e via contact holes 43a and 43b, respectively. The other pin 1-line 42' is connected to a common drain region (not shown) located 1LS1L ahead of the transfer transistor via a contact hole 43c. These beep! A protective insulating film 44 is coated on the interlayer insulation 11941 including the lines 42, 42-.

According to the semiconductor memory device of the present invention, approximately 2
Since the p-type diffusion regions 2'7a and 27b having an impurity concentration of This can be significantly suppressed by the presence of regions 27a and 27b. In fact, the potential of the storage node is p
When the potential difference was 5V with respect to the type well region 22, the width of the depletion layer extending between the b-type diffusion regions 27a, 27b and the n-type diffusion regions 28a, 28b was about 0.2 μm.

As a result, the distance (A
Even if the n-type diffusion regions 27a and 27b overlap with each other by 0.6 μm, the punch-through phenomenon between them can be prevented.

In the structure of the groove capacitor i shown in FIG. 1, the punch-through phenomenon already occurred when the distance between the groove capacitors was about 2 μm. This is an improvement of more than three times in terms of distance. Moreover, in the present invention, the junction capacitance of the bit line does not increase at all.

Therefore, by preventing the punch-through phenomenon between trench capacitors, high-density memory cells can be realized.

Further, the groove portions 2 constituting the groove capacitors 25a to 25e are
6a to 26e can be made deeper than the depth of the well region 22 from the surface of the well region 22 without any restriction. Moreover, in the trench type capacitor insulating film, for example, the n-type diffusion region 27a
The pn junction capacitance between the n-type diffusion region 28a and the n-type diffusion region 28a with the silicon oxide film 31a interposed between the n-type diffusion region 28a and the electrode 30
Since the capacitance is superimposed on the capacitance between the trench capacitor 25a and the trench capacitor 25a, which has a high capacitance value per unit area, it is possible to realize a high density memory cell. In fact, it has been found that the pn junction capacitance reaches approximately 30% of the capacitance value when the 200A silicon oxide film 31a is used as the capacitor insulating film.

Furthermore, a p-type well region 2 is formed on the surface of the n-type silicon substrate 21.
2 and an n-type diffusion region 27a in the outermost layer of the trench capacitor 25a, the p-type well region 22 and the pW diffusion region 27a are generated along the trajectory of the Since a potential barrier is formed around the storage node against the carriers, a semiconductor memory device with excellent soft error resistance can be realized.

In the above embodiment, a silicon oxide film is used as the capacitor insulating film, but the present invention is not limited to this. For example, a composite film in which a silicon nitride film is sandwiched between silicon oxide films, a silicon nitride film, or a two-layer film of silicon oxide and tantalum oxide may be used.

In the above embodiment, an n-type silicon substrate was used as the semiconductor layer, but an n-type silicon substrate may also be used. in this case,
The second conductivity type impurity diffusion region is n type, the first conductivity type impurity diffusion region is p type, and the transfer transistor is a p channel Mos transistor.

Although the above embodiment has been explained using a dynamic MOS memory as an example, it can be similarly applied to a static MOS memory. In this case, for example, the trench type capacitor described above may be provided at the bistable node of a flip-flop type cell.

〔Effect of the invention〕

As described in detail above, according to the present invention, a trench capacitor having a large capacitor value per unit area is provided, and the distance between the trench capacitors is significantly shortened without causing a punch-through phenomenon, thereby achieving high density memory cells. In addition, it is possible to improve the error resistance and provide a high-density, highly reliable semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional dynamic MOS memory, and FIG. 2 is a sectional view showing a dynamic MOS memory according to an embodiment of the present invention.
A sectional view of the OS memory, FIG. 3 is a plan view of the main part of FIG. 2,
Figure 4 is a sectional view taken along line IV-IV in Figure 3;
Figures (a) to (C) are cross-sectional views showing steps for forming the trench type capacitor of this example. 21... N-type silicon substrate, 22... P-type well region, 23... Field oxide film, 24a to 24c.
... Active region (memory cell), 25a-25e... Trench capacitor, 26a-26e... Groove portion, 27a-2
7e...n-type diffusion region (second conductivity type impurity diffusion region), 28a-28e...n-type diffusion region (first s-type impurity diffusion region), 29a-29e...extension portion, 30
...Electrodes made of first layer polycrystalline silicon, 31a to 3
1e...Silicon oxide group (insulating film for capacitors), 3
3... Boron-doped silicon oxide film, 34... Phosphorus-doped silicon oxide film, 358-35e... Transfer transistor, 36a-36c... n++ source region, 3
7a, 37b...n+ type drain regions 39a to 39
e...Gate electrode made of second layer polycrystalline silicon, 4
2.42'...Bit line. Applicant's agent Patent attorney Takehiko Suzue 7'5117I Figure 2

Claims (4)

[Claims] (1) A semiconductor layer of a first conductivity type, a well region of a second conductivity type selectively buried in the surface layer of the semiconductor layer, and a trench provided extending from the surface of the well region into the semiconductor layer. , a 213th type impurity diffusion region provided in the well region and the semiconductor layer on the inner surface of the trench, and a first conductive layer having a junction depth shallower than that of the diffusion region provided in the impurity diffusion region on the inner surface of the trench. an impurity diffusion region of a mold type, and an electrode provided from inside the groove to at least around the opening via an insulating film for a capacitor, the electrode being a first capacitor electrode, and the first electrode being a first capacitor electrode. 1. A semiconductor memory device comprising a trench type capacitor having a structure in which a conductive type impurity diffusion region is used as a second capacitor electrode. (2) The concentration of the semiconductor layer, the well region, the second conductivity type impurity diffusion region, and the first s conductivity type impurity diffusion region is set to n
2. The semiconductor memory device according to claim 1, wherein when l, n2, n3, and n4, their concentration relationship is nl<n2≦j13<n4. (3) The semiconductor memory device according to claim 1, wherein the second conductivity type and first conductivity type impurity diffusion regions of the trench capacitor are formed by a double diffusion method. (4) Source and drain regions of the first conductivity type provided electrically isolated from each other on the surface of the well region of the second conductivity type, and gate insulation on the well region portion including at least between these source and train regions. a transfer transistor including a gate electrode provided through a film, one of the source and drain regions being connected to a first conductivity type impurity diffusion region of the trench capacitor, and the other being connected to a bit line. A semiconductor memory device according to claim 1, characterized in that: