JPS6273761A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the density of a semiconductor memory by constructing to dispose the hole of a groove type capacitor of one memory cell only directly under the gate wiring of a transfer of other memory cell to reduce the occupying area of the cell while sufficiently increasing the capacity of an MOS capacitor. CONSTITUTION:A semiconductor memory is so constructed that the position of a hole 102 formed in a substrate 101 of a cell capacitor is disposed directly under the gate wiring 104 of a transfer transistor of other memory cell passing on a cell plate electrode 103 which forms an upper electrode. In other words, the irregular surface of the substrate 101 formed with the hole 102 is also used to bury the hole with the electrode 103 and the wiring 104 of the transfer transistor of other memory cell passing on the electrode 103. The increase of the capacitance by the groove 102 formed in this manner becomes approx. 50-70% when the ratio of the area of the hole of the groove 102 to that of the cell capacitor is approx. 20-30% and the depth of the groove 102 is set to become 1.0-1.5mum.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to an F-79 type memory device in which a memory cell is constructed by combining one transistor and one capacitor f, and particularly relates to an F-79 type memory device that includes a capacitive filtration element. The present invention relates to a semi-i4'+ body drilling device formed in a groove drilled in the surface of a semiconductor substrate.

[Technical front of the invention and its problems]

Generally, dynamic RAM (hereinafter referred to as AM in D1)
A memory cell has M for storing charge and retaining information.
It is composed of an OS capacitor and a switch transistor (transfer 1 to transistor) for transferring the charge to and from an external circuit.

FIG. 3 is a cross-sectional view of a device showing the structure of a multi-layer used in such a conventional semiconductor processing device. This memory cell has a first phase silicon gate electrode 13 disposed on a semiconductor substrate 11 via a gate insulating film 12 as an upper electrode, and an impurity layer 1 having a conductivity type opposite to that of the semiconductor substrate 11.
The second phase polysilicon gate electrode 16 disposed through the insulating film 15 is used as the gate electrode, and the M plate 11 and the opposite conductivity type high leakage electrode are used as the gate electrode. It is composed of an MO8I transistor with impurity diffusion region 17 as a drain region and impurity layer 14 as a source.

Note that the memory cells are electrically isolated from each other by a thick insulating film 18 for element isolation. The hanging charge accumulated in the MOS resistor in the memory cell is
It is determined by the thickness J3 of the gate insulating film 12 forming the capacitor and its area.

Also, the size of the signal read when no information is read is
It is determined by the magnitude of the accumulated charge. Therefore, in order to increase the amount of accumulated charge, it is necessary to reduce the thickness of the gate insulating film 12 and increase its area.

When a planar MOS I-transistor as shown in FIG. 3 is used, there is a natural limit to the thickness and area of the insulating film 12, which hinders high-density electrification.

Twelve improved structure of the main element to solve such problems are proposed in, for example, Japanese Patent Laid-Open No. 52-148385 and Japanese Patent Laid-Open No. 52-149989.

The MOS capacitors disclosed in these documents are called trend capacitors, and are made by forming a hole on the surface of a semiconductor substrate and oxidizing the inner surface of the hole to form a h''4G capacitor used as a trend capacitor.

FIG. 4 shows a plan view of a conventional so-called groove-type key, and FIG. 5 shows a sectional view thereof.

A hole 202 is formed in the substrate 201 of the cell capacitor, an oxide film 206 is formed on the inner wall surface of the hole 202, and a cell plate 203 is formed of polysilicon or the like on the surface of the hole 202. This cell plate 1-203 is used as the upper electrode, and the substrate A groove-type transistor I7 is constructed using the impurity-enhanced rl1 layer 207 diffused on the surface of the resistor 201 as a lower electrode.

Due to the formation of the hole 202, large irregularities are formed on the surface of the semiconductor substrate 201, and due to the step caused by the cell plate 203 and the gate wiring 204 of the transfer transistor of another memory cell passing over it, This makes it easy for the bit line 205 to break.

FIG. 6 shows a cross-sectional view of a conventional trench type capacitor in which trenches are buried. A filler material 208 such as polysilicon is formed in the hole 202 to fill the hole 202 . However, several additional steps such as oxidation diffusion and etching are required to perform such embedding, which has the disadvantage of increasing the cost of the device.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and is based on the MOS kit. By making the capacity of the base sufficiently large, reducing the area occupied by the memory hill, enabling higher density, and facilitating the JJ manufacturing process, it is possible to achieve high yields and reduce turnaround time. The first goal is to capture the head of semiconductors.

[Summary of the invention]

The semiconductor memory device of the present invention has an IS characteristic in that it is configured such that one memory vortex occupies only one position immediately below the gate wiring of the transfer transistor of another memory cell. .

[Embodiments of the invention]

FIGS. 1 and 2 show a cross-sectional view and a plan view of a semiconductor memory device according to an embodiment of the present invention.

The cross-sectional view shown in FIG. 1 is a cross-sectional view of a portion cut along the line BB' in FIG. 2.

The hole 102 formed in the substrate 101 of the cell capacitor is located at the cell plate electrode 103 forming the upper electrode.
It is configured to be located only directly below the gate wiring 104 of the transfer transistor of another memory cell passing above.

However, the hole 102 is covered with the gate wiring 104. By adopting such a structure, the difference in level between the pit line 105 passing over the gate wiring 104 and the base layer is further reduced by L.

That is, the semiconductor substrate 10 due to the formation of the hole 102
The unevenness on the surface of the cell plate electrode 103 and the gate 1 of the transfer transistor of the other memory cell passing between them
The wiring 104 is also used to fill in the holes. The increase in capacitance due to the groove formed in this manner is achieved by setting the ratio of the opening area of the groove to the area of the cell capacitor to be about 20 to 30%, and by setting the depth of the groove to 1.0 to 1.5%.
If it is designed to be 5 μm, it will be about 50 to 70%.

Furthermore, as the degree of integration improves and the area of the cell capacitor becomes smaller, the ratio of the opening area of the trench increases, and therefore the rate of increase in capacitance increases.

Although polysilicon is usually used as the wiring material for the cell plate electrode 103 and the gate wiring 104, it is also possible to use a high melting point metal such as molybdenum or tungsten, and in this case, the present invention also applies. Applicable.

〔Effect of the invention〕

As described above, according to the present invention, the opening of the trench capacitor of one memory cell is located only directly under the gate wiring of the transfer transistor of another memory cell, so that the opening of the trench capacitor of one memory cell is located directly below the gate wiring of the transfer transistor of the other memory cell. Since the -1tJ passitance hole is effectively filled, there are fewer irregularities on the surface of the semiconductor substrate, and there is an advantage that there is no need to break the wiring.

In addition, increasing the manufacturing process is 4T < full! l:j
Since it is possible to construct an X-shape, it is possible to achieve B-densification of the meshing device, and there is also an advantage that it is possible to avoid production costs.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a cell portion of a memory device according to an embodiment of the present invention, FIG. 2 is a plan view thereof, FIG. 3 is a cross-sectional view of a cell portion of a conventional semiconductor memory device, and FIG. 5 is a plan view of a conventional trench capacitor, FIG. 5 is a sectional view taken along line 8-A', and FIG. 6 is a sectional view of a conventional trench capacitor in which a trench is buried. 101... Semiconductor substrate, 102... Groove (hole) formed in capacitor portion, 103... Cell play 1-electrode, 104... Wiring to gate 1 of transfer transistor of other memory cell, 105 ...Pi 1~ line. Applicant's agent Sato - Richi Yuba 1.

Claims (1)

[Claims] In a semiconductor memory device in which a memory cell is configured by combining a capacitive element formed in a groove drilled on the surface of a semiconductor substrate and a transfer transistor formed on the surface of the semiconductor substrate adjacent to the capacitive element, one memory A semiconductor memory device characterized in that the trench of a cell is located only directly under a gate wiring of a transfer transistor of another memory cell.