JPS6294976A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent soft errors, by applying a groove-dug-type capacitor structure wherein an impurity layer having a specific impurity density and the same conduction type as a substrate is formed on the whole part of the substrate from the surface of a silicon substrate to the depth deeper than the bottom of the groove. CONSTITUTION:After boron ion implantation with a dosage of 1X10<13>cm<2> into a P-type substrate 1 having resistivity of 5OMEGA.cm, thermal treatment is performed at a temperature of 1,190 deg.C for 680min to form an impurity layer 3a, and the impurity density profile of the substrate is adjusted. a 3mum-deep groove 21 is dug on a silicon substrate, and arsenic is diffused to form an N-type impurity layer 2, and then a SiO2 film 6 of 100Angstrom thickness is grown on the inside wall of the groove 21 by thermal oxidation. A polysilicon electrode 8 is arranged to form a capacitor. A one transistor/one capacitor-type dynamic memory is completed by installing a transistor for readout. Prevention characteristics for soft error superior to or equal to the conventional Hi-C structure can be realized, thereby.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to a dynamic memory having a one-transistor/one-capacitor type memory cell.

[Technical background of the invention and its problems] The reason why this kind of one-transistor/one-capacitor type dynamic memory has been conventionally used as a structure that is particularly resistant to soft errors caused by alpha rays is that 6
It has a Hi-C (high capacitance cell) structure.

As shown in FIG. 4, this structure has an impurity concentration layer 3 of the same conductivity type, which has a higher impurity concentration than the silicon substrate 1, below the silicon substrate 1 on which information is to be stored and an impurity region 2 of the opposite conductivity type. This highly concentrated impurity layer forms a potential barrier against carriers, thereby preventing soft errors. In FIG. 4, 4 and 5 are regions (source, drain) of a conductivity type opposite to that of the substrate 1, 6 is an insulating film, 7 is a gate electrode, and 8 is a capacitance electrode.

FIG. 5 is an electrical equivalent circuit of FIG. 4, in which 11 is a transistor, 12 is a capacitor for storing information, 13 is a word line, and 14 is a bit line.

For capacitors formed on a plane, the conventionally used H1-c structure (Fig. 4) was sufficient, but with the increasing integration of LSIs, the structure shown in Fig. 6 has been used. Recently, a trench 21 has been dug in the silicon substrate 1 and the inner wall thereof has been used as a capacitor. In FIG. 6, parts corresponding to those in FIG. 4 are given the same reference numerals.

Even with this structure, it is theoretically possible to form a Hi-C structure as shown in FIG. 6, but as can be easily seen, the impurity region 3 cannot be easily formed using the conventional ion implantation method. . One method for forming this region 3 is to use a solid diffusion source such as a BSG film, but this requires quite a complicated process.

OBJECT OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a trench-type capacitor structure with soft error resistance equal to or higher than that of the conventional H;-C structure. The present invention aims to provide a semiconductor memory device that can be easily applied.

[Summary of the Invention] The present invention provides that when using a trench type capacitor structure, the impurity concentration in the entire substrate from the surface of the silicon substrate to a position deeper than the bottom of the trench is 1×1018 an'3 or more, and the impurity of the substrate is By providing an impurity layer having a higher concentration than the substrate and having the same conductivity type as the substrate, soft errors are prevented.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a sectional view showing the configuration of the same embodiment, but since this corresponds to that of the conventional example, the same reference numerals are used for corresponding parts. First, on the P-type basic board 1 with a specific resistance of 5Ω・air,
Boron ions were implanted at a dose of lX1013α.11
Thermal diffusion is performed at 90° C. for 680 minutes to form an impurity layer 3a, and the impurity concentration profile of the substrate is adjusted as shown in FIG. Next, a trench 21 with a depth of 3 μm is dug in the silicon substrate, arsenic is diffused to form an N-type impurity region 2, and then a 100-layer 5Lo2 film 6 is grown on the inner wall of the trench 21 by thermal oxidation. Thereafter, a polysilicon electrode 8 is provided, and a capacitor (corresponding to 12 in FIG. 5) is formed. After that, a writing/reading transistor (corresponding to 11 in Fig. 5) is installed adjacent to this capacitor, and by further performing predetermined wiring, a 1-transistor/1-capacitor type dynamic memory as shown in Fig. 1 is created. Complete.

Figure 3 shows the effect of the present invention, where the vertical axis is the soft error rate of a dynamic memory created by varying the boron ion implantation amount using the method described in the example, and the horizontal axis is the boron ion implantation rate. It is the dose amount. As is clear from FIG. 3, the present invention has a remarkable effect on reducing the soft error rate, and the boron ion implantation amount is reduced to 5×101
2cm''2, a dynamic memory with soft error resistance almost equivalent to that of the conventional Hi-C structure can be obtained.Also, by setting the boron ion implantation dose to 1×101
By setting it to 3 cm'2 or more, a significantly better soft error rate can be obtained compared to the conventional Hi-C structure.

At this time, as you can see from Figure 2, the above 5 x 10
In the case of an ion implantation dose of 12 cm 4 , the impurity concentration from the silicon substrate surface to the bottom of the trench 21 is approximately 1×10
It is 1S101S or more. Also, as in the example
If a dose of X10"cm' is used, the concentration of the impurity layer 3a will be approximately 2X1016cm' or more, but in this case, as mentioned above, a remarkable effect can be obtained compared to the conventional Hi-C structure. be.

[Effect of the invention] As explained above, according to the present invention, the conventional 1-(i-C
It is possible to provide a semiconductor memory device that can realize soft error resistance equivalent to or better than the structure and is easy to manufacture.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an embodiment of the present invention. Figure 3 is a characteristic diagram showing the effect, and Figure 4 is a conventional Hi-
FIG. 5 is a circuit diagram of a one-transistor/one-capacitance type memory cell, and FIG. 6 is a cross-sectional view of a modified structure of FIG. 4. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2.4.5...Region of conductivity type opposite to the substrate, 3a...Impurity concentration layer of lX10"cm-3 or more, 6...Insulating film, 7.8. ...Electrode. Applicant's representative Patent attorney Takehiko Suzue 1 Figure (Hm)

Claims (1)

[Claims] In a semiconductor memory device having one transistor/one capacitor type memory cell, a semiconductor substrate of one conductivity type and a semiconductor substrate having a higher concentration than the semiconductor substrate and having a size of 1×10^1^6 cm are used.
A semiconductor memory device characterized by having an impurity layer of one conductivity type with a concentration of ^-^3 or more, a groove formed in this impurity layer, and an electrode formed in this groove with an insulating film interposed therebetween. .