JPH0650767B2 - Method of manufacturing semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a dynamic memory having one transistor / one capacitor type memory cell.

[Technical Background of the Invention and its Problems] In this type of 1-transistor / 1-capacitor type dynamic memory, what has been conventionally used as a structure having resistance to a soft error caused by α-rays is so-called. It is a Hi-C (high capacitance cell) structure.
In this structure, as shown in FIG. 4, an impurity concentration layer 3 of the same conductivity type as that of the substrate 1 having an impurity concentration higher than that of the substrate 1 is provided under the impurity region 2 of the conductivity type opposite to that of the silicon substrate 1 for storing information. The high-concentration impurity layer forms a potential barrier against carriers, so that soft error is prevented. In FIG. 4, 4 and 5 are regions (sources and drains) of opposite conductivity type to the substrate 1, 6 is an insulating film, 7 is a gate electrode, and 8 is a capacitance electrode.

FIG. 5 is an electrical equivalent circuit of FIG. 4, 11 is a transistor, 12 is a capacitor for storing information, 13 is a word line, and 14 is a bit line.

The Hi-C structure conventionally used (FIG. 4) was sufficient for a capacitor formed on a plane, but as shown in FIG. It has come to be practiced to dig a groove 21 in the silicon substrate 1 and use its inner wall as a capacitor. In FIG. 6, parts corresponding to those in FIG. 4 are designated by the same reference numerals. Even with this structure, as shown in FIG.
Although it is possible in principle to adopt the C structure, as is easily understood, the impurity region 3 cannot be easily formed by the ion implantation method as in the conventional case. One method of forming this region 3 is to use a solid diffusion source such as a BSG film, but it requires a considerably complicated process.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object thereof is to have a soft error resistance equal to or higher than that of a conventional Hi-C structure, and to easily form a grooved capacitor structure. It is intended to provide a method of manufacturing a semiconductor memory device applicable to the above.

SUMMARY OF THE INVENTION The present invention provides an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ or more over the entire substrate from the surface of the silicon substrate to a position deeper than the bottom of the trench when a trench-type capacitor structure is used.
By providing an impurity layer having a conductivity type higher than that of the substrate and having the same conductivity type as that of the substrate, soft error is prevented.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First
The drawing is a cross-sectional view showing the structure of the same embodiment, but since this corresponds to the conventional example, the same reference numerals are used for corresponding portions. First, boron is ion-implanted into the P-type basic plate 1 having a specific resistance of 5 Ω · cm at a dose of 1 × 10 ¹³ cm ⁻² , and thermal diffusion is performed at 1190 ° C. for 680 minutes to form the impurity layer 3a. The impurity concentration profile of the substrate is adjusted as shown. Next, a groove 21 having a depth of 3 μm is dug in a silicon substrate, arsenic is diffused to form an N-type impurity region 2, and then a 100 Å SiO ₂ film 6 is grown on the inner wall of the groove 21 by thermal oxidation. Thereafter, a polysilicon electrode 8 is provided and a capacitor (corresponding to 12 in FIG. 5) is formed. After that, a transistor for writing and reading (corresponding to 11 in FIG. 5) is provided adjacent to this capacitor, and by further performing a predetermined wiring, a 1-transistor / 1-capacitor dynamic memory as shown in FIG. 1 is obtained. Complete.

FIG. 3 shows the effect of the present invention. The vertical axis represents the soft error rate of the dynamic memory created by changing the boron ion implantation amount by the method described in the embodiment, and the horizontal axis represents the boron ion implantation. The dose amount. As is clear from FIG. 3, the present invention shows a remarkable effect in reducing the soft error rate, and the boron ion implantation amount is 5 × 10 5.
^By setting the ^height to ¹² cm ^-2 , a dynamic memory having a soft error resistance almost equal to that of the conventional Hi-C structure can be obtained. The boron ion implantation dose is set to 1 × 10 ¹³
By setting it to be cm ⁻² or more, a remarkably good soft error rate can be obtained as compared with the conventional Hi-C structure. At this time, as can be seen by referring to FIG. 2, the above 5 × 10 ¹² cm
^If the ion implantation amount is ^-2, the groove 21 is formed from the silicon substrate surface.
The impurity concentration up to the bottom is approximately 1 × 10 ¹⁶ cm ⁻³ or more. If a dose amount of 1 × 10 ¹³ cm ⁻² is used as in the embodiment, the concentration of the impurity layer 3a is approximately 2 × 10.
¹⁶ cm ^-3 or more, but in this case the conventional H
The significant effect can be obtained as compared with the i-C structure.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device that can realize a soft error resistance equal to or higher than that of the conventional Hi-C structure and that has a simple structure.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, FIGS. 2 and 3 are characteristic diagrams showing the effect thereof, and FIG. 4 is a sectional view of a storage device having a conventional Hi-C structure, and FIG. The figure shows 1 transistor / 1
FIG. 6 is a circuit diagram of the capacitance type memory cell, and FIG. 6 is a sectional view of the modified structure of FIG. 1 ... Silicon substrate, 2, 4, 5 ... Region of opposite conductivity type to the substrate, 3a ... 1 × 10 ¹⁶ cm ⁻³ or more impurity concentration layer, 6 ...
Insulating film, 7, 8 ... Electrodes.

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor memory device having a transistor / 1 capacitor type memory cell, wherein the capacitor is formed on a P type semiconductor substrate with a dose of 1 ×.
Boron is ion-implanted at 10 ¹³ cm ^-2 or more to 1 × 10 ¹⁶ cm
A step of forming an ion-implanted layer having a concentration of ^-3 or more, a step of forming a groove in the ion-implanted layer that is shallower than the depth of the ion-implanted layer, and an N-type layer on the side wall and bottom wall of the groove. In forming the N-type layer, the step of forming the N-type layer so that the bottom of the N-type layer is located between the bottom wall of the groove and the bottom of the ion-implanted layer; And a step of forming an electrode layer for a capacitor, the method for manufacturing a semiconductor memory device.