JPH05182457A - Dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To provide the DRAM having a small cell size almost the some as the size of an SGT and high reliability. CONSTITUTION:Word lines 15 are formed via gate oxide films 14 on a (p) type silicon substrate 11 and (n) type diffusion layers 19, 20 are formed in the respective memory cell regions holding the word lines 15. Bit lines 21 connected to the (n) type diffusion layers 20 are disposed and are connected to the (n) type diffusion layers 19, by which accumulated node electrodes 22 overlapping on the word lines 15 coated with oxide films 16, 17 are formed. Grooves 18 are formed on the substrate along the word lines 15 in the stacked capacitor structure disposed with plate electrodes 25 via capacitor oxide films 24 on the accumulated node electrodes 22. The (n) type diffusion layers 19 are formed in the side wall parts of the grooves 18 and the accumulated node electrodes 22 are connected by the side wall parts to the (n) type diffusion layers 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM) using memory cells of 1 transistor / 1 capacitor.

[0002]

2. Description of the Related Art With the progress of miniaturization technology, miniaturization and high integration of DRAM have been remarkably advanced. As one of the miniaturization techniques of DRAM, a pillar-shaped semiconductor layer formed by digging a groove in a semiconductor substrate is used, and a gate electrode is formed on the outer periphery of the pillar-shaped semiconductor layer with a gate insulating film interposed between the pillar-shaped semiconductor layer and the bottom surface of the pillar-shaped semiconductor layer. A vertical SGT cell is known in which a MOS transistor (Surrounding Gate Transistor, hereinafter referred to as SGT) having a source diffusion layer and a drain diffusion layer respectively is used as a switching transistor.

11 (a) and 11 (b) are a perspective view and a sectional view showing an SGT cell. A gate electrode 3 is formed via a gate insulating film so as to surround the upper periphery of the columnar silicon layer 2 obtained by forming a groove in the silicon substrate 1. The gate electrodes 3 are continuously arranged in one direction to form word lines W.
It becomes L. An n ⁻ type diffusion layer 4 is formed as a storage node on the outer peripheral surface of the lower portion of the pillar-shaped silicon layer 2, and a plate electrode 5 is formed in a groove so as to face the storage node via a capacitor insulating film. An n ⁺ type diffusion layer is formed on the upper surface of the pillar-shaped silicon layer 2, and the bit line 6 contacting this is formed.

By laying out such an SGT cell by the open bit line system, the cell size is significantly reduced as compared with the case where a conventional planar structure MOS transistor using the folded bit line system is used. be able to. Ideally considering the design rule F [μm], the cell size is 8 in the conventional folded bit line method using the planar MOS transistor.
It becomes F ² . On the other hand, in the SGT cell, the cell size can be reduced to about 4F ² by half.

However, the conventional SGT shown in FIG.
In the cell, since the n ⁻ type diffusion layer formed on the outer periphery of the columnar silicon layer is used as the storage node, the storage node area is large, and therefore the reliability such as the soft error resistance and the pause characteristic is not sufficient.

On the other hand, when the cell size of the DRAM is reduced, the layout of the sense amplifier becomes difficult. In particular, in the open bit line system in which paired bit lines are arranged on both sides of the sense amplifier, one sense amplifier is required for each bit line in principle, so if the bit line pitch is narrow, layout of the sense amplifier is difficult. become. On the other hand, a relaxed open bit line system is considered in which one sense amplifier is arranged for two bit lines to be an open bit line system, but the bit line pitch is still very small. If the layout of the sense amplifier is not easy.

[0007]

As described above, the conventional S
Although the GT cell can reduce the cell size, it has a problem of insufficient reliability.

Further, as the cell size of DRAM is reduced,
Especially when the open bit line system is adopted, there is a problem that the layout of the sense amplifier becomes difficult.

It is an object of the present invention to provide a DRAM that has both reduced cell size and reliability.

It is another object of the present invention to provide a DRAM in which the layout of sense amplifiers is facilitated by the open bit line method using miniaturized memory cells.

[0011]

SUMMARY OF THE INVENTION The present invention is first, first,
A gate electrode, which is formed on a conductive type semiconductor substrate via a gate insulating film and serves as a word line continuous in one direction, and a second conductive type first and second electrodes formed in each memory cell region with the gate electrode interposed therebetween. A second diffusion layer, a bit line which is in contact with the first diffusion layer and is continuously arranged in a direction intersecting the word line, and a second diffusion layer which is in contact with and covered with an insulating film. In a stacked capacitor structure DRAM having a storage node electrode drawn out on the exposed word line and a plate electrode provided on the storage node electrode via a capacitor insulating film, a substrate is provided along the word line. A groove is formed, the second diffusion layer is formed on a side wall portion of the groove, and the storage node electrode is brought out on the word line in contact with the second diffusion layer at the side wall portion. To.

Secondly, the present invention is characterized in that in the open bit line type DRAM, the sense amplifier circuits are laid out at a ratio of one to four bit lines.

[0013]

According to the first aspect of the present invention, the area of the diffusion layer to which the storage node electrode is connected can be made smaller than that of the SGT cell by one digit or more. Therefore, the reliability such as the soft error resistance and the pause characteristic can be improved. Better than a cell. Moreover, since the contact portion of the storage node electrode is provided on the side surface of the groove instead of the flat portion, the cell size can be made smaller than the cell of the conventional stacked capacitor structure, and a small cell size similar to SGT can be realized.

According to the second invention, the relaxed open bit line system is further extended to the layout of the sense amplifier circuit, and one sense amplifier circuit is arranged for every four bit lines. The layout of the sense amplifier circuit when the fine cell structure obtained by the invention is adopted becomes easy.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

1A and 1B are a memory cell layout of a DRAM according to an embodiment of the present invention and a sectional view taken along the line AA '. In the memory cell of this embodiment, the diffusion layers serving as the source and the drain are 45 ° with respect to the word line and the bit line.
A bit line prefabricated type stacked cell structure cell (DASH cell) formed in a direction, a diffusion layer connected to a storage node electrode is formed on a groove side wall, and the diffusion layer is contacted with the groove side wall. The storage node electrode is drawn out.

A specific description will be given according to the manufacturing process. Figure 2
5A to 5C are plan views of respective steps corresponding to the plan view of FIG. 1A, and FIGS. 6A to 6D show A of respective steps corresponding to FIG. 1B.
It is a -A 'sectional view. First, the first trench 12 is formed in the p-type silicon substrate 11 by etching the isolation region by RIE so that the two memory cell regions become one island region. An isolation oxide film 13 is embedded in the first groove 12 (FIGS. 2 and 6 (a)). The area surrounded by the broken line in FIG. 2 is one memory cell area. The first groove 12 has a design rule of F and a depth of about 2F and a width of about 0.5F. The width of the first groove 12 is narrower than the design rule,
This can be formed by utilizing edge emphasis type phase shift or the like.

Then, two word lines 15 are provided in the island region surrounded by the first trench 12 with the first-layer polycrystalline silicon via the gate oxide film 14. Oxide films 16 and 17 are formed on the sidewalls and upper surface of the formed word line 14. Then, an n-type diffusion layer 20 serving as a common drain layer is formed in a region sandwiched by the word lines 15, and the bit line 2 arranged in a direction orthogonal to the word line 15 is contacted with the diffusion layer 20.
1 is formed by the second layer polycrystalline silicon (FIGS. 3 and 6).
(b)). The surface of the formed bit line 21 is covered with an oxide film 26. Oxide film 26 covering word line 21 and word line 1
The oxide films 16 and 17 covering the layer 5 serve to prevent the bit line 21 and the word line 15 from being etched during the subsequent formation of the second groove.

After that, the substrate is etched by using the oxide film as a mask to form a second groove 18 wider than the first groove 12 so as to overlap the first groove 12 along the word line 15. The second groove 18 has a depth F. Then, after lightly oxidizing to form a thin oxide film 27 on the inner wall of the second groove 18,
A resist 29 is left on the bottom of the second groove 18 by using etch back (FIGS. 4 and 6 (c)).

Next, an oxide film etching is performed using the resist 29 left on the bottom of the second groove 18 and the resist pattern having an opening shown by hatching in FIG.
Expose the sidewalls of. Then, the third-layer polycrystalline silicon is deposited and patterned to form the storage node electrode 22 which comes into contact with the side wall of the second trench 18 and is drawn out onto the word line 15. At this time, the third-layer polycrystalline silicon is doped with an n-type impurity in advance, and the impurity is diffused to form an n-type diffusion layer 19 on the side wall of the second trench 18, and the storage node electrode 22 is Direct contact with. Then the second groove 1
8 is filled with an oxide film 23, a capacitor oxide film 24 is formed on the surface of the storage node electrode 22, and then a plate electrode 25 is provided on the entire surface (FIGS. 5 and 6 (d)).

The portion of the first groove 12 below the word line 15 and the word line 15 are patterned so as to intersect each other at 45 °, whereby the storage node electrode 22 is contact-connected. The n-type diffusion layer 20 in which the type diffusion layer 19 and the bit line 21 are contact-connected is the word line 1
5 and bit line 21 in the direction of 45 °.

In this embodiment, the size of the unit cell area shown by the broken line in FIG. 1 is 2.125F in the running direction of the bit line.
(Word line interval: F / 2 + word line width: F + half of side wall contact separation: F / 2 + side wall contact alignment:
0.125F), and the running direction of the word line is 2.37.
5F (bit line width: F + capacitor electrode width: F + other insulating film thickness: 0.375F), which is about 5F ² . That is, while having a stacked capacitor structure,
It has a small cell size equivalent to the SGT cell. Then, the n-type diffusion layer 1 with which the storage node electrode 22 contacts
The area of 9 is sufficiently smaller than that of the SGT cell, so that excellent soft error resistance and pause characteristics can be obtained.

FIG. 7 shows an embodiment of a cell layout using the cell structure of the present invention. Similar to the case of the SGT cell, the layout is performed by the open bit line method. MCA1,
MCA2 is a memory cell array section, and SA is a sense amplifier section. The sense amplifier section SA has a system in which one sense amplifier is arranged on four bit lines.

Bit line B of memory cell array section MCA1
L1 and BL2, a memory cell array portion M paired with these
For the bit lines / BL1 and / BL2 of CA2, the sense amplifier section SA includes an equalize / precharge circuit 31 for the bit line BL2 and a DQ gate circuit 3 for the bit line BL2.
2. PMOS flip-flop circuit 3 for bit line BL1
3, bit line BL2 PMOS flip-flop circuit 3
4, NMOS flip-flop circuit 3 for bit line BL1
5, NMOS flip-flop circuit 3 for bit line BL2
6, a DQ gate circuit 37 for bit line BL1 and an equalize / precharge circuit 38 for bit line BL1.

8 to 10 show the sense amplifier section S of FIG.
It is an example of a pattern in which A is actually laid out by three-layer polycrystalline silicon and two-layer Al.

[0026]

As described above, according to the present invention, the area of the diffusion layer to which the storage node electrode is connected is less than that of the SGT cell.
It is possible to provide a DRAM that is smaller than a digit, has excellent soft error resistance and pause characteristics, and has a cell size as small as an SGT cell.

[Brief description of drawings]

FIG. 1 is a plan view showing a memory cell structure of a DRAM according to an embodiment of the present invention and its AA ′ cross-sectional view,

FIG. 2 is a plan view showing a first groove formation state of the embodiment,

FIG. 3 is a plan view showing a word line and bit line formation state of the embodiment.

FIG. 4 is a plan view showing a second groove formation state of the embodiment,

FIG. 5 is a plan view showing the final structure of the memory cell portion of the embodiment,

FIG. 6 is a cross-sectional view showing the manufacturing process of the embodiment.

FIG. 7 is a diagram showing a layout example in which the memory cells of the same embodiment are arranged by an open bit line system.

FIG. 8 is a diagram showing a specific layout pattern of the sense amplifier section SA of FIG.

9 is a diagram showing a specific layout pattern of the sense amplifier section SA of FIG.

10 is a diagram showing a specific layout pattern of the sense amplifier section SA of FIG.

FIG. 11 is a diagram showing a conventional SGT cell.

[Explanation of symbols]

 11 ... P-type silicon substrate, 12 ... First groove, 13 ... Oxide film, 14 ... Gate oxide film, 15 ... Word line, 16, 17 ... Oxide film, 18 ... Second groove, 19 ... N-type diffusion layer (Storage node contact layer), 20 ... N-type diffusion layer (bit line contact layer), 21 ... Bit line, 22 ... Storage node electrode, 23 ... Oxide film, 24 ... Capacitor oxide film, 25 ... Plate electrode.

Claims (2)

[Claims] 1. A gate electrode formed on a first conductivity type semiconductor substrate via a gate insulating film to be a word line continuous in one direction, and a first gate electrode formed in each memory cell region with the gate electrode interposed therebetween. Two conductive type first and second diffusion layers, a bit line which is in contact with the first diffusion layer and is continuously arranged in a direction intersecting the word line, and a second diffusion layer In a dynamic semiconductor memory device having a storage node electrode which is brought into contact with the word line and which is drawn out onto the word line covered with an insulating film, and a plate electrode which is disposed on the storage node electrode via a capacitor insulating film, A groove is formed in the substrate along a word line,
Dynamic diffusion layer is formed on the side wall of the groove, and the storage node electrode is brought out to the word line in contact with the second diffusion layer on the side wall. .. 2. A dynamic semiconductor memory device having a memory cell of 1 transistor / 1 capacitor and having a sense amplifier circuit of an open bit line system, wherein the sense amplifier circuit is laid out at a ratio of 1 to 4 bit lines. And a dynamic semiconductor memory device.