JPS62136869A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory device integrated with a high density by a method wherein a capacitor is provided in a groove formed in a semiconductor substrate and a transistor is provided on an insulating layer formed selectively on the semiconductor substrate and the capacitor and the adjoining transistor are connected by the region of the semiconductor substrate adjacent to the side wall of the insulating layer. CONSTITUTION:An N<+> type diffused region, which is to be one of the electrodes of a capacitor is connected to the source region of a TFT by single crystal 4 and the connection is secured. Moreover, the connection can be formed by a self-alignment manner with a part of a mask pattern for a trench and a part of a mask pattern for a transistor overlapping each other. As a transistor provided on an SiO2 layer 3 has an SOI structure, a space required for separating elements can be small. In other words, the transistor and the capacitor are separated by the side of the depth direction and the side of the horizontal direction of the SiO2 layer 3 which is selectively formed and to be a field oxide film. Moreover, as the separation between capacitors is achieved by a P-N junction including a P<+> type region 2, the element separating structure of this DRAM is very simple.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a novel structure of a DRAM suitable for increasing density.

C. Summary of the Invention] The present invention provides a semiconductor memory device composed of one transistor and one capacitor, in which the capacitor is provided in a groove formed in a semiconductor substrate, and the transistor is selectively placed on the semiconductor substrate. The capacitor and the transistor adjacent thereto are connected by the semiconductor substrate region adjacent to the sidewall of the insulating layer, thereby providing a highly integrated semiconductor memory device. be.

[Conventional technology]

2. Description of the Related Art As the density of semiconductor integrated circuits has increased, technology has been developed to reduce the area occupied by the capacitor by forming a trench and building a capacitor therein.

An example of a 4M memory cell structure using a trenched capacitor will be described with reference to FIG. (Nikkei Micro Device Spring 1985 Issue pp. 16-18) Each transistor is surrounded by an isolation oxide film 19 in an isolation trench. Separation oxidation JJ! A polycrystalline Si electrode is formed on the outside of 19, which constitutes one capacitor electrode and is connected to the source of the transistor. Capacitor insulation film 2
The polycrystalline Si cell plate 22 sandwiching the capacitor 1 serves as the electrode of the other capacitor. The drain D is connected to the bit line via the contact hole 23. In this cell structure, a transistor and a capacitor are formed in parallel with a bit line, and one trench functions as both an element isolation function and a capacitor function.

[Problem that the invention seeks to solve]

The conventional trenched capacitor DRAM structure has a problem in that the connection between the capacitor and the transistor cannot be made by self-line. Moreover, the connection is made using polycrystalline Si.

Further, in the conventional trenched capacitor DRAM structure, there is a problem in that a thin oxide film must be precisely formed in the polycrystalline Si in the trench. In other words, it is necessary to provide element isolation and capacitor functions to a single trench, so multiple oxide films must be formed within the trench, and achieving this requires extremely advanced and complex technology. .

Furthermore, the conventional trench capacitor structure also has a problem in that the area required for isolation between elements and the area of the capacitor are still large.

[Means for solving problems]

A transistor is provided on an insulating layer selectively formed on a semiconductor substrate, a trench is formed in the semiconductor substrate and a capacitor is built therein, and the capacitor and the transistor adjacent to the capacitor are adjacent to the side wall of the insulating layer. The above problem was solved by adopting a configuration in which areas are separated.

[Effect]

The N diffusion region, which is one electrode of the capacitor, is made of TPT (
It is connected to the source region of a thin film transistor (Thin Film Transistor) by a single crystal, and the connection is more reliable than in conventional DRAMs. Moreover, the connection can be made by self-line by partially overlapping the trench mask pattern and the transistor mask pattern.

Since the transistor provided on the SiO□ layer 3 has an SOI structure, the space required for isolation between elements is smaller than that of the conventional one. In other words, the transistor and the capacitor are separated by the depth and lateral sides of the SiO□ layer 3, which is selectively formed as a field oxide film.

Further, since the capacitors are isolated from each other by a PN connection including the P'' region 2, the element isolation structure of the DRAM of the present invention is extremely simple compared to that of the conventional DRAM.

〔Example〕

FIG. 1A shows a sectional view in the channel length direction of the novel RAM of the present invention, and FIG. 1B shows a sectional view in the channel width direction. an N″ region formed by diffusion of a donor from the inner surface of a trench dug for forming a capacitor;
This is one electrode of the capacitor. A thermal oxide film 11 of 100 layers becomes a capacitor insulating film, and a polycrystalline Si layer 12 buried inside the trench serves as a cell plate of the capacitor.

A TPT is provided on a selective oxide film 3 on a P diffusion layer 2 on the surface of a P-type Si substrate. The Si semiconductor layer 4 is made into a single crystal by recrystallization technology, and the source region and drain region are formed in a self-aligned manner by ion implantation using the gate oxide film 14, polycrystalline gate electrode 6, and W-5i electrode 7 as masks. has been done. The source region is connected to the capacitor electrode N'. It is connected to the bit line 9 of the drain/C drain electrode AI.

The word line made of polycrystalline Si 6 and -Si layer 7 is covered with CvD oxide film 8 .

FIG. 1C is a diagram showing the positional relationship between the word line, the focus line, the trench mask pattern 15, and the transistor mask pattern 16. The cross-sectional view taken along the dashed-dotted line A-A is the first one.
In FIG. 1C, a sectional view taken along the dashed-dotted line B-'B is shown in FIG. At a place where the trench mask pattern 15 and the transistor mask pattern I6 overlap,
A transistor and a capacitor are connected to the self-line in the N layer.

The specifications of the DRA gate of the present invention are as follows: Cell size: 1.5 x 2.5 = 3.75μ
d capacitor: 5.8 (peripheral)
It is l1m.

〔Effect of the invention〕

The structure of the DRAM of the present invention has the effect that the capacitor and the transistor are connected by a self-line through the N' single crystal layer.

Furthermore, the present invention does not require extremely sophisticated technology such as forming two thin oxide films in the polycrystalline Si inside the trench, unlike the conventional method for manufacturing a trenched capacitor DRAM. This is because the present invention employs a simple element structure and simplifies element isolation. The capacitor and the transistor are separated by the side surfaces and top surface in the depth direction of the field oxide film 3, and the capacitors are separated by a PN junction. As a result, the cell size could be reduced to 3.75 μm', while the capacitance of the capacitor could be increased to 55.6 fF.

[Brief explanation of drawings]

FIG. 1A is a sectional view in the channel length direction of the DRAM of the present invention. FIG. 1B is the DI of the present invention? FIG. 3 is a cross-sectional view in the direction of the channel of AM. FIG. 1C is a layout diagram of a mask pattern of a DRAM according to the present invention. FIG. 2 is a diagram showing the cell structure of a conventional DRAM. ■...SiP type substrate 2...P layer 3...
・CVO oxide film 4...Si layer 5...gate region 6...polycrystalline Si gate electrode 7...
・-Si gate electric scraper 8...5in2 layer 9...
Bit line 10...N゛diffusion layer 11...
Thermal oxide film 12... Polycrystalline Si layer 13...
Thermal oxide film 14・Group gate oxide film 15・・・Mask pattern for trench 16・・Mask butter for transistor 17・・Word line 18・Group polycrystalline Si electrode 19・・・Separate oxidation Film 2o...Polycrystalline Si electrode 21...Capacitor insulating film 22...Polycrystalline Si cell plate 23...Contact hole

Claims (1)

[Claims] In a semiconductor memory device constituted by one transistor and one capacitor, the transistor is arranged on an insulating layer selectively formed on a semiconductor substrate, and the capacitor is arranged on an insulating layer selectively formed on a semiconductor substrate. A semiconductor memory device formed by a groove formed in a substrate, and wherein the transistor and the capacitor are connected by the semiconductor substrate region adjacent to the sidewall of the insulating layer.