JPS6286754A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To avoid the deviation of channel lengths by providing a part where a capacitor plate overlaps a word line. CONSTITUTION:After a thin oxide film and a field oxide film 5 are formed on a P-type silicon substrate 1, a word line 3 is patterned to have a width L1. After the word line 3 is covered with a thin oxide film, a capacitor plate 4 is patterned so as to make a part of the plate 4 overlaps the word line 3. After that, an N<+> type diffused region 2 is formed by ion implantation or the like and a layer insulating film 6, a bit line 7 and so forth are laminated one upon another. With this constitution, the channel lengths of MOS transistors which perform switching operation can be uniformized through the respective memory cells and, moreover, the distance between the word line ad the capacitor plate can be shortened so that the integrity can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a dynamic type R
AM relates to so-called DRAM.

[Summary of the invention]

The present invention prevents variations in channel length by forming a capacitor plate on a word line in a semiconductor memory device consisting of a memory cell composed of one capacitor and one transistor, and also makes it possible to manufacture the semiconductor memory device. It has a simple structure.

[Conventional technology]

2. Description of the Related Art In general, a so-called DRAM, a semiconductor memory device, is known as a semiconductor memory device, which is composed of a memory cell composed of one capacitor and one transistor.

Such a semiconductor memory device is formed on a semiconductor substrate such as a silicon substrate, and has a MOS transistor (MOS) that performs a switching operation and a capacitor that stores information signals formed in one memory cell by a capacitor plate. .

Here, an example of a conventional semiconductor memory device including a memory cell configured with one capacitor and one transistor will be briefly described with reference to FIGS. 3 and 4.

First, as the above semiconductor memory device, there is a semiconductor memory device (semiconductor device) having a structure as shown in FIG. The structure of this semiconductor device is such that a gate electrode of a MOS transistor is partially laminated on a capacitor plate, and n+ type diffusion regions B1, B1 facing the main surface of a silicon substrate S.
2 and B3 are formed, and an inversion layer (channel portion) D is further formed under the capacitor plate (first layer polycrystalline silicon) Pl. MOS that performs switching operation
) The transistors T2 and T3 use the first layer polycrystalline silicon P2 connected to the word line A as a gate electrode, the n+ type diffusion regions Bl and B3 as drains, and the inversion layer as a source.

Further, as another conventional semiconductor memory device, an example of a semiconductor memory device as shown in FIG. 4 is also known. The structure of this semiconductor memory device is such that the gate electrode of the MOS transistor and the capacitor plate are arranged at a distance of 12 without being stacked, and are connected to the bit line 12 facing the main surface of, for example, a p-type silicon substrate 14. An n small diffusion region 18S is formed, and an n+ type diffusion region 18D is further formed under the region between the capacitor plate (electrode) -13 and the word line 11 facing the main surface. The word line 11 becomes a gate electrode of a MOS transistor that performs a switching operation. An inversion layer 15 is formed under the capacitor plate 13, and includes a field oxide film 171 and an interlayer insulating film 16. An insulating film 19 is formed respectively.

[Problem that the invention seeks to solve]

The semiconductor memory device as described above has the following problems in terms of manufacturing process.

First, as shown in FIG. 3, a semiconductor memory device having a structure in which a gate electrode of a MOS transistor, that is, a second N polycrystalline silicon P2 is partially laminated on a capacitor plate P1, has a structure in which this capacitor plate P1 and a second N polycrystalline silicon P2 are partially stacked. When the positional shift of polycrystalline silicon P2 occurs, the channel length N0s
Each dimension of A1 changes, resulting in a lack of uniformity in the switching operation of each MO3) transistor.

Furthermore, as shown in FIG. 4, a semiconductor memory device having a structure in which a word line 11, which is a gate electrode of a MOS transistor, and a capacitor plate 13 are arranged at a distance of 12 without being laminated has the above-mentioned dimensional accuracy of the channel length. Although there is no problem with variations, it is necessary to leave a distance of 12, and the degree of integration cannot be improved. In addition, the n-type diffusion region 18
Forming D is inconvenient in the manufacturing process.

Therefore, in view of the above-mentioned problems, the present invention has good dimensional accuracy of the channel length of the MOS transistor of each memory cell, and
Another object of the present invention is to provide a semiconductor memory device that is easy to manufacture without sacrificing the degree of integration of memory cells.

[Means for solving problems]

The present invention solves the above-mentioned problems by using a semiconductor memory device including a memory cell configured with one capacitor and one transistor, which has at least a portion where a capacitor plate overlaps on a word line.

[Effect]

Since the word line has at least a portion where the capacitor plate overlaps, the word line is not affected by the positional relationship with the capacitor plate, and the pattern width of the word line directly becomes the width of the gate electrode of the MO3I transistor. Therefore, the channel length of the MO3I-transistor that performs the switching operation is uniform for each memory cell. Furthermore, the structure in which the capacitor plate overlaps the word line improves the degree of integration without arranging the word line and the capacitor plate with a certain distance between them. Furthermore, since the distance between the word line and the capacitor plate is shortened, there is no need to form an impurity diffusion region by introducing impurities, which is convenient in terms of manufacturing process.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

This embodiment is a semiconductor memory device consisting of a memory cell composed of one capacitor and one transistor, and has a structure in which at least a portion where a capacitor plate overlaps a word line is provided. This example is used in a layout having a rectangular active region (inversion layer) as described later.

First, regarding the structure of the semiconductor memory device of this embodiment, as shown in FIG.
The diffusion region 2 of this type and the capacitor plate 4 form an inversion layer 9 which becomes the capacitance of a capacitor. In the upper part between this inversion N9 and the n-type diffusion region 20, a word line 3, which becomes a gate electrode of a MOS transistor that performs a switching operation, is patterned with a pattern width L1. The capacitor plate 4 is made of, for example, polycrystalline silicon and covered with a thin insulating film.The capacitor plate 4 has a shape in which the entire surface of the capacitor plate 4 is covered and an end portion 4a of the capacitor plate is opened. And this capacitor plate 4 is
It overlaps the word line 3 with a thin insulating film interposed therebetween.

The capacitor plate 4 is made of polycrystalline silicon, for example. Incidentally, since the memory cells are separated by field oxide film 5 and a multilayer structure is formed, capacitor plate 4 and bit line 7 are insulated by glabellar insulating film 6 such as PSG (phosphorus silicate glass).

When manufacturing the semiconductor memory device of this embodiment having such a structure, after forming a thin oxide film or field oxide film 5 on the p-type silicon substrate 1, word lines 3 are patterned to have a width L1. . After covering the word line 3 with a thin oxide film, a part of the capacitor plate 4 is overlapped on the word line 3, that is, the word line 3 is covered with a thin oxide film.
The capacitor plate 4 is patterned so as not to leave a gap between the capacitor plate 4 and the capacitor plate 4. Thereafter, the n-type diffusion region 2 is formed by ion implantation or the like, and the glabella insulation 116, the bit line 7, etc. are laminated.

In the semiconductor memory device of this embodiment, the word lines 3 are formed as described above, and then the capacitor plates 4 are formed. Therefore, the pattern width L1 of the word line 3 becomes the width of the gate electrode of the MOS transistor. Therefore, the channel length of the MOS transistor directly reflects the pattern width of the word line 3, and the channel length of each memory cell is reliably constant.

Further, since the capacitor plate 4 is formed overlapping the word line 3 without leaving a gap, the degree of integration is improved, and memory cells can be arranged at a high density to realize a high-performance DRAM.

Furthermore, by adopting such a structure, there is no need to form a region to serve as a diffusion region for the MO3I transistor, as was conventionally done. Therefore, in terms of the manufacturing process, the ion implantation process is simplified, and in terms of microfabrication, the characteristics of each memory cell element are stabilized if even the pattern formation of the word line 3 is controlled reliably.

Further, since there is no need to form an extra diffusion region, the region where a diffusion region is conventionally formed, for example, the region of the n-type diffusion region 18D in FIG. The capacitor capacity can be increased with the same occupied area.

Furthermore, since the expanded Mil region of the MOS transistor can be on one side, the so-called bunch-through voltage can be increased, and the channel can be shortened accordingly. Therefore, the structure is compatible with high-speed operation.

The semiconductor memory device of this embodiment can be arranged in a layout as shown in FIG. 2, for example. still,
In FIG. 2, the same reference numerals as in FIG. 1 are used for the same regions. Further, in FIG. 2, a cross-sectional portion corresponding to the cross-sectional view of FIG. 1 is indicated by line II.

The layout shown in FIG. 2 is an example of a semiconductor memory device having a rectangular inversion layer 9, and for example, the area indicated by the two-dot chain line in FIG. 2 is one memory cell 10a or one memory cell 10b. These memory cells 10a and memory cells 10b are arranged in a pair. The word line 3 is patterned as a first polycrystalline silicon layer on a p-type silicon substrate through a thin oxide film, and the word line 3 is not directly placed on the inversion layer 9 of an adjacent memory cell. is taken into consideration. Further, after the formation of the first polycrystalline silicon layer, the capacitor plate 4 is once deposited on the entire surface as a second polycrystalline silicon layer.
Part a is opened. The rectangular inversion layer 9 is
They are arranged at regular intervals along the bit line 7, and are shifted for each column. That is, the central portions of the pair of memory cells are adjacent to the isolation region of the adjacent column of memory cells. For example, a shaded area C in one memory cell in FIG. 2 is an area where the capacitor plate 4 overlaps the word line 3.

By adopting such a layout, first, the word line 3 is not located on the rectangular inversion N9, which is the active area, and therefore, the word line 3 and the inversion 119 are separated to prevent adverse effects. can. In addition, in conventional memory cells, the degree of integration was reduced in the MOS transistors that perform switching operations in order to separate memory cells from each other, but as in the layout of this embodiment, MOS transistors perform switching operations.
The transistor part is an inversion layer 9 which is the active region of the next column.
are sufficiently separated, and no additional area is required for separation.

In the above-described embodiment, the substrate is of p-type and the diffusion regions are of n-type, but the present invention is not limited to this, and other conductivity types may be used. Further, the shape of the inversion layer is not limited to a rectangle, and any shape may be used.

〔Effect of the invention〕

Since the semiconductor memory device of the present invention has a structure in which a capacitor plate is stacked on a word line, the pattern width of the word line directly becomes the width of the gate electrode of the MO3) transistor, and the channel length of the MOS transistor that performs the switching operation is Each memory cell is uniform. Further, since the capacitor plate overlaps the word line, the distance between the word line and the capacitor plate is shortened, and the degree of integration is improved. Furthermore, when manufacturing the semiconductor memory device of the present invention, since the distance between the word line and the capacitor plate is shortened, there is no need to form an impurity diffusion region by introducing impurities, which is convenient in terms of the manufacturing process, and improves performance. A stable semiconductor memory device can be manufactured.

Furthermore, it can correspond to shorter channels.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor memory device of the present invention, FIG. 2 is a layout diagram thereof, FIG. 3 is a sectional view of a conventional semiconductor memory device, and FIG. 4 is a sectional view of another conventional semiconductor memory device. be. 1...Silicon substrate 2...Diffusion region 3...Word line 4...Capacitor plate 9...Inversion layer patent Applicant Sony Corporation representative Patent attorney Kobu Mima Sakae Tamura

Claims (1)

[Claims] A semiconductor memory device comprising a memory cell configured with one capacitor and one transistor, the semiconductor memory device having at least a portion where a capacitor plate overlaps on a word line.