JP2572864B2 - A method of manufacturing a semiconductor device - Google Patents

A method of manufacturing a semiconductor device

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Publication number
JP2572864B2
JP2572864B2 JP2023898A JP2389890A JP2572864B2 JP 2572864 B2 JP2572864 B2 JP 2572864B2 JP 2023898 A JP2023898 A JP 2023898A JP 2389890 A JP2389890 A JP 2389890A JP 2572864 B2 JP2572864 B2 JP 2572864B2
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layer
conductive layer
ring
insulating layer
insulating
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JPH03227566A (en
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守昭 赤澤
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三菱電機株式会社
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10861Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor being in a substrate trench
    • H01L27/10864Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor being in a substrate trench in combination with a vertical transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • H01L27/10838Dynamic random access memory structures with one-transistor one-capacitor memory cells the capacitor and the transistor being in one trench
    • H01L27/10841Dynamic random access memory structures with one-transistor one-capacitor memory cells the capacitor and the transistor being in one trench the transistor being vertical

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置及びその製造方法に関し、特にキャパシタ部として、いわゆるトレンチキャパシタ,トランジスタ部として縦型MOSトランジスタを配したダイナミック型記憶装置の構造に関するものである。 DETAILED DESCRIPTION OF THE INVENTION The present invention [relates] relates to a semiconductor device and a manufacturing method thereof, particularly as a capacitor portion, the structure of a dynamic memory device arranged vertical MOS transistor so-called trench capacitor, a transistor portion it relates.

〔従来の技術〕 [Prior art]

近年、半導体装置の高集積化が要求され、それに従い、半導体記憶装置においては1bitの情報を記憶するメモリセルの面積を縮小することが最大の技術課題となっている。 Recently, high integration is required for semiconductor device, accordingly, to reduce the area of ​​the memory cell for storing information of 1bit is the greatest technical challenge in the semiconductor memory device. ダイナミック型記憶装置においては、キャパシタ部,ドレイン部,及び素子分離部の各部の面積をできるだけ小さくすることが必要であり、この要求に対して従来、キャパシタ部としてトレンチキャパシタを採用し、トランジスタ部として同じトレンチ側面にMOSトランジスタを形成し、分離部は選択酸化膜を利用したダイナミック型記憶装置が提案されている。 In dynamic memory device, a capacitor portion, a drain portion, and it is necessary to minimize the area of ​​each part of the element isolation portion, prior to this request, the trench capacitor is employed as a capacitor portion, a transistor portion the MOS transistor is formed in the same trench side, separating unit dynamic storage device using a selective oxide film has been proposed. 第6図は従来の上述の構成をもつダイナミック型記憶装置を示す断面図である。 Figure 6 is a sectional view showing a dynamic memory device having a conventional configuration described above. 図において、21はp型Si基板、22はp型エピタキシャル層、23は選択酸化膜、24はドレイン、5は誘電膜、6は第1導電層、8はゲート絶縁膜、3は第2導電層である。 In the figure, the p-type Si substrate 21, 22 is p-type epitaxial layer, the selective oxide film 23, 24 is the drain, the dielectric film 5, the first conductive layer 6, the gate insulating film 8, the second conductive is 3 it is a layer.

次に製造工程について説明する。 Given of the fabrication process will be described.

まず、p型の不純物を含むSi基板21の上にこれより低い密度でp型不純物を含むSiエピタキシャル層22を形成し、この表面を素子分離すべき所のみを選択的に酸化し、選択酸化膜23を形成した後、ヒ素等のn型不純物のイオン注入及び熱処理により、ビット線をかねたドレイン24をp型エピタキシャル層22表面に形成する。 First, an Si epitaxial layer 22 to form, including a p-type impurity at a lower density than this on the Si substrate 21 including a p-type impurity, is selectively oxidized only place to be the surface isolation, selective oxidation after forming the film 23, by ion implantation and heat treatment of the n-type impurity such as arsenic, to form a drain 24 which serves as a bit line to the p-type epitaxial layer 22 surface.

次に所定の場所にp型基板21に達する孔を開け、内側にSi酸化膜、Si窒化膜等の誘電膜5、及びリン等のn型不純物を含むポリシリコンからなる第1導電層6をp型エピタキシャル層22の途中まで埋め込む。 Then a hole reaching the p-type substrate 21 in place, Si oxide film on the inside, the dielectric film 5, such as Si nitride film, and the first conductive layer 6 made of polysilicon containing an n-type impurity such as phosphorus embedded halfway in the p-type epitaxial layer 22. 但し、この時第1導電層6とp型エピタキシャル層22が導通するよう誘電膜5を後退させておく。 However, it allowed to retract dielectric film 5 so that this time the first conductive layer 6 and the p-type epitaxial layer 22 becomes conductive.

次にp型エピタキシャル層22の表面(ドレイン24の表面も含む)にゲート絶縁膜8を形成したのち、リン等を含むポリシリコンからなる第2導電層3を配してワード線にパターニングする。 Then after forming the gate insulating film 8 on the surface of the p-type epitaxial layer 22 (including the surface of the drain 24), it is patterned by disposing a second conductive layer 3 made of polysilicon containing phosphorus or the like to the word line.

ところで、この構造のメモリセルの動作はMOSトランジスタの構成として、まず出入力を制御するワード線をかねた第2導電層3をゲート電極とし、出入力を行うビット線をかねたドレイン24をドレイン領域とし、下部のストレノード部(キャパシタ電極)と一体をなす第1導電層6の上部をソース領域とし、p型エピタキシャル層 Incidentally, as a configuration operation MOS transistor of the memory cell of this structure, the second conductive layer 3 serves as a word line for controlling the first output and input to the gate electrode, a drain and a drain 24 which serves as a bit line for performing input and output and regions, and the upper portion of the first conductive layer 6 which forms an integral with the lower portion of the stress node portion (capacitor electrode) and the source region, p-type epitaxial layer
22の側面をチャネル領域としたもので、信号の出入力は通常のダイナミック型記憶装置と全く同じである。 22 side of which was a channel region, the signal output of the input is exactly the same as conventional dynamic memory device.

〔発明が解決しようとする課題〕 [Problems that the Invention is to Solve]

この構造による半導体装置では,MOSトランジスタの主要部、即ちソース,ドレイン,チャネル等をトレンチの外側に形成する。 In the semiconductor device according to this structure, the main portion of the MOS transistor, namely source, drain, a channel or the like is formed on the outside of the trench. 即ち、MOSトランジスタの活性層を基板側に形成するため、選択酸化膜等の素子分離が必要となる。 That is, to form an active layer of the MOS transistor on the substrate side, it is necessary to isolation of such selective oxide film. メモリセル面積に占める素子分離領域の面積は決して小さいとは言えず、無理に分離幅を小さくした場合、分離特性の悪化から素子としての能力及び信頼性が著しく損なわれる恐れもあり、素子分離領域の縮小には限界があるという問題点があった。 Area of ​​the element isolation region occupied in the memory cell area can not be said to be never less, forcibly if the separation width is made small, there is a possibility that capability and reliability is significantly impaired as an element from the deterioration in separation characteristics, the isolation region the reduction there is a problem in that there is a limit.

この発明は上記のような問題点を解消するためになされたもので、素子分離のための手段を特に講じなくとも、おのずから分離されている活性層を形成するようにし、セル面積の縮小、ひいては高集積化を達成することのできるダイナミック型記憶装置を得ることを目的とする。 The present invention has been made to solve the above problems, without particularly taking steps for the isolation, so as to form an active layer that is naturally separated, reduction of cell area, thus and to obtain a dynamic memory device capable of achieving high integration.

〔課題を解決するための手段〕 [Means for Solving the Problems]

この発明に係る半導体装置の製造方法は、半導体基板上に第1絶縁層,第2導電層,第2絶縁層を形成し、これら三層及び半導体基板を同時にパターニングし、所定の孔もしくは溝を形成する工程と、前記孔もしくは溝の側面を導電型に変えるための不純物注入を行い、この側面に誘電膜及び第1導電層を順に形成した後、それぞれの最上端が前記第1絶縁膜の上面と下面の中間の高さにくるまで前記誘電膜及び第1導電層を後退させる工程と、前記第2導電層及び第2絶縁層をダイナミック型記憶装置にいうワード線にパターニングする工程と、前記第2導電層の露出面にゲート絶縁膜としての絶縁膜を形成し、さらに前記孔もしくは溝の内部に活性層を埋め込み、前記ゲート絶縁膜を上下から挟んで前記第1絶縁層及び第2絶縁層に接す The method of manufacturing a semiconductor device according to the present invention, the first insulating layer on a semiconductor substrate, the second conductive layer, the second insulating layer is formed and patterned these three layers and the semiconductor substrate at the same time, a predetermined hole or groove forming, an impurity is implanted to alter the side surface of the hole or groove in the conductivity type, in this aspect after forming the dielectric layer and the first conductive layer in this order, each of the uppermost of the first insulating film a step of retracting the dielectric layer and the first conductive layer until the height of the upper surface and lower surface of the intermediate, a step of patterning the word line to say the second conductive layer and the second insulating layer in the dynamic memory device, forming an insulating film as a gate insulating film on the exposed surface of the second conductive layer, further wherein the hole or buried active layer in the trench, the gate insulating said first insulating layer film sandwich from above and below and the second Sessu in the insulating layer ごく近傍の前記活性層だけに不純物を拡散させることで一対のリング状の不純物拡散層を形成し、該2つのリング状不純物拡散層のうち下側に位置するリング状不純物拡散層の下端を上記第1導電層に接続する工程と、前記第2絶縁層の上面に第3絶縁層を形成した後、前記不純物拡散層の上端が露出するまで第3絶縁層を後退させ、その上にダイナミック型記憶装置にいうビット線となる第3導電層を配し、これを上記2つのリング状不純物拡散層のうち上側に位置するリング状不純物拡散層の上端と接続し、パターニングする工程とを含むものである。 Forming a very the active layer only to a pair of ring-shaped impurity diffusion layer by diffusing impurities in the vicinity of, the lower end of the ring-shaped impurity diffused layer located on the lower side of the two ring-shaped impurity diffusion layer a step of connecting the first conductive layer, wherein the upper surface of the second insulating layer after forming the third insulating layer, retracts the third insulating layer to the upper end of the impurity diffusion layer is exposed, dynamic thereon disposing a third conductive layer serving as a bit line referred to in the storage device, which is connected to the upper end of the ring-shaped impurity diffusion layer on the upper side of the two ring-shaped impurity diffusion layer, in which a step of patterning .

〔作用〕 [Action]

この発明においては、半導体基板上に第1絶縁層,第2導電層,第2絶縁層を形成し、これら三層及び半導体基板を同時にパターニングし、所定の孔もしくは溝を形成する工程と、前記孔もしくは溝の側面を導電型に変えるための不純物注入を行い、この側面に誘電膜及び第1 In the present invention, the first insulating layer on a semiconductor substrate, the second conductive layer, forming a second insulating layer, and patterning these three layers and the semiconductor substrate at the same time, forming a predetermined hole or groove, said perform impurity implantation for changing the side of the hole or groove in the conductivity type, a dielectric layer and the first to this aspect
導電層を順に形成した後、それぞれの最上端が前記第1 After forming the conductive layer in this order, wherein each of the uppermost first
絶縁膜の上面と下面の中間の高さにくるまで前記誘電膜及び第1導電層を後退させる工程と、前記第2導電層及び第2絶縁層をダイナミック型記憶装置にいうワード線にパターニングする工程と、前記第2導電層の露出面にゲート絶縁膜としての絶縁膜を形成し、さらに前記孔もしくは溝の内部に活性層を埋め込み、前記ゲート絶縁膜を上下から挟んで前記第1絶縁層及び第2絶縁層に接するごく近傍の前記活性層だけに不純物を拡散させることで一対のリング状の不純物拡散層を形成し、該2つのリング状不純物拡散層のうち下側に位置するリング状不純物拡散層の下端を上記第1導電層に接続する工程と、前記第2絶縁層の上面に第3絶縁層を形成した後、前記不純物拡散層の上端が露出するまで第3絶縁層を後退させ、その上にダイナ Patterning the word lines say a step of retracting the dielectric layer and the first conductive layer until the top surface and the bottom surface of the mid-height of the insulating film, the second conductive layer and the second insulating layer in the dynamic memory device step and, an insulating film as a gate insulating film on the exposed surface of the second conductive layer, further buried active layer inside the hole or groove, said first insulating layer across the gate insulating film from the upper and lower and second to form a pair of ring-shaped impurity diffusion layer at only by diffusing the active layer only impurity near in contact with the insulating layer, a ring-shaped located on the lower side of the two ring-shaped impurity diffusion layer retracting the step of connecting the lower end of the impurity diffusion layer on the first conductive layer, after forming the third insulating layer on the upper surface of the second insulating layer, the third insulating layer to the upper end of the impurity diffusion layer is exposed then, Dyna on it ック型記憶装置にいうビット線となる第3導電層を配し、これを上記2つのリング状不純物拡散層のうち上側に位置するリング状不純物拡散層の上端と接続し、パターニングする工程とを含むものとしたから、メモリセル面積が小さく高集積化されたダイナミック型記憶装置を容易にかつ制御性よく作製でき、さらに、キャパシタ電極となる第1導電層上に埋め込んだ活性層にリング状に不純物拡散層を形成してトランジスタのソース及びドレインを形成するようにしたから、キャパシタ電極の不純物濃度とソースの不純物濃度をそれぞれ適切に、容易に制御することができる。 Disposing a third conductive layer serving as a bit line referred to click-type memory device, which is connected to the upper end of the ring-shaped impurity diffusion layer on the upper side of the two ring-shaped impurity diffusion layer, and patterning because I is intended to include, a dynamic memory device the memory cell area is small highly integrated easily and good controllability can be prepared, furthermore, the ring-shaped active layer embedded in the first conductive layer serving as a capacitor electrode forming an impurity diffusion layer it is so arranged to form the source and drain of the transistor, the respective appropriately impurity concentration and the impurity concentration of the source of the capacitor electrode can be easily controlled.

〔実施例〕 〔Example〕

以下、この発明の一実施例を図について説明する。 A description is given of a first embodiment of the present invention.

第1図〜第5図は本発明の一実施例による、ダイナミック型記憶装置のメモリセル1セル分の素子の製造工程を示す図であり、各図(a)はその断面図、各図(b) Figure 1-Fig. 5 according to an embodiment of the present invention, is a diagram showing a manufacturing process of memory cells one cell element of a dynamic memory device, each figure (a) is a sectional view thereof, the diagram ( b)
は斜視図である。 It is a perspective view. これら図において、1は基板、2は第1絶縁層、3は第2導電層、4は第2絶縁層、5は誘電膜、6は第1導電層、7は第1不純物層、8はゲート絶縁膜、9は活性層、9aはドレイン領域、9bはソース領域、9cは第2不純物層、10は第3導電層、11は第3絶縁層、である。 In these figures, 1 denotes a substrate, 2 a first dielectric layer, a second conductive layer 3, the second insulating layer 4, the dielectric layer 5, the first conductive layer 6, the first impurity layer 7, 8 a gate insulating film, 9 active layers, 9a drain region, 9b is the source region, 9c and the second impurity layer, the third conductive layer 10, 11 denotes a third insulating layer.

次に、この実施例のダイナミック型記憶装置のメモリセル1セル分の素子の製造方法について述べる。 Next, the process for producing the dynamic memory device of the memory cells one cell element in this embodiment.

まず、第1図において、Si基板1上にプラズマCVD等の方法により、下から順にヒ素,リン等のn型不純物を含むSi酸化膜等の第1絶縁層2,ヒ素,リン等のn型不純物を含むポリシリコン等の第2導電層3,ヒ素,リン等のn型不純物を含むSi酸化膜等の第2絶縁層4を積層せさ、フォトレジストでパターニングの後、ドライエッチング法により円筒状の孔、即ちトレンチを形成する。 First, in FIG. 1, by a method such as plasma CVD on the Si substrate 1, arsenic in this order from the bottom, the first insulating layer 2 of Si oxide film containing n-type impurities such as phosphorus, arsenic, n-type such as phosphorus second conductive layer 3 such as polysilicon containing an impurity, arsenic, second insulating layer 4 laminated was of a Si oxide film or the like containing an n-type impurity such as phosphorus, after patterning with photoresist, cylindrical by dry etching Jo holes, i.e. to form a trench.

次に第2図(b)に示すように、フォトレジストでワード線をパターニングした後、ドライエッチング法により第2絶縁層4,及び第2導電層3のみを配線として加工する。 Then, as shown in FIG. 2 (b), after patterning the word lines in the photoresist is processed second insulating layer 4, and only the second conductive layer 3 as a wiring by dry etching.

次に第3図において、イオン注入法により前記トレンチ内表面にn型の第1不純物層7を形成した後、Si窒化膜,Si酸化膜等の薄い誘電膜5を堆積させ、さらにその表面にヒ素,リン等のn型不純物を含むポリシリコン等の第1導電層6を堆積させ、前記誘電膜5及び第1導電層6をドライエッチング法及びウエットエッチ法により加工し、前記誘電膜5の露出面の位置と、前記第1導電層6の露出面の最も高い部分の位置がともに第1絶縁層2の中央付近にするようにする。 Next, in FIG. 3, after forming the first impurity layer 7 of n-type in the trench surface by ion implantation, Si nitride film, is deposited a thin dielectric film 5 of such as Si oxide film, further on its surface arsenic, is deposited first conductive layer 6 such as polysilicon containing an n-type impurity such as phosphorus, the dielectric film 5 and the first conductive layer 6 is processed by dry etching and wet etching method, the dielectric film 5 the position of the exposed surface, the position of the uppermost portion of the exposed surface of the first conductive layer 6 are both to be the first near the center of the insulating layer 2.

次に、第4図において、第2導電層3の前記孔の内側面を熱酸化法等によりゲート絶縁膜8とし、この時に同時に酸化された第1導電層6の表面をドライエッチング法により選択的に除去した後、プラズマCVD法等でヒ素,リン等のn型不純物を含むポリシリコン等の活性層9を堆積させ、イオン注入法により表面にn型の第2不純物層9cを形成し、フォトレジストで前記トレンチ開口部を覆うようパターニングし、ドライエッチング法で、 Next, in FIG. 4, the inner surface of the hole of the second conductive layer 3 and the gate insulating film 8 by thermal oxidation or the like, selects a surface of the first conductive layer 6 which is simultaneously oxidized at this time by dry etching after removal, arsenic by plasma CVD method or the like, is deposited active layer 9 of polysilicon containing an n-type impurity such as phosphorus, a second impurity layer 9c of n-type is formed on the surface by ion implantation, patterning so that a photoresist covers the trench opening, a dry etching method,
第4図(b)に示すように活性層9のみを加工し、適当な熱処理により前記活性層9及び基板1に前記第1絶縁層2及び第2絶縁層4よりn型不純物を拡散させ、ドレイン領域9a,ソース領域9b,及び第1不純物層7及び第2 Figure 4 (b) to process the only active layer 9, as shown, appropriate the active layer 9 and the n-type impurity than the first insulating layer 2 and the second insulating layer 4 in the substrate 1 is diffused by heat treatment, drain region 9a, the source regions 9b, and the first impurity layer 7 and the second
不純物層9cを形成する。 Forming an impurity layer 9c.

最後に、第5図において、プラズマCVD法等によりSi Finally, in FIG. 5, Si by plasma CVD method or the like
酸化膜、Si窒化膜等の第3絶縁層11を堆積し、ドライエッチング法等により前記活性層9の上端面が露出するようにした後、全面に窒化Ti,Al等の第3導電層10を堆積させ、フォトレジストでビット線をパターニングし、ドライエッチング法により前記第3導電層10のみを配線として加工するものである。 Oxide film, depositing a third insulating layer 11 such as Si nitride film, after the upper surface of the active layer 9 was made to expose by a dry etching method or the like, the third conductive layer 10 on the entire surface nitriding Ti, such as Al the depositing, patterning the bit lines in a photoresist, is to process only the third conductive layer 10 as a wiring by dry etching.

ここで、この本実施例の素子構造は、まずトランジスタ部は活性層9内に作られたドレイン領域9a,ソース領域9b、その間のチャネル領域,ゲート電極としての第2 Here, the element structure of this embodiment, first transistor section drain region 9a made in the active layer 9, the source region 9b, between the channel region, the second as the gate electrode
導電層3,ゲート絶縁膜8を構成要素とし、キャパシタ部は一方の電極を第1不純物層7、もう一方の電極を第1 Conductive layer 3, as a component of the gate insulating film 8, the first impurity layer 7 capacitor unit one electrode, the other electrode first
導電層6、その間の誘電膜5を構成要素としており、キャパシタとトランジスタはソース領域9bの下端面と第1 Conductive layer 6, and as a component of the dielectric film 5 therebetween, the lower end surface and the first capacitor and a transistor source region 9b
導電層6の上端面で接続され、ワード線は第2導電層3 It is connected by the upper end surface of the conductive layer 6, the word line and the second conductive layer 3
自体が配線をなし、ビット線は前記活性層9の上端面すなわち第2不純物層9cを介してトランジスタと接続された第3導電層10が配線をなすというものである。 Itself forms the wiring, the bit line is that the third conductive layer 10 connected to the transistor through the upper surface or second impurity layer 9c of the active layer 9 forms a wiring.

このような本実施例では、従来のトレンチキャパシタ直上の孔または溝の内側にトランジスタの活性層を作り込んだので、従来のように孔または溝の外側を活性層とする場合に比べ、メモリセル面積を小さくすることが可能であり、高集積化が実現可能となる。 In such embodiment, since elaborate make a hole or inside the active layer of the transistor of the groove just above conventional trench capacitors, compared with the case where the outer conventional hole or groove as the active layer, the memory cells it is possible to reduce the area, high integration can be realized.

また、この実施例のトランジスタ構造では、ゲート長は堆積する膜厚で決定されるため、加工制御が容易であり、またゲート幅は孔の内周で決定されるため、見かけよりもゲート幅は大きく、電流駆動能力の高いトランジスタが得られる。 Further, the transistor structure of this embodiment, since the gate length is determined by the film thickness to be deposited, is easy to process control, and because the gate width which is determined by the inner periphery of the hole, the gate width than the apparent large transistor with high current drivability is obtained.

〔発明の効果〕 〔Effect of the invention〕

以上のように、この発明によれば、従来のトレンチキャパシタ直上の孔または溝の内側にトランジスタの活性層を作り込むことにより、従来孔または溝の外側を活性層とする場合に比べ、メモリセル面積を小さくすることが可能であり、ダイナミック型記憶装置の高集積化を実現することが可能となる。 As described above, according to the present invention, by the inside of the hole or the groove just above conventional trench capacitors fabricated active layer of the transistor, compared with the case of the outside of the conventional holes or grooves with the active layer, the memory cells it is possible to reduce the area, it is possible to realize a high integration of a dynamic memory device.

また、この発明のトランジスタ構造では、ゲート長は堆積する膜厚で決定されるため、加工制御が容易であり、またゲート幅は孔の内周で決定されるため、見かけよりもゲート幅は大きく、電流駆動能力の高いトランジスタが得られるなどの効果がある。 Further, the transistor structure of the present invention, since the gate length is determined by the film thickness to be deposited, is easy to process control, and because the gate width which is determined by the inner periphery of the hole, the gate width is greater than the apparent , the effect of such a high current driving capability transistor is obtained.

さらに、この発明によれば、トランジスタのソース及びドレインをキャパシタ電極となる第1導電層上に埋め込んだ活性層にリング状に形成した不純物拡散層で構成したから、製造時に容易にキャパシタ電極の不純物濃度とソースの不純物濃度をそれぞれ適切に制御することができる効果がある。 Further, according to the present invention, since it is constituted by an impurity diffusion layer of the source and drain are formed in a ring shape into the active layer embedded in the first conductive layer serving as a capacitor electrode of the transistor, the readily capacitor electrodes during manufacturing impurities there is an effect that can appropriately control each impurity concentration of the concentration and the source.

【図面の簡単な説明】 第1図ないし第5図はこの発明の一実施例による半導体装置の製造工程を示す図、第6図は従来の半導体装置を示す断面構造図である。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 through Figure 5 shows a manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 6 is a sectional view showing a conventional semiconductor device. 1……基板、2……第1絶縁層、3……第2導電層、4 1 ...... substrate, 2 ...... first insulating layer, 3 ...... second conductive layer, 4
……第2絶縁層、5……誘電膜、6……第1導電層、7 ...... second insulating layer, 5 ...... dielectric film, 6 ...... first conductive layer, 7
……第1不純物層、8……ゲート絶縁膜、9……活性層、9a……ドレイン領域、9b……ソース領域、9c……第2不純物層、10……第3導電層、11……第3絶縁層、。 ...... first impurity layer, 8 ...... gate insulating film, 9 ...... active layer, 9a ...... drain region, 9b ...... source region, 9c ...... second impurity layer, 10 ...... third conductive layer, 11 ... ... the third insulating layer,. なお図中同一符号は同一又は相当部分を示す。 Note figure designate the same or corresponding parts.

Claims (1)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】半導体基板上に第1絶縁層,第2導電層, 1. A first insulating layer on a semiconductor substrate, the second conductive layer,
    第2絶縁層を形成し、これら三層及び半導体基板を同時にパターニングし、所定の孔もしくは溝を形成する工程と、 前記孔もしくは溝の側面を導電型に変えるための不純物注入を行い、この側面に誘電膜及び第1導電層を順に形成した後、それぞれの最上端が前記第1絶縁膜の上面と下面の中間の高さにくるまで前記誘電膜及び第1導電層を後退させる工程と、 前記第2導電層及び第2絶縁層をダイナミック型記憶装置にいうワード線にパターニングする工程と、 前記第2導電層の露出面にゲート絶縁膜としての絶縁膜を形成し、さらに前記孔もしくは溝の内部に活性層を埋め込み、前記ゲート絶縁膜を上下から挟んで前記第1絶縁層及び第2絶縁層に接するごく近傍の前記活性層だけに不純物を拡散させることで一対のリング状に不純物 Forming a second insulating layer, and patterning these three layers and the semiconductor substrate at the same time, it performs a step of forming a predetermined hole or groove, an impurity implantation for changing the side of the hole or groove in the conductivity type, the side surface a step after forming the dielectric layer and the first conductive layer in this order, to retract the dielectric layer and the first conductive layer to the respective uppermost end comes to mid-height upper and lower surfaces of the first insulating film, wherein the step of patterning the second conductive layer and the second insulating layer to the word line referred to dynamic storage device, an insulating film as a gate insulating film on the exposed surface of the second conductive layer, further wherein the holes or grooves internal the embedded active layer, the gate insulating film an impurity into a pair of ring-shaped simply by diffusing an impurity into sandwich from above and below the active layer of the close proximity in contact with the first insulating layer and the second insulating layer 散層を形成し、該2つのリング状不純物拡散層のうち下側に位置するリング状不純物拡散層の下端を上記第1導電層に接続する工程と、 前記第2絶縁層の上面に第3絶縁層を形成した後、前記2つのリング状不純物拡散層のうち上側に位置するリング状不純物拡散層の上端が露出するまで第3絶縁層を後退させ、その上にダイナミック型記憶装置にいうビット線となる第3導電層を配し、これを前記2つのリング状不純物拡散層のうち上側に位置するリング状不純物拡散層の上端と接続し、パターニングする工程とを含むことを特徴とする半導体装置の製造方法。 The dispersion layer is formed, a step of the lower end of the ring-shaped impurity diffused layer located on the lower side of the two ring-shaped impurity diffusion layer connected to the first conductive layer, the third on the upper surface of the second insulating layer after forming the insulating layer, retracts the third insulating layer to the upper end of the ring-shaped impurity diffusion layer on the upper side of said two ring-shaped impurity diffusion layer is exposed, bits referred to dynamic storage device thereon disposing a third conductive layer serving as a line, which connects the upper end of the ring-shaped impurity diffusion layer on the upper side of said two ring-shaped impurity diffusion layers, characterized by comprising a step of patterning the semiconductor manufacturing method of the device.
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