JPH0744274B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0744274B2 JPH0744274B2 JP61290567A JP29056786A JPH0744274B2 JP H0744274 B2 JPH0744274 B2 JP H0744274B2 JP 61290567 A JP61290567 A JP 61290567A JP 29056786 A JP29056786 A JP 29056786A JP H0744274 B2 JPH0744274 B2 JP H0744274B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- gate
- insulating film
- diffusion region
- electrode material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 16
- 239000007772 electrode material Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 12
- 230000001681 protective effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 8
- 239000012535 impurity Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） 本発明は半導体装置及びその製造方法に関するもので、
特にMIS（Metal Insulator Semiconductor）型半導体装
置に使用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device and a method of manufacturing the same,
In particular, it is used for a MIS (Metal Insulator Semiconductor) type semiconductor device.
（従来の技術） 半導体基板に設けた溝の側壁に２つのゲート領域を形成
した半導体装置の一例として、Texas Instruments社の
W.F.RichardsonらによるTrench Transistor Cross−Poi
nt DRAM cellを挙げることができる（1985 IEDM Techni
cal Digest,P714）。(Prior Art) As an example of a semiconductor device in which two gate regions are formed on the side wall of a groove provided in a semiconductor substrate, Texas Instruments
Trench Transistor Cross-Poi by WR Richardson et al.
nt DRAM cell can be mentioned (1985 IEDM Techni
cal Digest, P714).
このセルでは、１つの溝の下側を第１ゲートキャパシタ
に使用し、溝の上部の側面を転送ゲート（第２ゲート）
に使用することにより、セルの微細化を可能にしたもの
である。この装置を得るには、まずP+基板31上にＰ型層
32をエピタキシャル形成し、表面に素子分離33と、ビッ
ト線を兼ねるn+拡散層34を形成し、半導体基板にp+基板
31に達するまで溝35を形成し、表面に第１ゲート酸化膜
36を形成する（第６図（Ａ））。次にn+多結晶シリコン
37を形成して溝35の上部の多結晶シリコンをウェット方
式でエッチングし、下部のみにn+多結晶シリコン37を残
し、ゲート酸化膜36を等方的にエッチングする（第６図
（Ｂ））。次にゲート酸化膜の膜厚の２倍以上のアンド
ープ多結晶シリコンを堆積し、これを等方的にエッチン
グして第６図（Ｂ）のアンダーカット部38のみに多結晶
シリコンを残す（第６図（Ｃ））。次いでスチーム酸化
により、転送ゲート領域となる溝上部の側壁と、多結晶
シリコン上を酸化し、ワード線となるn+多結晶シリコン
層39をデポパターニングする。第６図（Ｃ）のリファイ
ルドコンタクト部40においては、埋め込まれたn+多結晶
シリコンから不純物が基板側に拡散され、ソースあるい
はドレイン領域となるn+拡散層41が形成される（第６図
（Ｄ））。この場合ドレインまたはソースはn+層34で、
42がチャネル領域である。In this cell, the lower side of one groove is used as a first gate capacitor, and the side surface above the groove is used as a transfer gate (second gate).
It is possible to miniaturize the cell by using it. In order to obtain this device, first, a P-type layer is formed on the P + substrate 31.
32 was epitaxially formed, a device isolation 33 on the surface, to form an n + diffusion layer 34 serving also as a bit line, p + substrate to the semiconductor substrate
Groove 35 is formed until it reaches 31, and the first gate oxide film is formed on the surface.
36 is formed (FIG. 6 (A)). Then n + polycrystalline silicon
37 is formed, and the polycrystalline silicon on the upper portion of the groove 35 is etched by a wet method, the n + polycrystalline silicon 37 is left only on the lower portion, and the gate oxide film 36 is isotropically etched (FIG. 6 (B)). ). Next, undoped polycrystalline silicon having a thickness not less than twice the thickness of the gate oxide film is deposited and isotropically etched to leave the polycrystalline silicon only in the undercut portion 38 of FIG. 6B (see FIG. 6 (C)). Next, by steam oxidation, the side wall of the upper portion of the groove to be the transfer gate region and the polycrystalline silicon are oxidized, and the n + polycrystalline silicon layer 39 to be the word line is deposited and patterned. In the refiled contact portion 40 of FIG. 6 (C), impurities are diffused from the embedded n + polycrystal silicon to the substrate side, and an n + diffusion layer 41 to be a source or drain region is formed (see FIG. 6 (D). In this case the drain or source is the n + layer 34,
42 is the channel region.
第７図は第６図の等価回路で、第１ゲートのキャパシタ
43はポリシリコン層37とp+基板31で形成され、第２ゲー
ト（転送ゲート）44はn+層34,41で形成される。FIG. 7 is an equivalent circuit of FIG. 6, showing the capacitor of the first gate.
43 is formed of the polysilicon layer 37 and the p + substrate 31, and the second gate (transfer gate) 44 is formed of the n + layers 34 and 41.
（発明が解決しようとする問題点） 従来技術の半導体装置においては、半導体基板に設けら
れた側面に段差のない溝35の側面に第１ゲート43、第２
ゲート44の２つのMISゲート領域をもつ構造になってい
る。このような場合、第２ゲート（転送ゲート）領域は
第６図（Ｂ）に見るように、埋め込んだポリシリコンの
エッチバックや第６図（Ｃ）のように半導体基板に直に
接触したポリシリコンのエッチングなどで、トランジス
タ形成予定部（特にその溝の側壁）はダメージを受けや
すい。そのため従来においてはダメージの入りにくいウ
ェットエッチングを行なっているが、ウェットエッチン
グは気泡の付着などによりエッチングが阻害されやす
く、微細化に向かない欠点がある。従って第２ゲート領
域を、第１ゲート形成に必要なプロセスから保護しにく
いのが、従来の溝構成の半導体装置の最大の欠点であ
る。(Problems to be Solved by the Invention) In the conventional semiconductor device, the first gate 43 and the second gate are provided on the side surface of the groove 35 having no step on the side surface provided on the semiconductor substrate.
The structure has two MIS gate regions of the gate 44. In such a case, as shown in FIG. 6B, the second gate (transfer gate) region is formed by etching back the buried polysilicon, or by directly contacting the semiconductor substrate as shown in FIG. 6C. Due to etching of silicon or the like, the portion where the transistor is to be formed (particularly the side wall of the groove) is easily damaged. Therefore, in the past, wet etching, which is less likely to be damaged, is performed, but wet etching has a drawback that it is not suitable for miniaturization because the etching is likely to be hindered by the adhesion of bubbles. Therefore, it is difficult to protect the second gate region from the process required for forming the first gate, which is the greatest drawback of the conventional semiconductor device having the groove structure.
本発明は上記実情に鑑みてなされたもので、半導体基板
に設けられた溝の側部に２つ以上のゲート領域を設ける
半導体装置において、各ゲートプロセスを独立に行ない
やすい半導体装置及びその製造方法を提供しようとする
ものである。The present invention has been made in view of the above circumstances, and in a semiconductor device in which two or more gate regions are provided on the side portions of a groove provided in a semiconductor substrate, a semiconductor device in which each gate process is easily performed independently and a manufacturing method thereof. Is to provide.
（問題点を解決するための手段と作用） 本発明は、半導体基板に設けられた溝の側面に少くとも
１段以上の段差を設け、この段差の上と下にそれぞれ別
のゲート領域を設けるが、下のゲート領域を設けるとき
には、段差を利用しかつ該段差の上の溝の側面を保護し
た状態で行なうことにより、該側面にダメージを受けな
いようにしたものである。(Means and Actions for Solving Problems) In the present invention, at least one step is provided on the side surface of the groove provided in the semiconductor substrate, and different gate regions are provided above and below this step, respectively. When the lower gate region is provided, the step is used and the side surface of the groove above the step is protected so that the side surface is not damaged.
（実施例） 以下図面を参照して本発明の一実施例を説明する。第１
図は同実施例の断面図で、51はｐ型基板、52は第１のゲ
ート電極、53は第２のゲート電極、54〜56はソースまた
はドレインとなるn+領域である。この第１図は、ｐ基板
51の溝57に設けられた１段の段差の上側と下側にそれぞ
れ第１ゲート領域（MIS領域）と第２ゲート領域（MIS領
域）を形成したものである。この図では溝の両側を並列
に使用しているが、独立した回路として使用してもよ
い。第２図は第１図の等価回路であり、このような直列
トランジスタはNANDゲートなどに応用が可能である。こ
のような回路を平面上に構成しようとすれば、かなりの
面積が必要となる。Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
The figure is a cross-sectional view of the same embodiment, in which 51 is a p-type substrate, 52 is a first gate electrode, 53 is a second gate electrode, and 54 to 56 are n + regions serving as sources or drains. This Figure 1 shows the p substrate
The first gate region (MIS region) and the second gate region (MIS region) are formed on the upper side and the lower side of the one step provided in the groove 57 of 51, respectively. Although both sides of the groove are used in parallel in this figure, they may be used as independent circuits. FIG. 2 is an equivalent circuit of FIG. 1, and such a series transistor can be applied to a NAND gate or the like. If it is attempted to construct such a circuit on a plane, a considerable area is required.
第３図は第１図，第２図の構成の具体的な製造方法の一
例である。まず第３図（ａ）のように第１のマスク材１
をパターニングした後、ｐ型半導体基板３をエッチング
して溝をつくり、第２のマスク材２を堆積する。Ｏは予
め基板３につくられたn+層で、上記溝はこのn+層Ｏを貫
くように形成される。次に第３図（ｂ）に示すように第
２のマスク材２を異方性エッチングして溝の側壁のみに
残した後、これをマスクとして基板３を異方性エッチン
グすると、基板３の溝に１段の段差ができ、この段差の
下側の内面にゲート絶縁膜４を形成した後、第１のゲー
ト電極材料５を堆積する。次に第３図（Ｃ）に示すよう
に第１のゲート電極材料５を異方性エッチングし、主に
段差の底部にのみ第１のゲート電極材料５を残す。その
際第１のゲート電極材料で外部に配線するために、配線
部のみレジストでカバーしてもよい。次に溝の底部及び
段差の角部に、例えばイオン注入やリン拡散によりソー
スまたはドレインとなるn+拡散層21,22を形成する。次
にゲートエッジを後酸化した後、層間絶縁膜６を形成す
る。次いで第３図（ｄ）に示すように第１のマスク材
１、第２のマスク材２を除去した後、第２ゲート絶縁膜
７を形成し、第２ゲート電極材料８を堆積し、異方性エ
ッチバックにより主に段差の上にのみ第２ゲート電極材
料８を残す。これもレジストにより配線部は残すことが
できる。溝の底部のn+層11へのコンタクトは層間絶縁膜
６の形成後、通常の写真蝕刻工程を用いて形成すればよ
い。FIG. 3 shows an example of a specific manufacturing method for the structure shown in FIGS. First, as shown in FIG. 3A, the first mask material 1
After patterning, the p-type semiconductor substrate 3 is etched to form a groove, and the second mask material 2 is deposited. O is an n + layer previously formed on the substrate 3, and the groove is formed so as to penetrate the n + layer O. Next, as shown in FIG. 3B, the second mask material 2 is anisotropically etched to leave only the side walls of the groove, and the substrate 3 is anisotropically etched using this as a mask. One step is formed in the groove, the gate insulating film 4 is formed on the inner surface below this step, and then the first gate electrode material 5 is deposited. Next, as shown in FIG. 3 (C), the first gate electrode material 5 is anisotropically etched to leave the first gate electrode material 5 mainly only at the bottom of the step. At this time, the wiring may be covered only with the resist in order to connect the first gate electrode material to the outside. Next, at the bottom of the groove and the corner of the step, n + diffusion layers 21 and 22 to be a source or a drain are formed by, for example, ion implantation or phosphorus diffusion. Next, after the gate edge is post-oxidized, the interlayer insulating film 6 is formed. Next, as shown in FIG. 3 (d), after removing the first mask material 1 and the second mask material 2, a second gate insulating film 7 is formed, a second gate electrode material 8 is deposited, and The second gate electrode material 8 is left mainly only on the step due to the anisotropic etchback. The resist can also leave the wiring part. The contact to the n + layer 11 at the bottom of the groove may be formed by using a normal photolithography process after forming the interlayer insulating film 6.
第３図のものにあっては、段差上の第２のマスク材２を
マスクとして段差下の第１ゲートプロセスを行なうか
ら、特に段差下に溝を設けるときマスク合わせ余裕が不
要であり、また段差の上側の溝の壁面はマスク材２で覆
われたまゝ第１ゲートプロセスが行なわれるので、段差
の上側の溝の壁面にダメージを受けないものである。In the case of FIG. 3, since the first gate process under the step is performed using the second mask material 2 on the step as a mask, a mask alignment margin is not necessary especially when a groove is provided under the step. Since the first gate process is performed until the wall surface of the groove above the step is covered with the mask material 2, the wall surface of the groove above the step is not damaged.
第４図は本発明の他の実施例で、従来例で用いたものと
同様のDRAMセルに応用したものである。図中４′は第１
ゲート絶縁膜、５′は第１ゲート電極材料、７′は第２
ゲート絶縁膜、８′は第２ゲート電極材料で、この第４
図の等価回路は第７図の場合と同じである。またこの第
４図の利点も第３図の場合と同じで、段差の上側の溝の
壁面に設けられた保護材をマスクとして段差の下側の第
１ゲートプロセスを行なうから、特に段差下に溝を設け
るときマスク合わせ余裕が不要であり、また段差の上側
の溝の壁面は上記保護材で覆われたまゝ第１ゲートプロ
セスが行なわれるから、段差の上側の溝の壁面にダメー
ジを受けないものである。FIG. 4 shows another embodiment of the present invention, which is applied to a DRAM cell similar to that used in the conventional example. 4'in the figure is the first
Gate insulating film, 5'is the first gate electrode material, 7'is the second
The gate insulating film, 8'is the second gate electrode material,
The equivalent circuit in the figure is the same as in FIG. The advantage of FIG. 4 is also the same as that of FIG. 3, and since the first gate process on the lower side of the step is performed using the protective material provided on the wall surface of the groove on the upper side of the step as a mask, When the groove is provided, no mask alignment margin is required, and the wall surface of the groove above the step is covered with the above-mentioned protective material, and the first gate process is performed, so that the wall surface of the groove above the step is not damaged. It is a thing.
第５図は本発明の更に他の実施例で、第５図（ａ）
（ｂ）はそれぞれ第５図（ｃ）のパターン平面図のＡ−
Ａ′及びＢ−Ｂ′線に沿う断面図である。本構造はDRAM
セルである。第５図（ｃ）の２点鎖線で示した領域が１
セル分である。動作について説明すると、書き込みはビ
ット線10に与えられた電位が基板と逆導電型の不純物領
域16に与えられる。11がワード線になっている。第５図
（ｃ）では、２点鎖線で囲まれた１セル分の領域がＢ−
Ｂ′方向では接近して配置され、Ａ−Ａ′方向では離れ
て配置されているので、Ｂ−Ｂ′方向にワード線11がつ
ながり（第５図（ｂ）参照）、Ａ−Ａ′方向にはワード
線11の厚みの２倍以上分離された構造となる（第５図
（ａ）参照）。転送ゲート酸化膜15の接している半導体
基板側がチャネル領域となって電荷を基板と逆導電型の
不純物領域17に伝える。キャパシタ電極12を一方の電
極、不純物領域17を他方の電極、第１ゲート酸化膜14を
誘導体とするMISキャパシタに電荷は蓄積される。13は
隣接するセル間を分離するために埋め込まれた素子分離
絶縁膜である。このようなセル構造では、隣接するキャ
パシタの電極17どうしの間に積極的に素子分離領域を設
けないと、キャパシタ電極17の下が反転して電荷がリー
クする可能性が高い。そのため溝の一番底部に素子分離
用の絶縁膜をもつようにしている。即ち溝底部にもう１
段段差を設け、絶縁膜13を埋め込んだものである。この
第５図の等価回路も第７図と同じであり、利点も前記各
実施例の場合と同じである。FIG. 5 shows still another embodiment of the present invention, which is shown in FIG.
(B) is A- of the pattern plan view of FIG. 5 (c), respectively.
It is sectional drawing which follows the A'and BB 'line. This structure is DRAM
It is a cell. The area indicated by the chain double-dashed line in FIG. 5 (c) is 1
It is a cell. In operation, the potential applied to the bit line 10 for writing is applied to the impurity region 16 of the conductivity type opposite to that of the substrate. 11 is a word line. In FIG. 5 (c), a region for one cell surrounded by a two-dot chain line is B-
The word lines 11 are connected to each other in the BB 'direction (see FIG. 5B) because they are arranged close to each other in the B'direction and separated from each other in the AA' direction (see FIG. 5B). Has a structure in which it is separated by more than twice the thickness of the word line 11 (see FIG. 5 (a)). The semiconductor substrate side in contact with the transfer gate oxide film 15 serves as a channel region to transfer charges to the impurity region 17 having a conductivity type opposite to that of the substrate. Electric charges are accumulated in the MIS capacitor having the capacitor electrode 12 as one electrode, the impurity region 17 as the other electrode, and the first gate oxide film 14 as a dielectric. Reference numeral 13 is an element isolation insulating film embedded to separate adjacent cells. In such a cell structure, unless an element isolation region is positively provided between the electrodes 17 of adjacent capacitors, there is a high possibility that the bottom of the capacitor electrode 17 will be inverted and electric charges will leak. Therefore, an insulating film for element isolation is provided at the bottom of the groove. That is, another one on the bottom of the groove
A step is provided and the insulating film 13 is embedded. The equivalent circuit of FIG. 5 is also the same as that of FIG. 7, and the advantages are the same as those of the above-described embodiments.
本発明の半導体装置においては、各ゲート領域の平面上
の幅はたかだかゲート電極材料の膜厚にすぎない。また
各ゲートは、最初につくった溝の段差から自己整合的に
次々につくることができるので、マスク合わせ余裕がい
らない。一方、デバイスの信頼性に大きな影響を与える
ゲート長は、見かけ上（平面上）のデバイスの大きさを
大きくしなくても長くすることができる。また本発明に
おいては、段差の上側の側面を保護材でカバーした状態
で段差の下側のプロセスが行なえるので、段差の上側の
素子形成予定部はダメージを受けず、プロセスを容易化
できると共に、高歩留、高信頼性が容易に達成できるも
のである。In the semiconductor device of the present invention, the width of each gate region on the plane is at most a film thickness of the gate electrode material. Further, since each gate can be formed one after another in a self-aligned manner from the step difference of the groove initially formed, no mask alignment margin is required. On the other hand, the gate length, which greatly affects the reliability of the device, can be lengthened without increasing the apparent (planar) size of the device. Further, in the present invention, since the process on the lower side of the step can be performed in a state where the side surface on the upper side of the step is covered with the protective material, the element formation planned portion on the upper side of the step is not damaged and the process can be facilitated. The high yield and high reliability can be easily achieved.
第１図は本発明の一実施例の断面図、第２図はその等価
回路図、第３図は本発明の実施例の工程図、第４図，第
５図（ａ）（ｂ）は本発明の異なる実施例の断面図、第
５図（ｃ）は第５図（ａ）（ｂ）のパターン平面図、第
６図、第７図は従来装置の説明図である。 1,2……マスク材、３……半導体基板、4,4′……第１ゲ
ート絶縁膜、5,5′……第１ゲート電極、６……絶縁
膜、7,7′……第２ゲート絶縁膜、8,8′……第２ゲート
電極、10……ビット線、11……ワード線、12……キャパ
シタ電極、13……素子分離絶縁膜、14……キャパシタ絶
縁膜、15……転送ゲート絶縁膜、16,17……基板と逆導
電型の不純物領域。1 is a sectional view of an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram thereof, FIG. 3 is a process drawing of the embodiment of the present invention, and FIGS. 4 and 5 (a) (b) are Sectional views of different embodiments of the present invention, FIG. 5 (c) is a pattern plan view of FIGS. 5 (a) and (b), and FIGS. 6 and 7 are explanatory views of a conventional apparatus. 1,2 ... Mask material, 3 ... Semiconductor substrate, 4,4 '... First gate insulating film, 5,5' ... First gate electrode, 6 ... Insulating film, 7,7 '... 2 gate insulating film, 8, 8 '... second gate electrode, 10 ... bit line, 11 ... word line, 12 ... capacitor electrode, 13 ... element isolation insulating film, 14 ... capacitor insulating film, 15 ...... Transfer gate insulating film, 16,17 …… Impurity region of the opposite conductivity type to the substrate.
Claims (2)
と、 前記第１の溝の側壁に沿う前記半導体基板の表面領域に
設けられた第１の拡散領域と、 前記第１の溝および前記第２の溝の段差部分に設けられ
た第２の拡散領域と、 前記第２の溝の底部に設けられた第３の拡散領域と、 前記第２の溝の内側面に絶縁膜を介して設けられた第１
の電極材料と、 前記第１の溝の内側面に絶縁膜を介して設けられた第２
の電極材料とを具備し、 前記第１の拡散領域、第２の拡散領域および第２の電極
材料により上側のトランジスタが形成され、前記第2,第
３の拡散領域および前記第１の電極材料により下側のト
ランジスタが形成されていることを特徴とする半導体装
置。1. A first groove provided in a semiconductor substrate, a second groove provided with a step at the bottom of the first groove, and a surface of the semiconductor substrate along a sidewall of the first groove. A first diffusion region provided in the region, a second diffusion region provided in a step portion of the first groove and the second groove, and a third diffusion region provided in the bottom of the second groove. And a first diffusion layer provided on the inner surface of the second groove via an insulating film.
Electrode material and a second electrode provided on the inner surface of the first groove via an insulating film.
An electrode material of the above, wherein an upper transistor is formed by the first diffusion region, the second diffusion region and the second electrode material, and the second and third diffusion regions and the first electrode material are formed. A semiconductor device in which a lower transistor is formed by.
設け、 この第１の拡散領域を貫いて第１の溝を形成し、 この第１の溝の側面に設けられた保護膜をマスクとして
前記第１の溝の底部に段差をもって第２の溝を形成し、 この第２の溝の内側面に絶縁膜を介して第１の電極材料
を形成し、 前記第２の溝の底部および段差部分にそれぞれ第2,第３
の拡散領域を形成し、 第１の溝の内側面に絶縁膜を介して第２の電極材料を形
成することにより、 前記第１の拡散領域、前記第２の拡散領域および前記第
２の電極材料からなる上側のトランジスタと、前記第2,
第３の拡散領域および前記第１の電極材料からなる下側
のトランジスタとを設けることを特徴とする半導体装置
の製造方法。2. A first diffusion region is provided in a surface region of a semiconductor substrate, a first groove is formed through the first diffusion region, and a protective film provided on a side surface of the first groove is formed. As a mask, a second groove is formed with a step on the bottom of the first groove, and a first electrode material is formed on the inner side surface of the second groove with an insulating film interposed between the bottom and the bottom of the second groove. And second and third at the step
Of the first diffusion region, the second diffusion region, and the second electrode by forming a second electrode material on the inner surface of the first groove via an insulating film. An upper transistor made of material, and the second,
A method of manufacturing a semiconductor device, comprising providing a third diffusion region and a lower transistor made of the first electrode material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61290567A JPH0744274B2 (en) | 1986-12-08 | 1986-12-08 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61290567A JPH0744274B2 (en) | 1986-12-08 | 1986-12-08 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63143860A JPS63143860A (en) | 1988-06-16 |
| JPH0744274B2 true JPH0744274B2 (en) | 1995-05-15 |
Family
ID=17757693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61290567A Expired - Lifetime JPH0744274B2 (en) | 1986-12-08 | 1986-12-08 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0744274B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04162566A (en) * | 1990-10-25 | 1992-06-08 | Nec Corp | Semiconductor memory device |
| JPH04354159A (en) * | 1991-05-31 | 1992-12-08 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| CN114242777A (en) * | 2022-02-22 | 2022-03-25 | 北京芯可鉴科技有限公司 | LDMOSFET, preparation method, chip and circuit |
| CN114220846A (en) * | 2022-02-22 | 2022-03-22 | 北京芯可鉴科技有限公司 | LDMOSFET, preparation method, chip and circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6122665A (en) * | 1984-07-11 | 1986-01-31 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS6123360A (en) * | 1984-07-12 | 1986-01-31 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory and manufacture of the same |
-
1986
- 1986-12-08 JP JP61290567A patent/JPH0744274B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63143860A (en) | 1988-06-16 |
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