JPH0682797B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0682797B2 JPH0682797B2 JP60282636A JP28263685A JPH0682797B2 JP H0682797 B2 JPH0682797 B2 JP H0682797B2 JP 60282636 A JP60282636 A JP 60282636A JP 28263685 A JP28263685 A JP 28263685A JP H0682797 B2 JPH0682797 B2 JP H0682797B2
- Authority
- JP
- Japan
- Prior art keywords
- trench
- conductivity type
- capacitor
- semiconductor device
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title claims description 9
- 239000003990 capacitor Substances 0.000 claims description 28
- 238000009792 diffusion process Methods 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 230000002265 prevention Effects 0.000 claims description 9
- 238000003860 storage Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 239000005368 silicate glass Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、トレンチキャパシタを有する半導体メモリな
どの半導体装置の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device such as a semiconductor memory having a trench capacitor.
トレンチキャパシタを有する半導体装置においては、キ
ャパシタ相互間のリークを防止することは重要な問題で
ある。In a semiconductor device having a trench capacitor, preventing leakage between capacitors is an important issue.
第２図（ａ）はリーク防止のための従来のトレンチキャ
パシタの構造例を示すもので、例えばキャパシタの電荷
蓄積領域をn-層で構成する場合、Ｐ型シリコン基板１に
まずリーク防止領域としてのＰウェル２を形成してか
ら、このＰウェル２の表面にキャパシタ用のトレンチを
形成しそこに電荷蓄積領域となるn-層３と熱酸化膜４と
キャパシタ電極となるポリシリコン層５とを積層状に形
成することによりトレンチキャパシタを作成している。FIG. 2A shows an example of the structure of a conventional trench capacitor for preventing leakage. For example, when the charge storage region of the capacitor is composed of an n − layer, the leakage prevention region is first formed on the P-type silicon substrate 1. After the P well 2 is formed, a trench for a capacitor is formed on the surface of the P well 2, and an n − layer 3 serving as a charge storage region, a thermal oxide film 4, and a polysilicon layer 5 serving as a capacitor electrode are formed therein. A trench capacitor is formed by forming the above in a laminated shape.
また、Ｐウェル２を作る代りに、同図（ｂ）に示すよう
にＰ型シリコン基板１にまずトレンチを形成してからこ
のトレンチの内面にＰ型不純物を含んだ固体拡散源、例
えばボロンドープトシリケートガラス（BSG）６を堆積
させ、このBSG6からボロンを拡散させてトレンチの周囲
にリーク防止領域としてのP-層７を形成するという方法
も用いられている。Instead of forming the P well 2, a trench is first formed in the P type silicon substrate 1 as shown in FIG. 1B, and then a solid diffusion source containing P type impurities, for example, boron doping, is formed on the inner surface of the trench. There is also used a method of depositing a tosilicate glass (BSG) 6 and diffusing boron from the BSG 6 to form a P − layer 7 as a leak prevention region around the trench.
しかしながら、第１図（ａ）に示したＰウェル２内にト
レンチキャパシタを形成する方法においては、Ｐウェル
２はキャパシタ相互間でリークが発生しないように高い
不純物濃度をトレンチキャパシタの深さ以上まで確保し
なくてはならないため、長時間に亘ってウェル拡散を行
わなくてはならない。そのために、半導体装置の製造時
間が長くなってしまうという問題がある。However, in the method of forming the trench capacitor in the P well 2 shown in FIG. 1A, the P well 2 has a high impurity concentration up to the depth of the trench capacitor or more so as to prevent leakage between the capacitors. Since it must be ensured, well diffusion must be performed for a long time. Therefore, there is a problem that the manufacturing time of the semiconductor device becomes long.
また、同図（ｂ）に示したBSG6などを用いてトレンチの
周囲にリーク防止用のP-層７を形成する方法において
は、BSG6をはく離する際に素子間分離用として形成した
酸化膜の厚みが減少し、更にトレンチの内面にひ素ドー
プトシリケートガラス（AsSG）などを堆積させてこれを
拡散源としてP-層７の内側に電荷蓄積領域となるn-層を
形成した後、AsSGをはく離する際にまた酸化膜厚が減少
してしまうという問題がある。また、P-層をまず形成し
てその後にn-層を形成するという２段階の拡散工程が必
要であるために、この方法も製造時間が長いという問題
を有している。Further, in the method of forming the leak preventing P − layer 7 around the trench by using BSG6 or the like shown in FIG. 7B, the oxide film formed for element isolation when the BSG6 is peeled off is used. As the thickness decreases, arsenic-doped silicate glass (AsSG) is deposited on the inner surface of the trench, and this is used as a diffusion source to form an n - layer serving as a charge storage region inside the P - layer 7. There is a problem that the oxide film thickness decreases again when peeling. Further, this method also has a problem that the manufacturing time is long because a two-step diffusion process of first forming the P − layer and then forming the n − layer is required.
本発明は上記に鑑みなされたもので、トレンチキャパシ
タの電荷蓄積領域とリーク防止領域とを短時間で形成す
ることができる半導体装置の製造方法を提供することを
目的とする。The present invention has been made in view of the above, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a charge storage region and a leak prevention region of a trench capacitor in a short time.
上記目的を達成するために本発明は、半導体基板にキャ
パシタ用トレンチを形成した後、このトレンチの内面に
基板と同導電型の拡散係数の比較的大きい不純物とこれ
と異導電型の拡散係数の比較的小さい不純物とを両方含
有する固体拡散源を堆積させ、この拡散源からトレンチ
周囲の基板内へ両不純物を同時に各々の拡散係数に従っ
て拡散させることによって、トレンチの周囲に内側には
キャパシタの電荷蓄積領域となる基板とは異導電型の半
導体層を、またその外側にはリーク防止領域となる基板
と同導電型の半導体層を同時に形成するようにしたもの
である。In order to achieve the above object, the present invention is to form a capacitor trench in a semiconductor substrate, and then form an impurity having a relatively large diffusion coefficient of the same conductivity type as that of the substrate and a diffusion coefficient of a different conductivity type on the inner surface of the trench. By depositing a solid diffusion source containing both relatively small impurities and diffusing both impurities simultaneously from the diffusion source into the substrate around the trench according to their respective diffusion coefficients, the charge of the capacitor is placed inside the trench. A semiconductor layer having a different conductivity type is formed on the substrate to be the accumulation region, and a semiconductor layer having the same conductivity type as the substrate to be the leak prevention region is formed on the outer side thereof at the same time.
以下、実施例により本発明を説明する。 Hereinafter, the present invention will be described with reference to examples.
第１図は本発明に係る半導体装置の製造方法の一実施例
を示す。FIG. 1 shows an embodiment of a method of manufacturing a semiconductor device according to the present invention.
まず、Ｐ型シリコン基板11上に、これをエッチングする
際のマスク材となるCVD二酸化シリコン12を堆積した
後、その上にフォトレジスト13を堆積しパターニングす
る（第１図（ａ））。次に、このフォトレジスト13をマ
スクとして、その下にCVD二酸化シリコン12を反応性イ
オンエッチング法（RIE）によりエッチングする（同図
（ｂ））。その後、フォトレジスト13をはく離し、エッ
チングしたCVD二酸化シリコン12をマスクとして、その
下のシリコン基板11をRIEによりエッチングしてそこに
キャパシタ用トレンチ14を形成する（同図（ｃ））。次
に、このトレンチ14の内面にＰ型とｎ型の両不純物を含
有した固体拡散源、例えばボロンひ素ドープトシリケー
トガラス（BAsSG）15をCVD法により堆積させて950℃で3
0分間アニールし、このBAsSG15からトレンチ14の周囲の
基体内部へボロンとひ素を同時に熱拡散させる（同図
（ｄ））。このとき、ボロンは拡散係数がひ素に比較し
て高いために同一条件下での熱拡散によって拡散深度は
ひ素よりも深い位置まで到達する。その結果、トレンチ
14の周囲には、内側にはひ素拡散による電荷蓄積領域と
なるn-層16が、またその外側にはボロン拡散によるリー
ク防止領域となるP-層17が同時に形成される。次に、BA
sSG15およびCVD二酸化シリコン12をはく離し（同図
（ｅ））、続いて全表面にキャパシタ絶縁酸化膜を形成
した後、その上にキャパシタ電極となるポリシリコン19
を堆積する（同図（ｆ））。これにより、リーク防止域
を備えたトレンチキャパシタが完成する。First, a CVD silicon dioxide 12 that serves as a mask material for etching the P-type silicon substrate 11 is deposited, and then a photoresist 13 is deposited and patterned on the CVD silicon dioxide 12 (FIG. 1A). Next, using this photoresist 13 as a mask, the CVD silicon dioxide 12 is etched under the photoresist 13 by the reactive ion etching method (RIE) (FIG. 2B). Then, the photoresist 13 is peeled off, and the etched silicon dioxide 12 is used as a mask to etch the underlying silicon substrate 11 by RIE to form a capacitor trench 14 therein (FIG. 3C). Next, a solid diffusion source containing both P-type and n-type impurities, for example, boron arsenic-doped silicate glass (BAsSG) 15 is deposited on the inner surface of the trench 14 by the CVD method, and the solid-state diffusion source is deposited at 950 ° C.
Annealing is performed for 0 minutes, and boron and arsenic are simultaneously thermally diffused from this BAsSG15 into the inside of the substrate around the trench 14 (FIG. 7 (d)). At this time, since boron has a higher diffusion coefficient than arsenic, the diffusion depth reaches a position deeper than arsenic by thermal diffusion under the same conditions. As a result, the trench
Around the periphery of 14 is formed an n − layer 16 which serves as a charge storage region by arsenic diffusion, and a P − layer 17 which serves as a leak prevention region by boron diffusion is formed on the outside thereof at the same time. Then BA
Peel off the sSG15 and the CVD silicon dioxide 12 ((e) in the same figure), then form a capacitor insulating oxide film on the entire surface, and then use polysilicon 19 to become a capacitor electrode on it.
Are deposited ((f) in the figure). As a result, the trench capacitor having the leak prevention region is completed.
このように、ボロンとひ素の拡散係数の違いを利用して
一度の熱拡散で電荷蓄積領域（n-層16）とリーク防止領
域（P-層17）とを同時に形成することによって、製造時
間を短縮できると共に、拡散源（BAsSG15）のはく離も
１回で済むので、はく離を２回行わなければならない従
来方法（第２図（ｂ））に比較して、はく離による素子
分離用の酸化膜の膜厚の減少が少ないという利点があ
る。In this way, the charge accumulation region (n − layer 16) and the leak prevention region (P − layer 17) are simultaneously formed by one thermal diffusion by utilizing the difference in the diffusion coefficient between boron and arsenic. Since the diffusion source (BAsSG15) can be stripped only once, the oxide film for element isolation by stripping can be compared to the conventional method in which stripping must be performed twice (Fig. 2 (b)). There is an advantage that the reduction of the film thickness is small.
尚、上記実施例では電荷蓄積領域をn-層とする場合につ
いて述べたが、もちろんP-層とする場合にも本発明は適
用でき、この場合にはｎ型の不純物の方がＰ型の不純物
よりも拡散係数が大きくなるように不純物を選択するこ
とになる。Although the above embodiment has described the case where the charge storage region is the n − layer, the present invention can also be applied to the case where the charge storage region is the P − layer. In this case, the n-type impurity is the p-type. The impurities are selected so that the diffusion coefficient is larger than that of the impurities.
以上説明したように、本発明によれば拡散係数の異なる
互いに異導電型の２種類の不純物を含有した固体拡散源
を用いて、キャパシタ用トレンチの周囲にキャパシタの
電荷蓄積領域となる半導体層とリーク防止領域となる半
導体層とを同時に形成するようにしているので、トレン
チキャパシタの製造時間が短縮されるという効果が得ら
れる。As described above, according to the present invention, a solid-state diffusion source containing two kinds of impurities of different conductivity types having different diffusion coefficients is used, and a semiconductor layer serving as a charge storage region of a capacitor is formed around a capacitor trench. Since the semiconductor layer serving as the leak prevention region is formed at the same time, the manufacturing time of the trench capacitor can be shortened.
第１図は本発明に係る半導体装置の製造方法の一実施例
をその工程順に示す断面図、第２図は従来のトレンチキ
ャパシタのリーク防止のための構造を示す断面図であ
る。 1,11……Ｐ型シリコン基板、２……Ｐウェル、3,16……
n-層、4,18……キャパシタ絶縁酸化膜、5,19……キャパ
シタ電極、６……ボロンドープトシリケートガラス、7,
17……P-層、12……CVD二酸化シリコン、13……フォト
レジスト、14……キャパシタ用トレンチ、15……ボロン
ひ素ドープトシリケートガラス。FIG. 1 is a sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps, and FIG. 2 is a sectional view showing a conventional structure for preventing leakage of a trench capacitor. 1,11 …… P-type silicon substrate, 2 …… P well, 3,16 ……
n - layer, 4,18 ... Capacitor insulating oxide film, 5,19 ... Capacitor electrode, 6 ... Boron-doped silicate glass, 7,
17 …… P - layer, 12 …… CVD silicon dioxide, 13 …… Photoresist, 14 …… Capacitor trench, 15 …… Boron arsenic-doped silicate glass.
Claims (2)
製造方法において、第１導電型のシリコン基板にキャパ
シタ用トレンチを形成した後に、このトレンチの内面に
拡散係数の比較的大きい第１導電型の不純物と拡散係数
の比較的小さい、第１導電型と異なる第２導電型の不純
物の双方を含有するシリケートガラスを堆積させ、この
シリケートガラスから前記トレンチの周囲の基体内へ前
記両不純物を同時に夫々の拡散係数に従って拡散させる
工程を備え、この工程により前記トレンチの周囲の内側
には前記キャパシタの電荷蓄積領域となる第２導電型の
半導体層を、またその外側にはリーク防止領域となる第
１導電型の半導体層を同時に形成するようにしたことを
特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device having a trench capacitor, wherein after a capacitor trench is formed in a silicon substrate of the first conductivity type, an impurity of the first conductivity type having a relatively large diffusion coefficient is formed on the inner surface of the trench. Depositing a silicate glass having both a first conductivity type and a second conductivity type impurity having a relatively small diffusion coefficient, and simultaneously diffusing both the impurities from the silicate glass into the substrate around the trench. A step of diffusing in accordance with a coefficient, and by this step, a semiconductor layer of a second conductivity type that becomes a charge storage region of the capacitor is provided inside the periphery of the trench, and a semiconductor layer of a first conductivity type that becomes a leak prevention region is provided outside thereof. 2. A method for manufacturing a semiconductor device, characterized in that the semiconductor layers are simultaneously formed.
第１導電型の不純物はボロンであり、前記第２導電型の
不純物はひ素であることを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。2. The silicon substrate is a P-type substrate, the first conductivity type impurity is boron, and the second conductivity type impurity is arsenic. A method for manufacturing a semiconductor device as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60282636A JPH0682797B2 (en) | 1985-12-16 | 1985-12-16 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60282636A JPH0682797B2 (en) | 1985-12-16 | 1985-12-16 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62141753A JPS62141753A (en) | 1987-06-25 |
| JPH0682797B2 true JPH0682797B2 (en) | 1994-10-19 |
Family
ID=17655095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60282636A Expired - Fee Related JPH0682797B2 (en) | 1985-12-16 | 1985-12-16 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682797B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5231677A (en) * | 1975-08-19 | 1977-03-10 | Matsushita Electronics Corp | Production method of semiconductor device |
| JPS5270756A (en) * | 1975-12-10 | 1977-06-13 | Oki Electric Ind Co Ltd | Impurity diffusion method |
| JPS60152059A (en) * | 1984-01-20 | 1985-08-10 | Toshiba Corp | Semiconductor memory device |
-
1985
- 1985-12-16 JP JP60282636A patent/JPH0682797B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62141753A (en) | 1987-06-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |