JPH0682797B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device such as a semiconductor memory having a trench capacitor.

[Prior art]

In a semiconductor device having a trench capacitor, preventing leakage between capacitors is an important issue.

FIG. 2A shows an example of the structure of a conventional trench capacitor for preventing leakage. For example, when the charge storage region of the capacitor is composed of an n ⁻ layer, the leakage prevention region is first formed on the P-type silicon substrate 1. After the P well 2 is formed, a trench for a capacitor is formed on the surface of the P well 2, and an n ⁻ layer 3 serving as a charge storage region, a thermal oxide film 4, and a polysilicon layer 5 serving as a capacitor electrode are formed therein. A trench capacitor is formed by forming the above in a laminated shape.

Instead of forming the P well 2, a trench is first formed in the P type silicon substrate 1 as shown in FIG. 1B, and then a solid diffusion source containing P type impurities, for example, boron doping, is formed on the inner surface of the trench. There is also used a method of depositing a tosilicate glass (BSG) 6 and diffusing boron from the BSG 6 to form a P ⁻ layer 7 as a leak prevention region around the trench.

[Problems of conventional technology]

However, in the method of forming the trench capacitor in the P well 2 shown in FIG. 1A, the P well 2 has a high impurity concentration up to the depth of the trench capacitor or more so as to prevent leakage between the capacitors. Since it must be ensured, well diffusion must be performed for a long time. Therefore, there is a problem that the manufacturing time of the semiconductor device becomes long.

Further, in the method of forming the leak preventing P ⁻ layer 7 around the trench by using BSG6 or the like shown in FIG. 7B, the oxide film formed for element isolation when the BSG6 is peeled off is used. As the thickness decreases, arsenic-doped silicate glass (AsSG) is deposited on the inner surface of the trench, and this is used as a diffusion source to form an n ^- layer serving as a charge storage region inside the P ^- layer 7. There is a problem that the oxide film thickness decreases again when peeling. Further, this method also has a problem that the manufacturing time is long because a two-step diffusion process of first forming the P ⁻ layer and then forming the n ⁻ layer is required.

[Object of the Invention]

The present invention has been made in view of the above, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a charge storage region and a leak prevention region of a trench capacitor in a short time.

[Outline of Invention]

In order to achieve the above object, the present invention is to form a capacitor trench in a semiconductor substrate, and then form an impurity having a relatively large diffusion coefficient of the same conductivity type as that of the substrate and a diffusion coefficient of a different conductivity type on the inner surface of the trench. By depositing a solid diffusion source containing both relatively small impurities and diffusing both impurities simultaneously from the diffusion source into the substrate around the trench according to their respective diffusion coefficients, the charge of the capacitor is placed inside the trench. A semiconductor layer having a different conductivity type is formed on the substrate to be the accumulation region, and a semiconductor layer having the same conductivity type as the substrate to be the leak prevention region is formed on the outer side thereof at the same time.

Example of Invention

 Hereinafter, the present invention will be described with reference to examples.

FIG. 1 shows an embodiment of a method of manufacturing a semiconductor device according to the present invention.

First, a CVD silicon dioxide 12 that serves as a mask material for etching the P-type silicon substrate 11 is deposited, and then a photoresist 13 is deposited and patterned on the CVD silicon dioxide 12 (FIG. 1A). Next, using this photoresist 13 as a mask, the CVD silicon dioxide 12 is etched under the photoresist 13 by the reactive ion etching method (RIE) (FIG. 2B). Then, the photoresist 13 is peeled off, and the etched silicon dioxide 12 is used as a mask to etch the underlying silicon substrate 11 by RIE to form a capacitor trench 14 therein (FIG. 3C). Next, a solid diffusion source containing both P-type and n-type impurities, for example, boron arsenic-doped silicate glass (BAsSG) 15 is deposited on the inner surface of the trench 14 by the CVD method, and the solid-state diffusion source is deposited at 950 ° C.
Annealing is performed for 0 minutes, and boron and arsenic are simultaneously thermally diffused from this BAsSG15 into the inside of the substrate around the trench 14 (FIG. 7 (d)). At this time, since boron has a higher diffusion coefficient than arsenic, the diffusion depth reaches a position deeper than arsenic by thermal diffusion under the same conditions. As a result, the trench
Around the periphery of 14 is formed an n ⁻ layer 16 which serves as a charge storage region by arsenic diffusion, and a P ⁻ layer 17 which serves as a leak prevention region by boron diffusion is formed on the outside thereof at the same time. Then BA
Peel off the sSG15 and the CVD silicon dioxide 12 ((e) in the same figure), then form a capacitor insulating oxide film on the entire surface, and then use polysilicon 19 to become a capacitor electrode on it.
Are deposited ((f) in the figure). As a result, the trench capacitor having the leak prevention region is completed.

In this way, the charge accumulation region (n ⁻ layer 16) and the leak prevention region (P ⁻ layer 17) are simultaneously formed by one thermal diffusion by utilizing the difference in the diffusion coefficient between boron and arsenic. Since the diffusion source (BAsSG15) can be stripped only once, the oxide film for element isolation by stripping can be compared to the conventional method in which stripping must be performed twice (Fig. 2 (b)). There is an advantage that the reduction of the film thickness is small.

Although the above embodiment has described the case where the charge storage region is the n ⁻ layer, the present invention can also be applied to the case where the charge storage region is the P ⁻ layer. In this case, the n-type impurity is the p-type. The impurities are selected so that the diffusion coefficient is larger than that of the impurities.

〔The invention's effect〕

As described above, according to the present invention, a solid-state diffusion source containing two kinds of impurities of different conductivity types having different diffusion coefficients is used, and a semiconductor layer serving as a charge storage region of a capacitor is formed around a capacitor trench. Since the semiconductor layer serving as the leak prevention region is formed at the same time, the manufacturing time of the trench capacitor can be shortened.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps, and FIG. 2 is a sectional view showing a conventional structure for preventing leakage of a trench capacitor. 1,11 …… P-type silicon substrate, 2 …… P well, 3,16 ……
n ^- layer, 4,18 ... Capacitor insulating oxide film, 5,19 ... Capacitor electrode, 6 ... Boron-doped silicate glass, 7,
17 …… P ^- layer, 12 …… CVD silicon dioxide, 13 …… Photoresist, 14 …… Capacitor trench, 15 …… Boron arsenic-doped silicate glass.

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a trench capacitor, wherein after a capacitor trench is formed in a silicon substrate of the first conductivity type, an impurity of the first conductivity type having a relatively large diffusion coefficient is formed on the inner surface of the trench. Depositing a silicate glass having both a first conductivity type and a second conductivity type impurity having a relatively small diffusion coefficient, and simultaneously diffusing both the impurities from the silicate glass into the substrate around the trench. A step of diffusing in accordance with a coefficient, and by this step, a semiconductor layer of a second conductivity type that becomes a charge storage region of the capacitor is provided inside the periphery of the trench, and a semiconductor layer of a first conductivity type that becomes a leak prevention region is provided outside thereof. 2. A method for manufacturing a semiconductor device, characterized in that the semiconductor layers are simultaneously formed. 2. The silicon substrate is a P-type substrate, the first conductivity type impurity is boron, and the second conductivity type impurity is arsenic. A method for manufacturing a semiconductor device as described above.