JPS63117461A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To easily realize the high integration by narrowing the interval between thin grooves and to realize the manufacture with good reproducibility and uniformly by a method wherein a p-type boron-diffused layer is deposited on the side wall of a thin groove and its bottom and an n-type arsenic-diffused layer which is thinner than this n-type diffused layer is deposited on this p-type diffused layer with a view to forming a capacitive electrode on this n-type diffused layer through an insulating film. CONSTITUTION:After a field oxide film 7 has been formed on a p-type semiconductor substrate 5, a thin groove 6 is formed; boron ions are implanted; the assembly is heat-treated. If, during this ion implantation process, the substrate 5 is turned while it is inclined at an angle bigger than an angle theta which is formed between a diagonal line of the thin groove 6 and its side wall, a P-type diffused layer 9 can be formed. Then, an opening is made at a memory cell capacitor part 11; arsenic ions are implanted; the assembly is heat-treated. If, during this ion implantation process, the substrate 5 is turned while it is inclined at an angle bigger than an angle phi which is formed between the diagonal line of the narrow groove 6 and its side wall, an n-type diffused layer 10 can be formed. Then, an SiO2 film is formed on the surface of the substrate 5 which is not thermally oxidized. In succession, a polysilicon film which does not contain phosphorus (P) is deposited. By removing the polysilicon film and the SiO2 film other than the cell capacitor part 11, a capacitive insulating film 12 composed of the SiO2 film and a capacitor electrode 14 composed of the polysilicon film are formed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device and a method for manufacturing the same.
In particular, the present invention relates to a charge storage section provided in a pore on a semiconductor substrate and a method for manufacturing the same.

[Conventional technology]

In recent years, due to the demand for higher integration in semiconductor memory devices, charge storage parts that were previously formed flat on a semiconductor substrate have been formed using pores in the semiconductor substrate to reduce the amount of semiconductor required for the charge storage part. Attempts have been made to reduce the area of the substrate surface.

An n-type diffusion layer is usually formed in the p-type semiconductor substrate layer under the capacitive insulating film provided in this charge storage section. The reason for this is that the pn junction has the effect of increasing the capacitance and that the capacitor electrode can be grounded, which is preferable for circuit operation.

Conventionally, when forming an electric storage part by providing pores in a p-type semiconductor substrate, as shown in FIG. In this way, an n-type diffusion layer 4 was formed. That is, after forming PSGWA 3 on the surface of a pore 2 provided on the surface of a p-type semiconductor substrate 1 by CVD, an n-type diffusion layer 4 made of phosphorus was formed on the side and bottom portions of the pore by heat treatment. .

[Problem that the invention seeks to solve]

In the conventional method described above, (1) it is difficult to control the phosphorus concentration in the PSG film formed by CVD and the temperature and time of heat treatment, resulting in poor reproducibility of the n-type diffusion layer; and (2) the pores are deep. In the case of pores, it is difficult to uniformly form a PSG film all the way to the bottom, (3) the phosphorus diffusion layer expands due to heat cycles in the post-process, and short circuits occur between the pores due to punch-through; There are drawbacks such as difficulty in shortening the hole spacing, making it difficult to adapt to high integration, and (5) no measures against soft errors caused by alpha rays.

An object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, which can eliminate such drawbacks, shorten the pore spacing, facilitate high integration, and be uniformly manufactured with good reproducibility. It is in.

[Means for solving problems]

A charge storage section comprising an insulating film and a capacitive electrode provided on the surface of a pore formed from the surface of a p-type semiconductor substrate toward the inside of the substrate, and an insulated gate field effect transistor according to the first invention. A semiconductor memory device comprising:
A P-type diffusion layer made of boron is formed on the side and bottom portions of the pore, and an n-type diffusion layer made of arsenic, which is shallower than this n-type diffusion layer, is laminated on this n-type diffusion layer, and this n-type The capacitor electrode is provided on the diffusion layer with the insulating film interposed therebetween.

Further, in the method for manufacturing a semiconductor memory device according to the second invention, boron ions are implanted into the side and bottom portions of the pores formed from the surface of the p-type semiconductor substrate toward the inside of the substrate, and heat treatment is performed to form the n-type semiconductor memory device. A process of forming a diffusion layer, a process of implanting arsenic ions onto this n-type diffusion layer and performing heat treatment to form a shallow n-type diffusion layer, and a process of forming a capacitor electrode on this n-type diffusion layer via an insulating film. and forming a charge storage section.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1E are cross-sectional views showing the steps of manufacturing a semiconductor memory device according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a field oxide film 7 for element isolation is formed on a p-type semiconductor substrate (hereinafter referred to as substrate) 5 by selective oxidation, and then a patterned photoresist film 8 is used as a mask. By reactive ion etching method (hereinafter referred to as RIE method), a width of 1.2 μm,
A pore 6 having a length of 1.2 μm and a depth of 5 μm is formed, and 10 13 to 10 14 boron ions/cT 12 are implanted by a known ion implantation method under conditions of 100 to 150 keV, followed by heat treatment.

During this ion implantation, boron ions are implanted perpendicularly into the substrate 5, and at the same time, the substrate 11 is rotated as shown by the arrow at an angle greater than the angle θ formed by the diagonal line of the pore 6 and the side surface. An n-type diffusion layer 9 is formed on the bottom and side surfaces of the substrate 6 by implanting boron ions.

Next, as shown in FIG. 1(b), the photoresist film 8
After removing the photoresist film 8', a photoresist film 8' is applied again, an opening is made in the storage capacitor cell part 11, and a 100%
Arsenic ion 1o 13-10 under ~150keV condition
14 pieces/clI+2 are injected and heat treated. During this ion implantation, by rotating the substrate 5 while tilting it at an angle greater than the angle φ formed by the diagonal line and the side surface of the pore 6 as shown by the arrow, arsenic ions are deposited on the bottom and side surfaces of the pore 6. An n-type diffusion layer 10 is formed by implantation. Depending on the heat treatment conditions, the n-type diffusion layer 10 can be formed shallower than the n-type diffusion layer 9.

Next, as shown in FIG. 1(c), about ioo.

A 5i02 film of approximately 150 layers is formed on the surface of the substrate 5 by thermal oxidation in a dry oxygen atmosphere at .degree. Subsequently, a polysilicon film containing phosphorus (P) is deposited by CVD. At this time, the pores 6 are filled with the polysilicon film. Then, the polysilicon film and the 5i02 film other than the cell capacitor portion 11 are removed to form a capacitor insulating film 12 made of a SiO□ film and a capacitor electrode 14 made of a polysilicon film.

Thereafter, thermal oxidation is performed again to form about 300 thin layers of 5i0213 in areas other than the memory cell capacitor portion 11.

At this time, the surface of the capacitor electrode 14 is covered with a thick 5iO21i (hereinafter referred to as a first interlayer insulating film) 15.

Next, as shown in FIG. 1(d), phosphorus (
After depositing a polysilicon film containing P), this polysilicon film and the thin 5i02 film 13 are patterned,
Gate oxide film 13' and gate electrode (word line) 16
form. Next, field oxide film 7 and gate electrode 1
6, and an n+ type impurity layer 1 in which arsenic ions are implanted using the first interlayer insulating film 15 as a mask and diffused to become a bit line.
form 7.

Next, as shown in FIG. 1(e), after forming a 5i02 film 18 and a PSG film 19 as a second interlayer film 20 on the entire surface, a 5i02 film 18 and a PSG film 19 are formed on the entire surface, and then
Openings 21 are provided in the 02 film 18 and the PSG film 19. Next, someone deposits a ^l film over the entire surface, patterns it, and connects it to the n+ type impurity layer 17! Wiring (bit line) 22 is formed and a semiconductor memory device is manufactured.

FIGS. 2(a) and 2(b) are cross-sectional views showing a second embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 2(a), after forming a field oxide film 7 on a substrate 5,
Using the patterned photoresist film 8 as a mask, R
Pores 6 are formed by the IE method.

Next, as shown in FIG. 2(b), the photoresist film 8
After removing the photoresist film 8', a photoresist film 8' is applied again.
An opening is provided in the storage capacitor cell portion 11, and boron ions and arsenic ions are implanted at 100 to 150 keV by ion implantation.
Under these conditions, 1011°1014 ions/cs2 are implanted and heat treated. During this ion implantation, the substrate 5 is implanted as shown by the arrow.
By rotating the pore 6 while tilting it at an angle greater than the angle φ formed by the diagonal line and the side surface of the pore 6, an n-type diffusion layer made of boron ions and an n-type diffusion layer made of arsenic ions are formed at the bottom and side portions of the pore 6. A diffusion layer is formed. Here, the n-type diffusion layer can be formed shallower than the n-type diffusion layer due to the difference in the diffusion coefficients of boron and arsenic in silicon.

Hereinafter, a semiconductor memory device is manufactured according to the steps shown in FIGS. 1(C) to 1(e).

〔Effect of the invention〕

As explained above, the present invention forms an n-type diffusion layer made of boron and an n-type diffusion layer made of arsenic shallower than this n-type diffusion layer on the side and bottom portions of the pores of the charge storage portion of a semiconductor memory device. As a result, 1) the capacitance due to the p-n junction can be increased, 2) the capacitive electrode can be grounded, and 3) the width of the depletion layer in the pore can be reduced, which reduces punch-through between the pores and 4) Minority carriers are less likely to gather in the pores due to the potential, resulting in reduction of soft errors.

In addition, regarding the manufacturing method, the n-type diffusion layer and the shallow n-type diffusion layer formed in the pores are implanted with boron ions and arsenic ions, so that the n-type diffusion layer and the shallow n-type diffusion layer are formed uniformly and reproducibly without depending on the depth of the pore. This has the effect of improving manufacturing yield.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views showing the manufacturing process of a semiconductor memory device according to an embodiment of the present invention, and FIGS.
b) is a sectional view showing the manufacturing process of the second embodiment of the present invention;
FIG. 3 is a cross-sectional view showing a charge storage section in a conventional manufacturing process. 1.5...p-type semiconductor substrate, 2.6...pore, 3゜19...PSG film, 4,10...n-type diffusion layer, 7.
...Field oxide film, 8...Photoresist film, 9
. . . p-type diffusion layer, 11 . . . storage cell capacitor portion, 12.
...Capacitive insulating film, 13.18...SiO□ film, 13'
...gate oxide film, 14...capacitance electrode, 15...
First interlayer insulating film, 16...gate electrode, 17...n
+ type impurity layer, 20... second interlayer insulating film, 21...
Opening hole, 22...Al wiring. Ga I diagram

Claims (2)

[Claims] (1) Includes a charge storage section having an insulating film and a capacitor electrode provided on the surface of a pore formed from the surface of a p-type semiconductor substrate toward the inside of the substrate, and an insulated gate field effect transistor. In the semiconductor memory device, a p-type diffusion layer made of boron and an n-type diffusion layer made of arsenic, which is shallower than the p-type diffusion layer, are laminated on the side and bottom portions of the pore. A semiconductor memory device characterized in that the capacitor electrode is provided on the n-type diffusion layer with the insulating film interposed therebetween. (2) A step of implanting boron ions into the side and bottom portions of the pores formed from the surface of the p-type semiconductor substrate toward the inside of the substrate and performing heat treatment to form a p-type diffusion layer;
Arsenic ions are implanted onto the type diffusion layer and heat treatment is performed to form a shallow n.
A method for manufacturing a semiconductor memory device, comprising the steps of forming a type diffusion layer and forming a charge storage section by providing a capacitor electrode on the n-type diffusion layer via an insulating film.