JPS5950561A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the breakdown of a gate insulation film by a method wherein a region of the same conductivity type as a substrate and a high impurity concentration is formed in the lower part of the source or drain region of a MISFET. CONSTITUTION:The n<+> type source region 202, the n<+> type drain region 203 of the MOSFET, an Si dioxide film 204, a gate electrode 205, interlayer insulation films 206, wiring layers 207, insulation films 208 and 209, and wiring layers 210 of the uppermost layers are formed on the p type substrate 1, and the p<+> regions of the impurity concentration higher than that of the substrate 1 are provided in the lower part of the regions 202 and 203. These regions are formed by implanting boron ions by ion implantation before forming e.g. the source and drain regions 202 and 203. This method enables to prevent the electrostatic breakdown.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate turtle field effect transistor (hereinafter referred to as
Simply M engineering 5FET'51 is MO8FI! Semiconductor integrated circuit bag fi (hereinafter referred to as iT) used as all circuit elements
(simply referred to as an IC) and its manufacturing method.

The MO8IO that uses all MlSFFiT is the one in which all the integrated M5FETs are of the same channel type (single channel type), the P channel type and the N
There is a channel type and a complementary type (cMs) that includes both channel types. These MO8 engineering C are S RAM (5tatic Ra
ndam Access Me+nory) and D
RAM (Dynatnic RandaU1Ac
It is widely used as memory area 0 such as ce81:1y6mory).

MO8IO is easily destroyed by pressure caused by static electricity introduced by workers or handlers during the manufacturing process. This electrostatic breakdown occurs when the gate electrode is
A phenomenon that tends to occur in MISNET connected to the external input terminal (ponding pad) of C, and the gate insulating film is destroyed by excessive voltage applied in an unexpected transient state based on static electricity. (hereinafter referred to as gate destruction) occurs. For those who want to prevent this gate destruction, M-8FM, which is conventionally connected to an external input terminal that is easy to destroy! It is known to insert a gate protection diode χ to clamp T in the case of excessive voltage. This gate protection diode is a PN in the semiconductor substrate.
Zener breakdown that occurs at the junction or surface breakdown that occurs at the PM junction on the surface of the semiconductor substrate? The ones used are common.

Surface breakdown? As the structure of the gate protection diode to be used, one using an M-S FET'i is well known. In this structure, the gate a and r source electrodes are commonly connected to serve as one terminal of a protection diode, and the drain electrode serves as the other terminal of the protection diode. This diode? By inserting it into the gate input circuit of the MISNET to be preserved, a resilient breakdown occurs near the surface of the drain junction of the MISNET for the protection diode, causing excessive voltage? This is to prevent damage to the MISNET which acts as a circuit element by clamping it. This gate protection structure is used for the MISNET which acts as a circuit element, and also for the M-8 for gate protection.
Since FETi can be formed, 1! ! ! Addition of manufacturing process?
It is extremely useful in that it is not necessary, and is widely used.

The present invention relates to this MO8 type 0 used as a gate protection element, and as a result of the experimental study by the present inventors, the above-mentioned 7cM is used as a FET' as a gate protection element. , MIEIF for gate protection
The gate insulating film of the ET itself was destroyed fi7'L.

It has been found that there is no sufficient protection against various abnormal human voltages. In particular, M-engine EIFET for gate protection
gate insulating film? It turned out that the thinning process made it easier to break.

Therefore, the purpose of the present invention is to destroy the lAl5FET itself used as a gate pixel retention element. Prevented MOS engineering by providing 0 all 0 all.

Furthermore, the purpose of the pond of the present invention is to
O8IC! An object of the present invention is to provide a gate protection structure suitable for the invention.

According to one embodiment of the present invention, awns 71. are formed on one semiconductor substrate. A semiconductor region having the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the previous semiconductor substrate is formed under at least one source or drain region of the M5FET for gate protection.

Noh performance of the present invention 1! According to Ill, the upper semiconductor area is MISNE constituting DRAM or SRAM.
It is formed at the same time as a region for preventing soft errors caused by α rays of T.

Hereinafter, an implementation sequence applied to the present invention (MO8 process 0 of y-8RAM) will be described.

FIG. 1 shows the storage capacity of bits ft' (SRAM 1, layered on one semiconductor substrate 1) according to the present invention.
r is shown schematically. In the figure, 111 to lnm are external pjm elements (ponding pads) provided on the periphery of the semiconductor substrate in order to receive external signals from the IC or to transmit internal signal sounds of the IC. 1
00 has many memory cells arranged in rows and columns (64x64 bits)
This is a memory array section arranged in . Each memory cell consists of four N-channel type MO8 as shown in FIG.
Consisting of FETs 601 to 604 and polycrystalline silicon resistors R1°R2, this cell is connected to a pair of adjacent data lines DL.
I, coupled to DL2, and word line WL.

is combined with The structure of this memory cell will be described later.

A predetermined X decoder 102 selects one of the many word lines of the memory array section 100; 103 reads signals from the memory array section 100;
E rc is a readout/convolution circuit for saving. X
Decoder, X decoder, readout, ¥1 included circuit is P
C! is composed of a channel type 11i08F'FXT and a channel type MOS FBT. It has an MO8 structure.

FIG. 3 shows an equivalent circuit diagram of an I'L7"C gate floor-standing circuit constructed according to the present invention and applied to the X-decoder I01. 402 is an N-channel MO8FET, 403
is P-chan 2, type MO8FgT, and these are CMO
It consists of an S inverter and a part of the X decoder circuit. Then the CMOS inverter's 1i
, the pole is connected to the external input terminal 111. According to the present invention, a gate logic element consisting of an N-channel type MO8FET 401 is inserted into the gate input circuit. MO811'ff1T for gate protection element
401 is a group 1-[pole g is electrically connected to the source region SK, they are both connected to a reference potential source, and its drain region d is gate destroyed? MO8F of input stage to be prevented
Connected to the gate electrode of ET 402 or 403.

According to the present invention, the drain region of the MO8FWT for gate protection element has a low breakdown voltage that is lower than the Zener breakdown voltage of the PN junction of the drain region itself, which is formed on the semiconductor substrate 1. Zener diode D.

is formed. The breakdown voltage of this low voltage Zener diode DI is set lower than the permanent breakdown voltage of the gate insulating film of MO8FKT401. The structure of an N-channel MO8FET with a Zener diode Ds kg for gate protection is shown in FIG.

In No. 5 (8), B201) Vip type substrate (p type W
ell), and the n++ source region 202 and n+ drain region 203 of the MOSFET are formed in this substrate. 204 is a silicon dioxide film formed by heat treatment, 205 is a gate electrode made of polycrystalline silicon, and 206 is a well-known OVD (Chemical Vapor Deposition) film.
207 is a second wiring layer made of polycrystalline silicon film, 208 is a silicon dioxide insulating film formed by OVD method, and 209 is phosphorus silicon glass. The insulating film 210 is aluminum (A
This is the uppermost wiring layer including the electrode part of Z). Reference numeral 211 denotes a p 2 region which is provided under each layer of the n 2 source region 202 and the n 2 drain region 203 and has a higher concentration of fine particles than the p type substrate 201 . This p++ region 211 is formed before forming the n-type source region 202 and the n+5 drain region 203.
Atomic silicon ion implantation method (Ion implantation) at 5 [KeV],
) is formed by driving. J is a junction part. Such an N-channel MO8FET is
The X decoder 101, the Y decoder 102, and the read/storage circuit 103 are formed at the same time as the N-channel MO8FETs. Therefore, the structure of an N-channel type MO5FKT other than that used as a gate protection element is also represented by FIG.

According to the invention, gate gi1. MO8FET for protection element
@Akira: 211, which has a higher concentration than the P-type semiconductor substrate 201 and has the same conductivity type as the substrate 201, is formed so as to be in close contact with the lower part of the 0+ type drain region 203 of 401. A Zener diode D1 is formed having a breakdown voltage of .

The third factor and the MO for the gate protection element shown in FIG.
In the 8FFiT401, the n+ type drain region 203,
Since the PN junction of the Zener diode D having a low breakdown voltage t is formed by the n++ additional region 211, an abnormal excessive voltage due to static electricity is applied to the external input terminal 111 in an unexpected transient state. Even if the voltage is applied, the excessive voltage will be clamped at the Zener diode D1. Therefore, permanent destruction of the gate insulating film (silicon oxide film) 902 of the MO8FET 401 is prevented.

According to the present invention, low voltage Zener diodes D, MO
Since the surface eighth breakdown diode at the drain junction near the gate insulating film 927 of the 8FET 401 itself performs a clamping operation in parallel, the range of protection against excessive vehicle pressure can be improved. At this time, the p-type additional region 211 and the nm drain region 203 are as follows.
Since both form a PNN junction shadow with high impurity concentration,
The PN junction capacitance at this portion increases.

Therefore, as shown in Fig. 3, the parasitic capacitance ftOt due to the above-mentioned PN junction capacitance is added to the low voltage Zener diode DI, so that its rise time is Grapes can be delayed. In other words, if there is a steep excessive input pulse vehicle pressure t, the peak value of the input pulse is limited, and the rise characteristics of the abnormal human power pulse deteriorate gradually, so MO8FET401 and Zener diode D are used.
, the protection operation 7 can be made more complete.

Although the non-implemented WIJtrix decoder 101 has been described, the gate power retention circuit of the Y decoder 102 is similarly constructed of an N-channel type MO8FKT having the same structure as in FIG.

Furthermore, if the output circuit connected to the external output terminal is configured with a MOSFET having the structure of MOS E'B T shown in FIG. 5, the final stage output circuit connected to the external output terminal will be configured. Destruction of the MOSFET gate can be prevented. FIG. 4 shows this embodiment.

In Figure 4, 5 is the output stage circuit, 501°50
2 is an N-channel MO8FET. MO of these people
8FETO8FET Bonseki 5 diagram j N channel type MO8F
By having the same structure as FfT, the drain region of each transistor is provided with low voltage Zener diodes D3, D4 and their capacitances C3, C4 and t. In Fig. 4, the inverter is used to convert the signal applied to the gate of the N-channel type MO8FET501 and the phase-inverted signal iN-channel type MOEIFKT.
502. The output circuit 5 is connected to an external output terminal 1 nm. Output circuit like this? By forming the external output terminal 1n
For example, even if an excessive voltage due to static electricity is applied to m, the MO8FET50
2 and 501 can be prevented from breaking.

As explained above, according to the present invention, the n-type source region of the N-channel MO8FET shown in FIG.
By providing a p-type region under at least one of the + drain regions, the p-type substrate has an impurity concentration similar to that of the p-type substrate.
N-channel MO8F'ET 401, 402, 501, 502 static damage in the input circuit and output circuit of the implementation column can be prevented. In addition, since the junction capacitance between the n-type source region or the n++ drain region and the p-type region provided with the D+-type region increases, the electrostatic pulse is reduced to 1, thereby increasing the electrostatic breakdown strength. I can do it.

The above-mentioned N-channel MO8FET in the p-type additional region t drain region is an N-channel MO8F that constitutes the memory cell of the memory array section 100 (FIG. 1).
Formed simultaneously with ET601-604 (FIG. 2). FIG. 6 shows a cross-sectional structure of MO8FETs 601 and 602 and a polycrystalline silicon resistor R, of the circuit assembly shown in the memory cell circuit of FIG. show.

In FIG. 6, l is a silicon semiconductor substrate, and a p-type well region 1001 is formed in this semiconductor substrate. 9
13 is an n-type semiconductor region and is the source (S) of the MOSFET.
) and drain (d) k. 912 is provided adjacent to the Ω++ semiconductor region 913 according to the present invention.
This region is a p++ semiconductor region, and this region is a well region 100.
It has a higher concentration of impurities than 1. 909 is the first polycrystalline silicon layer, which is the gate electrode (g) of the MOSFET.
)h, and a contact electrode is further formed on the drain region 913(d). A second polycrystalline silicon layer 916 constitutes a distribution layer r connecting the drain region 913 and the power source (V, . . . ).

This wiring layer has a resistive region 1002(R+)k consisting of a genuine conductor whose impurity concentration is lower than that of the pond region, or where the impurity r is substantially uncolored.

This resistance region 1002 is arranged in an array Ir1IGΩ~l0UG
Resistance value in Ω? Motsu. 917 is an aluminum wiring layer. 925 is a field insulating film made of silicon oxide. 927 is a thin insulating film used as a gate insulating film. This thin 1 insulating film is made of silicon oxide. A silicon oxide film 914 is used as an interlayer insulating film. 921 is a phosphosilicate glass film (psG
M) is used as the second interlayer insulating film. A method for manufacturing this memory cell portion will be described later.

In this way, in the MOSFET constituting the memory cell part r, impurities can be introduced into the lower part of the n+ type drain region and/or source region at a surface concentration higher than that of the substrate, and the impurity can be of the same type as the substrate. It is possible to form a p-type semiconductor region with

These MOSFETs are formed by the same process as the above-mentioned MO8FET for gate preservation.

The memory array with the structure shown in FIG.
i.e. soft error? It is possible to prevent this. Figure 8 shows the effect of soft errors? This is a graph shown experimentally.

Normal power supply voltage V. For a memory array where 0 is 5V, the pressure V is set to 8°7 to make the soft error effect due to alpha rays stronger. The horizontal axis shows the voltage lowered to the range of 1 to 3V. On the other hand, a certain amount of alpha rays? The vertical axis represents the percentage of the number of memory cells in which predetermined information stored in advance is inverted by irradiating each memory cell in the memory array section. FIG. 8 (Characteristic (a) shows the case of the conventional in-layer structure in which no p-type semiconductor region is formed under the drain region. Characteristic (b) shows the case of the p-type semiconductor according to the present invention. As can be clearly seen from the comparison of the characteristics of these 1i14 regions ρ), according to the present invention, the p2!18I region 912r is formed under the drain region. The junctions with the n WF rain region 913 are thick, and it is possible to reduce inversion of information in the memory cell (soft error) due to α rays.

In the above-mentioned embodiment, the memory array portion is formed in the p-type cell area IθO1 with the formation portion 7'1. Because of this,
Electrons generated on the substrate side by α rays can be eliminated by the potential barrier at the PN junction between the p-type well region 1001 and the n-type substrate 901. According to this nK, α
This allows for more complete countermeasures against soft errors caused by wires.

Next, M
Regarding the manufacturing method of SRA MIC equipped with OBFETf, see Fig. 7 (A) to Fig. 7)? Refer to and explain. An N-channel type MO8FET according to the present invention, which is used in SRAMIC for simplicity of explanation, and a P-channel type MO8FET according to the present invention
8FF;T and 7 will be representatively illustrated and the process will be explained.

As shown in FIG. 7(A), an n-type silicon wafer (substrate) 901 having a specific resistance of 8 to 12 Ω-cTnO is prepared in order to form a CMO of 8 to 11 inches.The n-type silicon wafer 901 is subjected to heat treatment, etc. A thin silicon dioxide y (5 to 2) 902' is formed by using the method.An oxidation-resistant film of nitride (813N4) is formed on the entire surface of this silicon oxide film 902.
- Leaving 904 oxidation-resistant films on the mold layer forming part, song blood TM
Remove any residual film.

As shown in FIG. 7B, phosphorus ions are implanted into the exposed portion of the insulating film 902 of the en-type silicon wafer 901 by the ion implantation method to form a region px2. Next, by thermally oxidizing the entire substrate, a thick silicon oxide film 925 is formed on the n7j portion exposed from the oxidation-resistant film.
Form a ligature.

As shown in FIG. 7(0), the oxidation-resistant film 904 is removed,
The thick silicon oxide film 925 and the thin silicon oxide film 9
By ion implantation method as 02 and r mask, 60KsV
Poron ion with energy of 2.5X1012 atoms/cr/l? A region BI shape M is implanted under the thin silicon oxide film 902.

As shown in FIG. 7), the region P and region Blr implanted by the ion implantation method are re-diffused by heat treatment, and the n-type region 905. 906 p-type layers are formed. Area 9
06 is used as a well region for an N-channel MO8FET'i type.

Thereafter, a nitride oxidation-resistant film 907 is formed entirely on the insulating films 902 and 925.

The oxidation-resistant film 907 formed in FIG. 7 (as shown in FIG. 7) is of course a mask of photoresist or the like? selectively removed using Next, in order to form a part of a p-type channel stopper with a high impurity concentration in the p-type layer 906,
Boron ions are implanted to form a channel stopper using the ion implantation method to form the bottom of the SBI region.

As shown in FIG. 7(F), heat treatment is performed to
Introducing impurity 2 of B process and p for channel stopper
At the same time as ffi region 908 is formed, well region 90 is formed.
On the different surface of No. 6, a thick silicon oxide film 926 is formed on a portion exposed by tJ3 from the oxidation-resistant film 907. After this, the oxidation-resistant film 907'i is removed. Furthermore, the oxidation-resistant film 90
The thin insulating film 902 on the lower surface of 7 is also removed.

As shown in FIG. 7CG), after the above treatment, a thin silicon oxide film 927r is formed by heat treatment, and this is used as an insulating film.

As shown in Figure 7), the channel threshold voltage r
In order to adjust the ion implantation method, a boron ion string is implanted to adjust the threshold voltage. Thereafter, a wiring layer of polycrystalline silicon and a conductive portion 909 of the gate m-pole are formed on the gate insulating film 927 by CvD technology. Thereafter, phosphorus impurity 2 is introduced into the polycrystalline silicon intoxication portion 909 to provide 4-potency. Thereafter, using a mask 910 such as a photoresist, in order to form a p-type region according to the present invention, an ion implantation method is performed to form a p+-type region at 1.25 (KeV) as shown by the arrow.
I will implant boron ions of 3XLO" atoms/C.

CtZ forms a region B in which impurities are concentrated in a relatively deep portion.

As shown in FIG. 7(1), the mask 910 such as photoresist is removed, a thin silicon oxide film 928 is formed again by heat treatment, and a nitride film 911 is formed on this.
f: Form. At this time, the region B1 into which boron ions have been implanted to form a p++ region 912 is diffused and becomes a p++ region 912. Next, phosphorus ions are implanted into the parts where the r1+ type source region and drain region are to be formed by ion implantation.

As shown in FIG. 7(J), OV D (Chemical
A silicon dioxide insulating film 914 is formed on the well region by alVapour Deposition)i, and then the f9 resistance film 911 is removed. After that, heat treatment is performed to form the n+ type region and drain region 91.
form 3.

As shown in FIG. 7(K), in order to form a p type source region and a p type drain region in the n type layer 905,
Using the disconnection M914 as a mask, boron ions BI are implanted by ion implantation. A through hole 915 is formed in the diagonal portion of the insulating film 914, and a polycrystalline silicon hole 16 is formed on the entire surface.

As shown in FIG. 7, the polycrystalline supersilicon film 916 is removed and selectively removed through the through holes 915, etc., to obtain wiring portions 917, 918, etc. Battanning.Polycrystalline silicon wiring portions 917, 9
Diffusion of phosphorus impurities into 18 gives it a characteristic effect. At this time, the boron ions BI are diffused to form a p++ drain region 919 in the p-1 type source branch. still,
When forming wiring portions 917 and 918 of polycrystalline silicon,
A mask is formed in advance on the portion 1002 which will become the resistance region shown in FIG. 6, and the diffusion of phosphorus impurities can be completely prevented.

FIG. 7 (As shown in the figure, a silicon dioxide insulation film 92
0 is formed, and an insulating film 9 of phosphosilicate glass is formed on the upper surface.
21 is formed. Thereafter, through holes 922 are formed and heat treated.

As shown in FIG. 7, aluminum (A
A top wiring layer 923 (Z) is provided, and a final passivation film (not shown) is formed to complete the device.

As explained above, according to this manufacturing process, the N-channel type layer OSFFiT with the p'-type region formed therein can be easily formed in a normal process.
The above objective can be achieved.

As explained above, the gate 1% usage M according to the present invention
O8FFiT is a MOS F that constitutes the memory array section.
Forming it simultaneously with F1T is effective in improving the nausea characteristics of the memory array section.

The present invention is not limited to the above-described embodiments, but may be modified in various ways without changing the gist thereof. In other words, the N-channel MO8FET may have a structure as shown in FIG. 9 in order to completely reduce the injection of hot electrons into the gate oxide film due to the drain voltage.

That is, as shown in FIG. 9, an n-type region 300 having an impurity concentration lower than that of the drain region is formed particularly around the n-type drain region 2030.

By doing this, the n-type drain region 20
3, the electric field strength at the surface under the gate insulating film of the drain junction is relaxed, and therefore carriers are trapped in the gate oxidation line by pot electrons. It is possible to reduce the proportion of

This results in completely preventing variations in the threshold voltage Vth of the MOSFET. In FIG. 9, parts having the same function as the structure shown in FIG. 5 described above are designated by the same reference numerals 11, and their explanations will be omitted.

The advantage of suppressing the deterioration of characteristics due to the hot electron effect will be explained based on the experimental results shown in the characteristic diagram of FIG. 1O.

The horizontal axis in Fig. 10 is the operating pressure V
. In order to observe the effect of hot electrons more markedly than if, a voltage in the range of 6 to tOV is applied to the SRAMIC which normally operates at 5.

On the other hand, the vertical line @ indicates the time during which the threshold voltage changes to a certain constant value due to the hot electron effect as the deterioration time. Characteristic (a) shows the experimental results when the 1niD region is not formed, and characteristic (b) shows the experimental results when the n- region is formed around the n+ type drain region.

As is clear from this experimental result, the structure according to the present invention shown in FIG. 9 has the following effects as shown by the arrows: 1.
It is possible to improve the characteristic deterioration time by 5 to 2 orders of magnitude. The same as above means that even if the SRAMIC is operated for a long time with a normal 5V voltage source, it is difficult for the characteristics to fluctuate.

In the structure shown in FIG. 9, the n-type region 300 is formed by phosphorus ion PI in the step shown in FIG.
It can be easily formed by implanting arsenic (A8) ions by ion implantation after i-implantation.

Furthermore, the present invention is not limited to the implementation array of SRAMI O described above, but is applicable to the N-channel type M shown in FIG.
The present invention can also be applied to a DRAMIO in which M is a one-element type memory cell having an O8FBT701 and a capacitor C5.

[Brief explanation of the drawing]

Figure 1 shows the construction cost when the present invention is applied to all SRAMICs.
Schematic diagram for explaining the layout of. FIG. 2 is a circuit diagram of a memory cell used in the EIRAMIG shown in FIG. FIG. 3 shows a gate floor circulation circuit according to the invention for use in the input stage of the peripheral circuit of FIG. FIG. 4 shows a gate protection circuit according to the invention for use in the output stage of the peripheral circuit of FIG. FIG. 5 is a structural diagram of an N-channel type layer OE'+FET according to the present invention shown in FIG. 1 and used in the fcS RA MIC. FIG. 6 is a structural diagram of a transistor forming a memory cell portion of the IC shown in FIG. 1. FIGS. 7(A) to 7(N) are cross-sectional views of ICs in each domain for explaining the manufacturing process for obtaining a structure according to the present invention. FIG. 8 and FIG. 10 are 1ζth characteristic diagrams explaining the characteristics of the SRAMIC according to the present invention. FIG. 9 shows an N-channel MO8FE-T according to the present invention.
A structural diagram showing the implementation of the pond. FIG. 11 is a circuit diagram of a RAMIC memory cell to which the present invention is applicable. 1... IC substrate, 100... memory array section, l
Ol...X decoder, 102...Y decoder, 10
3...Readout φ column, built-in circuit, 111~(n m...
External terminal, 201...p type substrate, 202...n+ type drain region, 203...n type drain region, 204,
206゜208.209...Insulating film, 205...Goo 1-electrode, 211...P type region, 300...n
- type area, 4...input stage circuit, 401 to 403, 50
1,502゜601~604...N channel type MO
8FET. 5...Output stage circuit. Fig. 1 Fig. 2 Cc Fig. 3 Fig. 4 Fig. 1i&, Fig. 5/Fig. 6 Fig. 7 and 8) Fig. 7 Fig. 7 (D2 (J) (K> Fig. 7/θ/ 8 Figure τ し方愛'/E Vcc CV) Figure 9 Figure 10 Figure 11

Claims (1)

[Scope of Claims] (2) In a semiconductor integrated circuit device in which a plurality of insulated gate type turtle field effect transistors are arranged on a semiconductor substrate, at least one of the source l or drain region of at least one insulated gate type turtle field effect transistor is provided. 1. A semiconductor integrated circuit device, characterized in that a semiconductor region is formed on a lower portion of a semiconductor substrate in the same four-cornered shape as the semiconductor substrate, and has an impurity concentration higher than that of the semiconductor substrate. 2. In a method for manufacturing a semiconductor integrated circuit device in which a plurality of insulated gate field effect transistors are disposed on a semiconductor substrate, the source I of at least one insulated gate field effect transistor is formed by forming the source I of the at least one insulated gate field effect transistor before the step of forming a drain region. Or, the lower part of at least one of the drain regions has the same conductivity type as the semiconductor substrate and has an impurity f! Is it a process of forming a semiconductor region with a high I concentration in the semiconductor substrate and a high J concentration? A method for manufacturing a semiconductor integrated circuit device, comprising: