JPH01304765A - Mixed-type semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve electrostatic breakdown strength and electric reliability by providing first and third semiconductor regions of high impurity density to reduce junction strength of a diode element. CONSTITUTION:In a mixed semiconductor integrated circuit device having an electrostatic breakdown preventive circuit, a diode element D (a drain region of clamp MISFET Qc) is provided whose electrostatic breakdown prevention circuit is formed by a p<+>-type semiconductor region 3 of buried-type high impurity density which is buried between a semiconductor substrate 1 and an epitaxial layer 4, and an n<+>-type semiconductor region 19 of high impurity density which is provided by bringing the bottom into contact with the p<+>-type semiconductor region 3 at a main phase of the epitaxial layer 4. Therefore, junction strength of the diode element D can be reduced by bringing a buried- type semiconductor region 3 of a high impurity density into contact with the n<+>-type semiconductor region 19 of a high impurity density, thus allowing reduction of electrostatic breakdown of an input circuit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a mixed type semiconductor integrated circuit device, and in particular to a technique that is effective when applied to a mixed type semiconductor integrated circuit device having an electrostatic breakdown prevention circuit. be.

[Conventional technology]

The present inventor is developing a mixed semiconductor integrated circuit device having a complementary MISFET (CMO5) and a bipolar transistor. This mixed type semiconductor integrated circuit device has an electrostatic breakdown prevention circuit inserted between an external terminal (ponding pad) and an input stage circuit.

The electrostatic breakdown prevention circuit consists of resistive elements and MISFE for clamps.
It is composed of T.

The resistance element is composed of an n-type semiconductor region (diffusion layer resistance). One end of the resistance element is connected directly to an external terminal,
The other end is connected to the input stage circuit with the drain region of the clamp MISFET interposed therebetween. The resistor element is configured to absorb an excessive current (transient current) input to an external terminal that may cause electrostatic damage to the substrate side by blunting or breaking down.

The clamping MISFET is composed of an n-channel, and its drain region is integrally formed on the other end side of the resistor element. The source region and gate electrode of the clamping MISFET are each connected to a reference potential. M for clamp
The I5FET is configured to absorb an excessive current passing through the resistive element into the substrate side by surface breakdown or breakdown. MI for clamp
The breakdown voltage (junction breakdown voltage) of the SFET is configured to be lower than the breakdown voltage of the gate insulating film of the complementary MISFET of the input stage circuit.

The electrostatic breakdown prevention circuit configured as described above blunts the excessive current input to the external terminal with a resistive element and clamps it with a clamping MISFET.

The structure is such that breakdown (electrostatic breakdown) of the gate insulating film of the input stage circuit can be prevented. Further, the electrostatic breakdown prevention circuit includes a resistance element, a MI 5F for clamping
Since each of the ETs can be formed in the same manufacturing process as MISFETs such as internal circuits, it is possible to reduce the number of manufacturing processes of the mixed semiconductor integrated circuit device.

Note that a semiconductor integrated circuit device having an electrostatic breakdown prevention circuit is described in, for example, Japanese Patent Laid-Open No. 61-53761.

[Problem to be solved by the invention]

The mixed semiconductor integrated circuit device currently being developed by the present inventor is highly integrated in accordance with the law of proportional reduction, and is constructed using a manufacturing process with a minimum processing size of 0.8 [μm]. In other words, the gate length of the gate electrode of the MISFET, which is most often microfabricated, and the width of the wiring are configured to be 0.8 [μm]. When such a manufacturing process is adopted, the gate insulating film of the MISFET in the internal circuit and the input stage circuit is formed to be a thin film of about 200 mm in accordance with the above-mentioned proportional reduction law. The dielectric strength voltage of this thinned gate insulating film is about 19 [V]. However, in order to reduce the increase in parasitic capacitance, etc., the impurity concentration of the semiconductor substrate (actually the well region) that forms the resistive element of the electrostatic breakdown prevention circuit and the drain region of the clamp MI S FET is determined according to the proportional reduction law. It's not expensive. This is the pn junction breakdown voltage (
This means that the breakdown voltage (breakdown voltage) does not substantially change as the level of integration increases. This junction breakdown voltage is approximately 20[V
] It is about . In other words, the complementary MISFE of the input stage circuit
The dielectric breakdown voltage of the gate insulating film of T is apparently smaller than the junction breakdown voltage of the resistance element of the electrostatic breakdown prevention circuit and the clamping MISFET. For this reason, when an excessive current is input to the external terminal, the input stage circuit frequently suffers from static electricity damage before the static electricity damage prevention circuit absorbs the excessive current.

An object of the present invention is to provide a technique that can reduce electrostatic damage and improve electrical reliability in a mixed semiconductor integrated circuit device having an electrostatic damage prevention circuit.

Another object of the present invention is to provide a technique that can achieve the above object and reduce the number of manufacturing steps.

Another object of the present invention is to provide a technique capable of reducing electrostatic damage in a mixed semiconductor integrated circuit device having an electrostatic damage prevention circuit.

Another object of the present invention is to achieve the other objects mentioned above, and
The objective is to provide a technology that can reduce the number of manufacturing steps.

Another object of the present invention is to provide a technology that can reduce electrostatic damage, improve the degree of integration, and reduce the number of manufacturing steps in a mixed semiconductor integrated circuit device having an electrostatic damage prevention circuit. It is in.

Another object of the present invention is to have an electrostatic breakdown prevention circuit and to
An object of the present invention is to provide a technology that can reduce electrostatic damage, improve the degree of integration, and reduce the number of manufacturing steps in a mixed semiconductor integrated circuit device having a RAM (dynamic random access memory).

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a mixed semiconductor integrated circuit device having an electrostatic breakdown prevention circuit, the electrostatic breakdown prevention circuit includes a first conductivity type first semiconductor region of a buried type with a high impurity concentration embedded in a semiconductor substrate. , the first
a second semiconductor region of the first conductivity type with a low impurity concentration and provided with its bottom surface in contact with the semiconductor region; and a third semiconductor region of the second conductivity type with a high impurity concentration provided on the main surface of the second semiconductor region. It has a diode element configured with a region.

(2) The first semiconductor region of the means (1) is formed in the same manufacturing process as the isolation region of the bipolar transistor, the second semiconductor region is formed in the same manufacturing process as the well region of the complementary MISFET, and the third semiconductor region is formed in the same manufacturing process as the well region of the complementary MISFET. The semiconductor region is complementary type M
It is formed in the same manufacturing process as the source region and drain region of the ISFET.

(3) In a mixed semiconductor integrated circuit device having an electrostatic breakdown prevention circuit, the electrostatic breakdown prevention circuit includes a first conductivity type first semiconductor region of a buried type with a high impurity concentration embedded in a semiconductor substrate. , the first
The diode element includes a second semiconductor region of a second conductivity type with a high impurity concentration and whose bottom surface is in contact with the semiconductor region.

(4) The first semiconductor region of the means (3) is formed in the same manufacturing process as the isolation region of the bipolar transistor, and the second semiconductor region is the same as the potential raising semiconductor region of the buried collector region of the bipolar transistor. Formed during the manufacturing process.

(5) The second semiconductor region of the means (3) constitutes a drain region of a clamping MISFET of an electrostatic breakdown prevention circuit, and this second semiconductor region forms a gate electrode of the clamping MISFET and a sidewall spacer on its sidewall. This sidewall spacer is then formed by introducing impurities into a mask.

(6) The mixed semiconductor integrated circuit device of the means (3) is D
It has a RAM, and the source region or drain region of the memory cell selection MISFET of the memory cell of this DRAM is constituted by a third semiconductor region having a shallower junction than the second semiconductor region.

[For production]

According to the means (1), it is possible to reduce the junction breakdown voltage of the diode element by providing the first semiconductor region and the third semiconductor region with high impurity concentration, and therefore it is possible to reduce electrostatic damage in the input stage circuit. , it is possible to reduce the rise of impurities from the first semiconductor region with a high impurity concentration, and to reduce the electrical voltage such as the threshold voltage of the complementary MISFET provided on the semiconductor region in the same layer as the first semiconductor region. Variations in characteristics can be reduced. In other words, the mixed semiconductor integrated circuit device can improve the electrostatic breakdown voltage and the electrical reliability.

(2) By means (2), the first semiconductor region, the second semiconductor region, and the third semiconductor region can be formed in the steps of forming each of the complementary MISFET and the bipolar transistor, so that the mixed semiconductor The number of manufacturing steps for integrated circuit devices can be reduced.

(3) According to the means (3), it is possible to reduce the junction breakdown voltage of the diode element by providing the first semiconductor region and the second semiconductor region with high impurity concentration, thereby reducing electrostatic damage in the input stage circuit. I can do it.

(4) By means (4), the first semiconductor region and the second semiconductor region can be formed in the step of forming the isolation region of the bipolar transistor and the potential pulling semiconductor region, respectively, so that the mixed type The number of manufacturing steps for a semiconductor integrated circuit device can be reduced.

(5) By the means (5), the MI 5 for the clamp
Since the amount of impurity diffusion toward the channel formation region side of the second semiconductor region of the FET can be reduced by an amount corresponding to the sidewall spacer, the channel length of the clamping MISFET can be secured. In other words, MI for clamp
Since the short channel effect of the SFET can be reduced, the degree of integration of the mixed semiconductor integrated circuit device can be improved.

(6) The above means (6) has the effect of the above means (3) and can reduce the amount of impurity diffusion toward the channel formation region side of the third semiconductor region of the MlSFET for memory cell selection. Reduce channel effects,
The area occupied by the memory cell selection MISFET can be reduced, and the degree of integration of the mixed semiconductor integrated circuit device can be improved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a mixed semiconductor integrated circuit device that integrates complementary MISFETs and bipolar transistors and has an electrostatic breakdown prevention circuit and a DRAM.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

Embodiment I Embodiment I is a first embodiment of the present invention in which an electrostatic breakdown prevention circuit for a mixed semiconductor integrated circuit device is composed of a resistance element and a clamping MISFET.

A mixed semiconductor integrated circuit device which is Embodiment I of the present invention is shown in FIG. 1 (a sectional view of main parts).

As shown in FIG. 1, the mixed semiconductor integrated circuit device is composed of a base body formed of a p-type semiconductor substrate 1 made of single-crystal silicon and an n-type epitaxial layer 4 grown on the main surface of the p-type semiconductor substrate 1. There is. A bipolar transistor formation region Bip and a complementary MISFET formation region C are provided on the central main surface of the mixed semiconductor integrated circuit device to form an internal circuit.
MO8 and a DRAM forming area DRAM are provided.

Further, a peripheral circuit formation region AR is provided on the main surface of the peripheral portion of the mixed semiconductor integrated circuit device.

The complementary MISFET formation region CMO8 has a complementary type M
ISFET is arranged. Complementary MISFET is n
Channel MISFETQn and p-channel MISFET
It is composed of QP.

The n-channel MISFET Qn is formed on the main surface of the p-type well region 6 in a region surrounded by the field insulating film 7. The field insulating film 7 is formed of a silicon oxide film formed by oxidizing the main surface of the well region 6. Although not shown, a p-type channel stopper region is provided on the main surface of the well region 6 under the field insulating film 7 . Well region 6 is provided on the main surface of epitaxial layer 4 . The bottom surface of the well region 6 is in contact with a buried p-type semiconductor region 3 provided between the semiconductor substrate 1 and the epitaxial layer 4. This buried P゛ type semiconductor region 3 lowers the specific resistance value of the bottom surface of the well region 6,
It is configured to prevent parasitic thyristor operation peculiar to complementary MISFETs. The n-channel MISFE
TQn mainly includes well region 6, gate insulating film 12 . Gate electrode 13°; a pair of n-type semiconductor regions 14 and a pair of n-type semiconductor regions 21, which are source and drain regions;
It consists of

The well region 6 is used as a channel forming region. The gate insulating film 12 is formed of a silicon oxide film formed by oxidizing the main surface of the well region 6. Gate electrode 1
3 is composed of a composite film in which a polycrystalline silicon film and a high melting point metal silicide film are laminated on top of the polycrystalline silicon film. The gate electrode 13 is not limited to the above-mentioned composite film, but may be composed of a single layer polycrystalline silicon film, a high melting point metal film, or a composite film thereof. The gate electrode 13 is formed by a second layer gate wiring forming step in the manufacturing process.

The low impurity concentration A-type semiconductor region 14 is formed integrally with the high impurity concentration n-type semiconductor region 21, and is provided between the n-type semiconductor region 21 and the channel formation region. This n-type semiconductor region 14 is a so-called LDD (L
An n-channel MISFETQn with an extremely D oped rain) structure is configured. Za-shaped semiconductor region 14
is formed on the side of the gate electrode 13 in self-alignment therewith. The Go-type semiconductor region 21 with a high impurity concentration is formed on the side of the sidewall spacer 16 provided on the sidewall of the gate electrode 13 in self-alignment therewith.

A wiring 26 is connected to the Go-type semiconductor region 21, which is the source region and drain region of the n-channel MISFETQn, through connection holes 24 formed in the interlayer insulating films 17 and 23. n° type semiconductor region 21
and wiring 26 are connected with an n'-type semiconductor region 25 interposed therebetween. The n-type semiconductor region 25 is formed by introducing an n-type impurity (P or As) into the region defined by the contact hole 24. The n° type semiconductor region 25 is
The well region 6 and the wiring 26 are configured so as not to be short-circuited if the position of the connection hole 24 with respect to the n° type semiconductor region 21 is misaligned with the mask. The wiring 26 is composed of, for example, a composite film including a barrier metal layer and an aluminum film laminated thereon. As the barrier metal layer, for example, a transition metal silicide film such as MoSi2 or a transition metal nitride film such as TiN is used. As the aluminum film, an aluminum alloy film to which Cu or Si is added is used. The wiring 26 is formed by a first layer wiring forming step in the manufacturing process.

Among the complementary MISFETs, p-channel MI 5F
ETQp is formed on the main surface of type well region 5 in a region surrounded by field insulating film 7 . Well region 5 is provided on the main surface of epitaxial layer 4 . The bottom surface of the well region 5 is a buried n° type semiconductor region 2 provided between the semiconductor substrate 1 and the epitaxial layer 4.
is in contact with. Like the buried p-type semiconductor region 3, the buried type semiconductor region 2 lowers the specific resistance value of the bottom surface of the well region 5, and prevents the parasitic thyristor operation peculiar to complementary MISFETs. It is configured as follows. The p-channel MISFET QP mainly has a well region (
It is composed of a channel forming region) 5, a gate insulating film 12, a gate electrode 13, a pair of p-type semiconductor regions 15 serving as a source region and a drain region, and a pair of p°-type semiconductor regions 22. The p-channel MIS'FETQp has an LDD structure similar to the n-channel MIS'FETQp.

A wiring 26 is connected to the p-type semiconductor region 22, which is the source region and drain region of the p-channel MISFET Qp, through the connection hole 24 formed in the interlayer insulating films 17 and 23.
is connected.

A bipolar transistor Tr is arranged in the bipolar transistor formation region Bip. The bipolar transistor Tr is provided on the main surface of the semiconductor substrate 1 in a region surrounded by an isolation region. The isolation region includes a semiconductor substrate 1, a buried p° type semiconductor region 3. It is composed of a P-type well region 6 and a field insulating film 7. A buried p° type semiconductor region 3. which constitutes this isolation region. Each of the well regions 6 includes a buried p-type semiconductor region 3 and a well region 6 provided in a complementary MISFET formation region CMOS.
are formed in the same layer (same manufacturing process) as each of them. The bipolar transistor Tr is of an npn type and includes an n-type collector region, a p-type base region, and an n-type emitter region.

The n-type collector region includes a buried type semiconductor region 2 used as a buried type collector region, and a potential raising type semiconductor region 1 for raising the collector potential of the buried type collector region.
9 and an A-type well region 5 (or epitaxial layer 4). The buried n° type semiconductor region 2 is the buried n° type semiconductor region 2 of the complementary MI S FET forming region CMO8.
It is formed in the same layer (same manufacturing process) as the type semiconductor region 2. That is, the buried n° type semiconductor region 2 is provided between the semiconductor substrate 1 and the epitaxial layer 4. Similarly, the well region 5 is a complementary MISFET formation region CMO.
It is formed in the same layer (same manufacturing process) as the well region 5 of No. 8. The potential raising go-type semiconductor region 19 is the well region 5
The bottom surface is in contact with the buried n° type semiconductor region 2.

n ° type semiconductor region 1 for raising the potential of this n type collector region
9 is a connection hole 24 formed in interlayer insulating films 17 and 23.
A wiring 26 is connected through the connector.

The p-type base region is composed of a p-type semiconductor region 20 as an intrinsic base region and a p-type semiconductor region 22 as a graft base region. The p-type semiconductor region 20 and the P'-type semiconductor region 22 are integrally formed and provided on the main surface of the well region 5, respectively.

The p-type semiconductor region 22 serves as a graft base region.

It is formed in the same layer (in the same manufacturing process) as the P' type semiconductor region 22 which is the source region and drain region of the p-channel MISFET QP.

The p° type semiconductor region 22 of this p type base region has a wiring 2
6 is connected.

The n-type emitter region is composed of a Go-type semiconductor region 21. The n° type semiconductor region 21 is provided on the main surface of the P type semiconductor region 20, which is the intrinsic base region of the P type base region. The n° type semiconductor region 21 is the n-channel MIS.
It is formed in the same layer (in the same manufacturing process) as the n'-type semiconductor region 21 which is the source region and drain region of FETQn.

A wiring 26 is connected to the n° type semiconductor region 21 which is an n type emitter region.

In the DRAM formation region DRAM, a plurality of DRAM memory cells are arranged in rows and columns. The memory cell is constituted by a series circuit of a memory cell selection MISFET Qm and an information storage capacitive element C.

The memory cell selection MISFET Qm and the information storage capacitive element C are provided on the main surface of the p-type well region 6 in a region surrounded by the field insulating film 7.

The information storage capacitive element C mainly has a so-called planar structure in which an n° type semiconductor region 8 as a lower electrode, a dielectric film 9, and a plate electrode 10 as an upper electrode are laminated. The n° type semiconductor region 8 is provided on the main surface of the well region 6. The dielectric film 9 is formed of, for example, a silicon oxide film formed by oxidizing the main surface of the n'' type semiconductor region 8. Furthermore, the dielectric film 9 is made of a single layer silicon nitride film or a silicon oxide film. It may be formed of a composite film in which a silicon nitride film and a silicon nitride film are superimposed.The plate electrode 10 is formed of, for example, a polycrystalline silicon film.The plate electrode ai10 is not limited to this, but for example, the power supply voltage 1/2 Vcc is applied.The power supply voltage 1/2V, , is the power supply voltage Vcc, for example, the intermediate potential between the circuit operating voltage 5 [V] and the reference voltage V. For example, the ground potential of the circuit 0 [V], about 2. 5 [V].The plate electrode 10 is formed in the first layer gate wiring formation step in the manufacturing process.The information storage capacitor C is connected to the n-type semiconductor region 8 as the lower electrode. A p type semiconductor region having a higher impurity concentration than the well region 6 is provided along the outer periphery, and the pn of the n + type semiconductor region 8 is provided.
The junction capacitance may be increased. This increase in the pn junction capacitance increases the amount of charge storage (the amount of charge that becomes information) of the information storage capacitive element C, and can reduce the occurrence of α-ray soft errors. .

Further, the p type semiconductor region 3 is an n type semiconductor region where electrons of the electron-hole pairs generated when α rays are incident on the memory cell are the lower electrode of the information storage capacitive element C'. By forming a potential barrier to prevent the α-rays from flowing into the rays 8, it is possible to reduce the occurrence of α-ray soft errors. In this embodiment, the buried P' type semiconductor region 3 existing over the entire surface under the memory cell forms a potential barrier against electrons, thereby reducing the occurrence of α-ray soft errors.

M I S F E T Q m for memory cell selection is
mainly.

Well region 6 (channel formation region), gate insulating film 12
, gate electrode 13. It is composed of a pair of n-type semiconductor regions 14 that are a source region and a drain region.

The gate electrode 13 of the memory cell selection MISFETQm is configured integrally with a word line (WL) 13 extending in the gate width direction. The word line 13 is connected to a plate electrode 10 on the field insulating film 7 and with an interlayer insulating film 11 interposed therebetween.
It is configured to extend over the top.

The n-type semiconductor region 14, which is a source region and a drain region, is an n-channel Ml5FET of a complementary MISFET.
Each of the substantial source and drain regions of Qn (n+
It has a lower impurity concentration and a shallower junction than the type semiconductor region 21). In other words, MIS for memory cell selection
In the FETQm, the amount of impurity diffusion of the n-type impurity toward the channel formation region side of the n-type semiconductor region 14, that is, the lateral diffusion distance can be made smaller than that of the n1-type semiconductor region 21.

Memory cell selection MISFE T configured in this way
Since Q m can ensure a sufficient channel length and reduce the occurrence of short channel effects, it is possible to reduce the memory cell area and achieve high integration of the DRAM. The specific resistance value of the channel forming region of the memory cell selection MISFET Qm is originally high, and even if the specific resistance value of the source region and the drain region are each composed of n-type semiconductor regions 14 with low impurity concentration and becomes slightly high, the memory cell The information write operation speed and information read operation speed of the device hardly change.

One n-type semiconductor region 14 of the memory cell selection MISFETQm is connected to the n-type semiconductor region 8 which is the lower electrode of the information storage capacitive element C. M for memory cell selection
The other n-type semiconductor region 14 of ISFETQm is connected to a data line (DL) 26 through a connection hole 24 formed in interlayer insulating films 17 and 23. The other n-type semiconductor region 14 and data line 26 are connected with an n'-type semiconductor region 25 interposed therebetween.

In the DRAM forming area DRAM, a shunt word line (W
L) 29 extends in a direction intersecting the data line 26. Although not shown, the shunt word line 29 is connected to the word line 13 in a predetermined region via an intermediate conductive film (26) formed in the first layer wiring forming step. In other words, the shunt word line 29 is configured to reduce the resistance value of the word line 13. The shunt word line 29 is formed of, for example, an aluminum film or an aluminum alloy film.

The shunt word line 29 is formed by a second layer wiring forming step in the manufacturing process.

On the input side of the peripheral circuit formation area AR, external terminals (
A bonding pad (BP) 29, an input stage circuit (■) and an electrostatic breakdown prevention circuit (■) are arranged. As shown in Figure 2, the external terminal BP on the input side is connected to the electrostatic damage prevention circuit.
It is connected to the input stage circuit (2) through the intervening.

The input stage circuit (2) is composed of an inverter circuit consisting of complementary MISFETs. This complementary MISFET is Rin1
It has substantially the same structure as the complementary MISFET that constitutes the internal circuit shown in the figure. The terminal P1 is a connection terminal to the internal circuit, and the terminal P2 is a control signal terminal that defines the operation of the input stage circuit (2). The external terminal BP is connected to an n-channel MISFETQn and a p-channel MISFET of the input stage circuit I.
The respective gate electrodes (13) of SFETQp are connected through an electrostatic breakdown prevention circuit (2).

The electrostatic breakdown prevention circuit (2) is mainly composed of a resistance element R and a clamp MISFETQc.

One end of the resistance element R is connected to an external terminal BP.

The other end of the resistance element R is the drain region (19) of the clamp MISFETQc and the complementary MISF of the input stage circuit I.
It is connected to each gate electrode (13) of the ET. A source region (21) and a gate electrode (13) of the clamp MISFET Q-c are each connected to a reference voltage V.

The clamping MISFET Qc is provided on the main surface of the p° type well region 6 in a region surrounded by the field insulating film 7, as shown in FIG. The clamping MISFET Qc mainly includes a well region 6 (channel forming region), a gate insulating film 12, a gate electrode 13, an n-type semiconductor region 14 serving as a source region, and an n'
It is composed of a - type semiconductor region 21 and an n.type semiconductor region 19 which is a drain region.

The n-type semiconductor region 14 and the n-type semiconductor region 21, which are the source regions of the clamp MISFETQc, are connected to the n-channel MISFETQ.
The same layer (same manufacturing process) as the n-type semiconductor region 14 and the 1-type semiconductor region 21, which are the source region and drain region of n.
It is formed of. The n-type semiconductor region 19, which is the drain region of the clamping MISFETQc, is provided on the main surface of the well region 6, and its bottom surface is configured to be in contact with the buried p"-type semiconductor region 3.

At the bottom of the well region 6, there is provided a buried p-type semiconductor region 3 formed in the same layer (same manufacturing process) as the well region 6 in which the complementary MISFET n-channel MISFETQn is formed. . The n-type semiconductor region 19 is in the same layer (same manufacturing process) as the n-type semiconductor region 19 for raising the potential of the n-type collector region of the bipolar transistor Tr.
It is formed of. The n◆-type semiconductor region 19 for raising the potential of the bipolar transistor Tr is formed by a junction deep enough to contact the buried n゛-type semiconductor region 2 (buried collector region) from the surface of the epitaxial layer 4. Therefore, n°
The type semiconductor region 19 likewise consists of a deep junction.

The n-type semiconductor region 19 is the n-channel MISFET.
It is constituted by a deeper junction than the n.sup.-type semiconductor region 21 and the n.sup.-type semiconductor region 25, which are the source region and drain region of Qn, respectively. High impurity concentration n-type semiconductor region 1 which is the drain region of this clamping MISFETQc
A parasitic diode element is formed at the portion where the buried p-type semiconductor region 8 (or well region 6) with a high impurity concentration contacts.

Resistance element R is for clamp M I S F E T Q
It is composed of an n' type semiconductor region 19 which is a drain region of c.

The external terminal BP is formed in the second layer wiring formation step (wiring 29) in the manufacturing process (it may also be formed in the first layer wiring formation step, that is, the wiring 26). External terminal (BP)
Reference numeral 29 denotes an n-type semiconductor region which is once connected to the wiring 26 through a contact hole 28 formed in the interlayer insulating film 27, and which is the drain region of the clamp MISFETQc, with the wiring 26 interposed therebetween. It is connected to 19.

On the external terminal (BP) 29, the shunt word line 29
A passivation film 30 is provided over the entire surface of the substrate including the top and wiring 29, respectively. Passivation film 30
An opening 31 is provided above the external terminal BP. Although this opening 31 is not shown, it is configured so that a bonding wire can pass therethrough. The bonding wire is configured to connect the external terminal BP of the mixed semiconductor integrated circuit device to an external terminal (for example, an inner lead or a terminal of a wiring board). The bonding wires are connected by, for example, a ball wedge bonding method.

Next, a method for manufacturing a mixed type semiconductor integrated circuit device configured as described above will be briefly explained using FIGS. Explain.

First, a p' type semiconductor substrate 1 made of single crystal silicon is prepared. The semiconductor substrate 1 is formed with a low impurity concentration and a resistance value of, for example, about 10 to 15 Ω.

Next, n-type impurities are selectively introduced into the main surface of the semiconductor substrate 1 in each of the p-channel MISFET QP formation region and the bipolar transistor formation region Bip of the complementary MISFET formation region CMO3. The n-type impurity is introduced by using sb having a high impurity concentration of about 1014 to 10" [atows/aJ], for example, by ion implantation with an energy of about 90 to 110 [KeV].

Next, steam oxidation at about 1000 ["C] is applied,
The n-type impurity is stretched and diffused to form an n-type semiconductor region 2A. This n-type semiconductor region 2A is formed by the same manufacturing process as that for forming the n-type semiconductor region 2A.
A silicon oxide film 32 having a thickness of about 2,000 to 4,000 [people] is formed on A.

Next, the n-channel MISFETQn formation region of the complementary MISFET formation region CMO8, the DRAM formation region DRA
M, p-type impurities are selectively introduced into the main surface of the semiconductor substrate 1 in the peripheral circuit formation region AR and isolation region. This p-type impurity is introduced using the silicon oxide film 32 as a mask for impurity introduction. That is, the p-type impurity is introduced into the n'-type semiconductor region 2A in a self-aligned manner. The p-type impurity is, for example, 10'' to 1014[ato
ms/ci using B of 40 to 60 [KeV]
It is introduced by ion implantation method with a certain amount of energy.

Next, heat treatment is performed at approximately 1000[°C], and as shown in FIG.
A type semiconductor region 3A is formed. In addition, this heat treatment
Damage to the main surface of the semiconductor substrate 1 caused by the introduction of the n-type impurity and the introduction of the p-type impurity described above can be recovered.

Next, the silicon oxide film 32 on the main surface of the semiconductor substrate 1 is removed.

Next, an n'' type epitaxial layer 4 is grown on the main surface of the semiconductor substrate 1. The epitaxial layer 4 is made of, for example, 2
It is formed with a low impurity concentration having a resistance value of about 4 [Ω]] and a film thickness of about 1.5 to 1.8 cm]. While forming this epitaxial layer N4, the semiconductor substrate 1
The respective impurities of the n'-type semiconductor region 2A and the p'-type semiconductor region 3A formed on the main surface of are diffused into the epitaxial layer 4 (rising up), and the buried n'-type semiconductor region 2 is
And a buried p' type semiconductor region 3 is formed.

Next, n-type impurities are selectively introduced into the main surface portion of the epitaxial layer 4 in each of the p-channel MISFET Qp formation region and the bipolar transistor formation region Bip of the complementary MISFET formation region CMO8. The n-type impurity is, for example, 1012[at.

using P with a low impurity concentration of about 120~
It is introduced by an ion implantation method with an energy of about 130 [KeV].

Next, steam oxidation is performed at a temperature of about 900 to 000['C], and the n-type impurity is stretched and diffused to form an n-type well region 5. A silicon oxide film having a thickness of about 1000 to 1500 [layers] is formed on this n-type well region 5 by the same manufacturing process as that for forming this n-type well region 5.

Next, the n-channel MISFET Qn formation region of the complementary MISFET formation region CMO8, the DRAM
In the formation region DRAM, the peripheral circuit formation region AR, and the isolation region, p-type impurities are selectively introduced into the main surface portion of the epitaxial layer 4. This p-type impurity is introduced using the silicon oxide film on the n-type well region 5 as a mask for impurity introduction. In other words.

The p-type impurity is introduced into the n°-type well region 5 in a self-aligned manner. The P-type impurity is 1, for example, 10" [ato
Using a BF of about ms/cd, 50 to 70 [K
e Introduce by ion implantation method with energy of about Vl.

Next, heat treatment is performed at about 1000 to 1200 ['C] to stretch and diffuse the p-type impurity to form a p-type well region 6.

Next, as shown in the fourth @, n” between the element formation regions.
A field insulating film 7 is selectively formed on the main surface of the type well region 5 and the main surface of the p-type well region 6, respectively. The field insulating film 7 is formed of a silicon oxide film having a thickness of, for example, 5,000 to 6,000 C by performing steam oxidation at about 1,000 ['C] using an oxidation-resistant mask such as a silicon nitride film. Although not shown, a p-type channel stopper region is formed under the field insulating film 7 of the p"-type well region 6. This p-type channel stopper region is formed, for example, before the field insulating film 7 is formed. It can be formed by selectively introducing a p-type impurity and stretching and diffusing this p-type impurity in a heat treatment for forming the field insulating film 7.

Next, in the DRAM forming region DRAM, n-type impurities are selectively introduced into the main surface of the p-type well region 6 to form an n-type semiconductor region 8. This n-type semiconductor region 8 forms the lower electrode of the information storage capacitive element C. The n4 type semiconductor region 8 is made of As with a high impurity level of about 1014 [atoms/d1, for example, and is made of 110-130EK e
It is formed by introducing an ion implantation method with an energy of approximately Vl.

Next, in the DRAM forming area DRAM.

A dielectric film 9 is formed on at least the main surface of the square-shaped semiconductor region 8.
form. The dielectric film 9 is formed of a silicon oxide film formed by steam oxidation, for example, and has a thickness of about 80 to 100 [layers].

Next, as shown in FIG.
In this step, a plate electrode 10 is formed on the dielectric film 9 and the field insulating film 7, that is, on the entire surface of the memory cell array except for the region where the memory cell selection MISFET Qm is formed. The plate electrode 10 is used as an upper electrode of the information storage capacitive element C. The plate electrode 10 is, for example, a CV
It is formed from a polycrystalline silicon film deposited by the D method, and has a
000 [formed with a film thickness of about the same thickness as a human body. This polycrystalline silicon film is doped with an n-type impurity such as P or As to reduce the resistance value. The polycrystalline silicon film is formed in the first layer gate wiring formation step in the manufacturing process. Further, in order to reduce the step shape, the end portion of the plate electrode 10 is formed with an inclination. By forming this plate electrode 10, the information storage capacitive element C of the DRAM memory cell is completed.

Next, an interlayer insulating film 11 is formed on the surface of the plate electrode 10 of the information storage capacitive element C. The interlayer insulating film 11 is
For example, a silicon oxide film formed by oxidizing the surface of a polycrystalline silicon film is used, and the film thickness is about 2,500 to 3,500 [layers].

Next, the n-type well region 5 which becomes the MISFET formation region
Impurities for adjusting the threshold voltage (vth) are introduced into the entire surface of the substrate including the main surface of the p-type well region 6 and the main surface of the p-type well region 6, respectively. This impurity is, for example, 1012 [atoms/a
B is introduced by an ion implantation method with an energy of about 30 to 40 K e V using B of about Since 11 serves as a mask for impurity introduction, the impurity is not introduced.

Next, the n-type well region 5 which becomes the MISFET formation region
A gate insulating film 12 is formed on the main surface of the p-type well region 6 and on the main surface of the p-type well region 6. The gate insulating film 12 is formed of a silicon oxide film formed by steam oxidation, for example, and has a thickness of approximately 200 [people].
It is formed with a film thickness of about 100%.

Next, as shown in FIG. 6, a gate voltage ti13 is formed on the gate insulating film 12. The gate electrode 13 is formed of, for example, a composite film in which a polycrystalline silicon film and a WSi film are laminated thereon. The lower layer polycrystalline silicon film is deposited, for example, by the CVD method, and is formed to have a film thickness of about 1500 to 2500 mm. An n-type impurity such as P or As is introduced into this polycrystalline silicon film to reduce the resistance value. The WSi,a film is deposited, for example, by sputtering or CVD, and
It is formed with a film thickness of about 3,500 [people]. This WSi,
The film is heat treated to densify and remove etching damage. Along with the step of forming the gate electrode 13, a word line (W L ) 13 extending over the interlayer insulating film 11 and the field insulating film 7 is formed in the DRAM forming region DRAM. The gate electrode 13 and the word line 13 are formed in a second layer gate wiring formation step in the manufacturing process.

Next, complementary MISFET formation region CMO3 (7) n-channel MISFETQn formation region, DRAM formation region D
MISFETQm formation region 1 for RAM memory cell selection
In each of the clamping MISFETQc formation regions of the peripheral circuit formation region AR, an n-type semiconductor region 14 is formed on the main surface of the p'' type well region 6. In addition to forming MISFETQc, the source region and drain region of MISFETQm for memory cell selection are also formed.
atoms/a! Using P in a low impurity process of about 1,
The 6n-type semiconductor region 14, which can be formed by introducing an ion implantation method with an energy of about 50 to 70[K e Vl, is formed by introducing an n-type impurity using the gate electrode 13 and the field insulating film 7. , is formed in self-alignment with respect to it. In regions where n-type impurities are not introduced, an impurity introduction mask such as a photoresist film is formed during the introduction.

By forming this n-type semiconductor region 14, a memory cell selection MISFETQm is completed, and a DRAM memory cell is completed.

Next, in the P channel MISFET QP formation region of the complementary MISFET formation region CMO8, as shown in FIG.
form 5. The P-type semiconductor region 15 has an LDD structure.
Form channel MI 5FETQp. The p-type semiconductor region 15 is formed using BF2 with a low impurity concentration of, for example, 1013 [atoms/aJ], and has a concentration of 40 to 60 [K e
It can be formed by introducing an ion implantation method with an energy of about Vl. Since the p-type impurity is introduced using the gate electrode 1413 and the field insulating film 7, the p-type semiconductor region 15 is formed in self-alignment therewith. In regions where p-type impurities are not introduced, an impurity introduction mask such as a photoresist film is formed during the introduction.

Next, as shown in FIG. 8, sidewall spacers 16 are formed on each sidewall of the gate electrode 13. The sidewall spacer 16 can be formed, for example, by subjecting a silicon oxide film deposited by CVD and having a thickness of about 4,000 to 5,000 µm to anisotropic etching such as RIE. The thickness of the gate electrode 13 of the sidewall spacer 16 in the gate length direction is defined by the thickness of the deposited silicon oxide film and the amount of etching. This sidewall spacer 16 is formed in self-alignment with the gate electrode 13.

Next, an impurity introduction mask 33 is formed over the entire surface of the substrate including over the gate electrode 13 and the word line 13.

The impurity introduction mask 33 forms a mask for impurities introduced in subsequent steps. Impurity introduction mask 3
3 is formed of, for example, a photoresist film.

Next, the formation region of the n-type semiconductor region for raising the potential of the bipolar transistor formation region Bip, and the peripheral circuit formation region A.
An opening 18 is formed in the impurity introduction mask 33 in the formation region of the drain region of the R clamping MISFET Qc.
form.

Next, mainly using the impurity introduction mask 33, as shown in FIG. 9, within the region defined by the opening 18,
An n-type impurity is introduced into the main surface of the n-type well region 5 and the main surface of the P"-type well region 6, and is applied to the semiconductor region 19 for raising the potential of the bipolar transistor Tr and the drain region of the clamping MISFET Qc. A certain n' type semiconductor region 19 is formed.

In other words, the n-type semiconductor region 19, which is the drain region of the clamping MISFET QC, is the bipolar transistor T.
It is formed by the same manufacturing process as the n' type semiconductor region 19 for raising the potential of r. Potential raising n-type semiconductor region 1
9. Each of the nj type semiconductor regions 19 has, for example, 1015
Using P (or As or sb) with a high impurity concentration of ~10'' [atoms/a & co, 70 ~ 90 [K e
It can be formed by introducing an ion implantation method with an energy of about V. Each of the n1-type semiconductor region 19 and the n-type semiconductor region 19 for raising the potential is heat-treated at a temperature of about 900 to 1000 ["C] after introducing an n-type impurity, and the n-type impurity is heated to a depth of about 1 cm". The bottom surface of the potential pull-up semiconductor region 19 is formed so as to be in contact with the buried n-type semiconductor region 2.At the same time, the clamping M The bottom surface of the n-type semiconductor region 19, which is the drain region of ISFETQc, is a buried p44
It is formed so as to be in contact with the mold semiconductor region 3. By forming the n.type semiconductor region 19, the resistor element R and diode element R of the electrostatic breakdown prevention circuit (2) are completed.

After this, the impurity introduction mask 33 is removed.

Next, in the formation region of the base region of the bipolar transistor Tr, as shown in FIG. 10, a p-type semiconductor region 20 is formed on the main surface of the n°-type well region 5. P-type semiconductor region 20 is used as an intrinsic base region. The p-type semiconductor region 20 can be formed by introducing B using an ion implantation method with an energy of about 30 to 40 [K e V ] using about 10'' [atoIms/aJ].

Next, the n-channel MISFET Qn formation region of the complementary MISFET formation region CMO3 and the peripheral circuit formation region AR
In each of the formation regions of the clamping MISFET QQ, an n" type semiconductor region 2 is formed on the main surface of the p- type well region 6.
At the same time, an n° type semiconductor region 21 is formed on the main surface of the p type semiconductor region 20 in the emitter region formation region of the bipolar transistor formation region Bip.

The former n-type semiconductor region 21 is an n-channel MI 5F.
It is used as a source region and a drain region of ETQn, and is also used as a source region of MISFETQQ for clamping. The latter n4 type semiconductor region 21 is used as an emitter region of the bipolar transistor Tr. The n4 type semiconductor region 21 has, for example, 101s to 10
It can be formed by using As with a high impurity concentration of about '@[a'toms/d] and introducing it by an ion implantation method with an energy of about 70 to 90 [KeV]. The n-type semiconductor region 21 has a thickness of, for example, 0.2 to 0.4[
The junction depth (χj) is on the order of [μm]. This n
- By the step of forming the type semiconductor region 21, the complementary type M
ISFET n-channel M I S F E T Q
n, M I S F for clamping electrostatic breakdown prevention circuit■
Each of E T Q c is completed.

Next, in the p-channel MISFET Qp formation region of the complementary MISFET formation region CMO3.

As shown in FIG. 11, a p''' type semiconductor region 22 is formed on the main surface of the n-type well region 5, and a main part of the p type semiconductor region 20 is formed in the base region forming region of the bipolar transistor forming region Bip. A p-type semiconductor region 22 is formed on the surface.The former p-type semiconductor region 22 is
They are used as the source region and drain region of the channel MISFET QP. The latter p type semiconductor region 22
is used as the graft base region of the bipolar transition transistor. The p type semiconductor region 22 has, for example, 10
It can be formed by using BF2 with a high impurity concentration of about 1' [atoms/all] and introducing it by an ion implantation method with an energy of about 70 to 90 [K e V ]. The P9 type half region 22 is, for example, 0.3 to 0.
．． The junction is formed with a depth of about 6 [μm]. By the process of forming this p-type semiconductor region 22, complementary MI
The SFET p-channel MISFETQp and bipolar transistor Tr are each completed.

Next, the interlayer insulating film 23, which forms an interlayer insulating film 23 over the entire surface of the substrate, is formed of, for example, a composite film of a silicon oxide film and a BPSG film deposited thereon. The silicon oxide film is 9 e.g. C
It is deposited by the VD method to a film thickness of about 1,500 to 2,500 mm. The silicon oxide film is configured to prevent P and B from leaking from the upper BPSG film to the semiconductor element side. The BPSG film is deposited, for example, by the CVD method,
6,000 to 8,000 [formed with a film thickness of about the same thickness as that of a human. This BPSG film is configured to be subjected to glass flow after its deposition to flatten the surface of the interlayer insulating film 23. The glass flow is performed at a high temperature of about 900 to 1000 ['C], which also serves as densification.

Next, the n-type semiconductor region 21, the potential-raising n-type semiconductor region 19, the n-type semiconductor region 14 . In each region of the I-type semiconductor region 22, the interlayer insulating films 23 and 17 are removed to form a contact hole 24. As shown in FIG. 12, interlayer insulating films 23 and 17 are formed on the main surfaces of the n-type semiconductor region 21, the potential-raising n-type semiconductor region 19, and the n-type semiconductor region 14, respectively. An n-type impurity is introduced through the connection hole 24 to form a Go-type semiconductor region 25. n°
The type semiconductor region 25 is, for example, 10” [atoIIIs/
It can be formed by using P with a high impurity concentration of about [ai] and introducing it by an ion implantation method. This n-type impurity is activated by heat treatment (this heat treatment is
(The BPSG film of the interlayer insulating film 23 can be further caused to glass flow).

Next, as shown in FIG. 13, a wiring 26 (including the data line 26) is formed on the glabella insulating film 23 so as to connect to a predetermined area through the connection hole 24. The wiring 26 is
For example, a composite film is formed by laminating MoSi and an aluminum alloy film to which Cu or Si is added. MOSi2 is deposited by sputtering, for example, and
It is formed with a film thickness of about 200 [persons]. The aluminum alloy film is deposited by sputtering, for example, and
00 [Form to have a film thickness comparable to that of a human. The wiring 26 is formed in the first layer wiring forming step in the manufacturing process.

Next, an interlayer insulating film 27 is formed over the entire surface of the substrate including on the wiring 26. The interlayer insulating film 27 is, for example, a silicon oxide film deposited by plasma CVD method, a silicon oxide film coated by SOG method,
A composite film is formed by sequentially stacking silicon oxide films deposited by plasma CVD.

Next, a portion of the interlayer insulating film 27 on a predetermined wiring 26 is removed to form a connection hole 28. The connection hole 28 is formed by a combination of anisotropic etching and isotropic etching in order to improve the step coverage of the upper layer wiring.

Next, a wiring 29 (including the external terminal BP) extending over the interlayer insulating film 27 is formed so as to be connected to a predetermined wiring 26 through the connection hole 28. The wiring 29 is formed of, for example, the same aluminum alloy film as described above.

The wiring 29 is formed by a second layer wiring forming step in the manufacturing process.

Next, a passivation film 30 is formed on the entire surface of the substrate including on the wiring m29. The passivation film 30 is formed of, for example, a composite film in which a silicon oxide film deposited by a CVD method and a silicon nitride film deposited by a plasma CVD method are laminated thereon.

Then, the portion of the passivation film 30 on the wiring 29 used as the external terminal BP is removed and an opening 31 for bonding is formed, thereby completing the mixed semiconductor integrated circuit device shown in FIG.

As described above, in the mixed semiconductor integrated circuit device having the electrostatic breakdown prevention circuit (2), the electrostatic breakdown prevention circuit (2) is a buried type high impurity concentration layer buried between the semiconductor substrate 1 and the epitaxial layer 4. It is composed of a p-type semiconductor region 3 and a highly impurity-concentrated n-type semiconductor region 19 provided on the main surface of the epitaxial layer 4 with its bottom surface in contact with the buried p-type semiconductor region 3. diode element D
(the drain region of the clamping MISFET Qc), the contact between the buried p-type semiconductor region 3 with high impurity concentration and the n-type semiconductor region 19 with high impurity concentration increases the junction breakdown voltage of the diode element. Therefore, electrostatic damage to the input stage circuit I can be reduced. According to the electrostatic breakdown test conducted by the present inventor, the junction breakdown voltage of the diode element of the electrostatic breakdown prevention circuit (■) is about 10 to 15 [V] diameter, and the complementary MISFET (Q n r Q p ) The dielectric strength voltage of the gate insulating film 12 was about 19 [V] diameter. In other words, one of the inventors of the present invention has determined the junction breakdown voltage (B V j
) was found to be lower than the dielectric strength voltage (BVg) of the gate insulating film 12 (BVj<BVg).

Further, the buried p° type semiconductor region 3 of the diode element is formed in the same manufacturing process as the buried p° type semiconductor region 3 constituting the isolation region of the bipolar transistor Tr. By forming the n° type semiconductor region 19 in the same manufacturing process as the potential pulling n° type semiconductor region 19 of the bipolar transistor Tr, the buried p° type semiconductor region 3 in the isolation region of the bipolar transistor Tr, In the step of forming each of the n° type semiconductor regions 19 for raising the potential.

Buried p° type semiconductor region 3 of the diode element, n°
Since each of the type semiconductor regions 19 can be formed,
The number of manufacturing steps for a mixed semiconductor integrated circuit device can be reduced.

The n-type semiconductor region 19 of the diode element constitutes the drain region of the clamping MISFETQc of the electrostatic breakdown prevention circuit H, and this n.

The type semiconductor region 19 includes the gate electrode 13 of the clamp MISFET Qc and the side wall spacer 16 on its side wall.
By forming the sidewall spacer 16 by introducing impurities using a mask after forming the sidewall spacer 16, the amount of impurity diffused into the channel forming region side of the go-type semiconductor region (drain region) 19 of the clamping MIS FETQc can be reduced. Since it can be reduced by the amount equivalent to the sidewall spacer 16, the clamp MISFET Qc
A sufficient channel length can be secured. In other words,
Since the clamping MISFET Qc can reduce the short channel effect, it is possible to reduce the area occupied by the electrostatic breakdown prevention circuit (2) and improve the degree of integration of the mixed semiconductor integrated circuit device.

As explained in the manufacturing method above, M I for clamping
After forming the go type semiconductor region 19 which is the drain region of S F E T Q c and the n° type semiconductor region 19 for raising the potential of the bipolar transistor Tr in the same manufacturing process and forming the side wall spacer 16, Since the n° type semi-sensitive region 19 is formed, the gate electrode 13 of the MISFET, the information storage capacitive element C of the DRAM, etc. are In the mixed semiconductor integrated circuit device of this embodiment, the order of the steps is significantly changed compared to the conventional manufacturing method.

Further, in a mixed semiconductor integrated circuit device having an electrostatic breakdown prevention circuit (1) and a DRAM, the n-type semiconductor region 14, which is the source region or drain region of the memory cell selection MISFETQm of the DRAM memory cell, is configured with a shallow junction, and the MISF for clamping electrostatic breakdown prevention circuit■
By configuring the go-type semiconductor region 19, which is the drain region of the ETQc, as a deep junction, as described above, the buried p-type semiconductor region 3 with high impurity concentration and the n-type semiconductor region with high impurity concentration can be connected. MI for the clamp in contact with 19
Since the junction breakdown voltage of the drain region of SFETQc can be lowered, it is possible to reduce electrostatic damage in the input stage circuit I, and it is also possible to reduce the breakdown voltage of the memory cell selection MISFETQ.
Since it is possible to reduce the amount of impurity diffused into the channel formation region side of the n-type semiconductor region 14, which is the source region and drain region of m, the short channel effect can be reduced and the area occupied by the memory cell selection MISFETQm can be reduced. The size of the semiconductor integrated circuit device can be reduced, and the degree of integration of the mixed semiconductor integrated circuit device can be improved. In other words, each of the source region and drain region of the memory cell selection MISFETQm of the DRAM memory cell is a deep-junction n-type semiconductor in the same layer (same manufacturing process) as the potential pulling go-type semiconductor region 19 of the bipolar transistor Tr. Although the charge storage amount of the information storage capacitive element C can be improved by forming the region 19 and increasing the junction capacitance, the DR of the mixed type semiconductor integrated circuit device of this embodiment
In the AM, each of the source region and drain region of the memory cell selection MISFETQm is formed of an n-type semiconductor region 14 with a low impurity concentration, and the degree of integration is improved by reducing the short channel effect.

Further, in the mixed semiconductor integrated circuit device, the go-type semiconductor region 21 (or the d-type semiconductor region 25 may be used), which is the source region and drain region of the n-channel MISFETQn, is formed, and the bipolar transistor Tr
forming an n゛゛ semiconductor region 21 which is an emitter region of
A p semiconductor region 22 is formed which is the source region and a drain region of the p-channel MISFET Qp, and a p semiconductor region 22 is a graft base region of the bipolar transistor Tr.

By forming the type semiconductor region 22, complementary type MIS
Since the base region and emitter region of the bipolar transistor Tr can be formed in the process of forming each of the source region and drain region of the FET, the number of manufacturing steps of the mixed semiconductor integrated circuit device can be reduced.

(Embodiment 2) Embodiment 2 is a second embodiment of the present invention in which the electrostatic breakdown prevention circuit of a mixed semiconductor integrated circuit device is constructed of diode elements.

A mixed semiconductor integrated circuit device according to Embodiment 2 of the present invention is shown in FIG. 14 (a sectional view of the main part of the electrostatic breakdown prevention circuit).

As shown in FIG. 14, the electrostatic breakdown prevention circuit (2) of the present embodiment (2) is composed of at least a diode element. The diode element mainly includes a buried p° type semiconductor region 3, a p− type well region 6, and an n° type semiconductor region 21 (
or d-type semiconductor region 25). In other words, the diode element is configured vertically with a Go/p-/f structure.

The n°-type semiconductor region 21 of the diode element is a go-type semiconductor region 21 that is the source region and drain region of the n-channel MISFET Qn of the complementary MISFET.
It is formed in the same layer (same manufacturing process) as . The external terminal (BP) is connected to the Go-type semiconductor region 21 of this diode element
) 29 and the input stage circuit I are connected to each other. The p-type well region 6 of the diode element is formed in the same layer (same manufacturing process) as the p-type well region 6 of the complementary MISFET. The buried type p semiconductor region 3 of the diode element is a bipolar transistor Tr.
It is formed in the same manufacturing process as the buried p° type semiconductor region 3 in the isolation region.

As described above, in the mixed semiconductor integrated circuit device having the electrostatic breakdown prevention circuit (2), the electrostatic breakdown prevention circuit (2) is a buried type with a high impurity concentration buried between the semiconductor substrate 1 and the epitaxial layer 4. a p° type semiconductor region 3; a low impurity concentration p− type well region 6 provided on the main surface of the epitaxial layer 4 with its bottom surface in contact with the buried p° semiconductor region 3; By having a diode element constituted by a high impurity concentration n° type semiconductor region 21 provided on the main surface of the type well region 6, a high impurity concentration buried p type semiconductor region 3 is formed. Since the junction breakdown voltage of the diode element can be lowered by providing the n° type semiconductor region 21 with a high impurity concentration, it is possible to reduce electrostatic damage of the input stage circuit I, and
Compared to the case where the semiconductor substrate 1 is made of p° type with high impurity concentration, the buried p° type semiconductor region 3 with high impurity concentration has better controllability of the impurity concentration distribution. The rise of p-type impurities from the semiconductor region 3 can be reduced, and the n-channel MI provided on the buried p-type semiconductor region 3 in the same layer as the buried p-type semiconductor region 3
Fluctuations in electrical characteristics such as threshold voltage of SFETQn can be reduced. In other words, when the semiconductor substrate 1 is made of p-type with a high impurity concentration in order to lower the junction breakdown voltage of the diode element, the amount of p-type impurities rising from the semiconductor substrate 1 is large, so that it is caused by the substrate effect. Although the threshold voltage of the n-channel MISFETQn fluctuates, it can be reduced according to the present invention. In addition, by reducing the rise of the p-type impurity,
Since the epitaxial layer 4 itself can be formed thin, the frequency characteristics of the bipolar transistor Tr can be improved. In other words, the mixed semiconductor integrated circuit device can improve the electrostatic breakdown voltage and the electrical reliability.

The buried p-type semiconductor region 3 of the diode element is formed in the same manufacturing process as the buried p-type semiconductor region 3 of the isolation region of the bipolar transistor Tr, and the p- Type well region 6 is complementary type MIS
The n-type semi-conductor region 21 of the diode element is formed in the same manufacturing process as the p-type well region 6 of the FET, and the n-type semiconductor region 21 which is the source region and drain region of the n-channel MISFET Qn is formed in the same manufacturing process. By forming it in the process.

Since the diode element can be formed in the steps of forming each of the bipolar transistor Tr and the complementary MISFET, the number of manufacturing steps of the mixed semiconductor integrated circuit device can be reduced.

In addition, the diode element has a very fast response because it allows an excessive current to flow that can cause electrostatic damage due to breakdown.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention provides the mixed semiconductor integrated circuit device with:
Static random access memory (S
RAM), or mask ROM, EPR
A non-volatile memory such as OM or EEPROM may be installed.

Further, in the present invention, the conductivity type of each element constituting the electrostatic breakdown prevention circuit of the mixed semiconductor integrated circuit device may be reversed.

Further, the present invention can be applied to an electrostatic breakdown prevention circuit provided between the output stage circuit of the hybrid semiconductor integrated circuit device and an external terminal connected thereto.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a mixed semiconductor integrated circuit device, it is possible to improve the electrostatic breakdown voltage and the electrical reliability.

In the mixed semiconductor integrated circuit device, the number of manufacturing steps for obtaining the above effect can be reduced.

In the mixed semiconductor integrated circuit device, the above effects can be obtained and the degree of integration can be improved.

In a mixed semiconductor integrated circuit device having a RAM, the above effects can be obtained, and in particular, the degree of integration of the RAM can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a mixed semiconductor integrated circuit device which is Embodiment I of the present invention, FIG. 2 is an equivalent circuit diagram of the input side of the mixed semiconductor integrated circuit device, and FIGS. FIG. 13 is a cross-sectional view of a main part of the mixed semiconductor integrated circuit device showing each manufacturing process, and FIG. 14 is a cross-sectional view of a main part of the mixed semiconductor integrated circuit device according to embodiment (2) of the present invention. In the figure, ■...Input stage circuit, ■...Electrostatic breakdown prevention circuit, BP, 29...External terminal, Q...MISFET
l Tr... Bipolar transistor, C... Capacitive element for information volume, D... Diode element, R... Resistance element, l... Semiconductor substrate, 2, 3... Buried semiconductor region , 4... epitaxial layer, 5, 6... well region, 8, 14°15, 20.21.22.25...
- Semiconductor region, 9... Dielectric film, 10... Plate electrode, 12... Gate insulating film, 13... Gate electrode, 16... Side wall spacer, 26.29...
・It is the wiring.

Claims (1)

[Scope of Claims] 1. In a mixed semiconductor integrated circuit device that integrates complementary MISFETs and bipolar transistors and has an electrostatic breakdown prevention circuit between an external terminal and an input stage circuit, the electrostatic breakdown prevention circuit includes a semiconductor a buried first semiconductor region of a first conductivity type with a high impurity concentration and formed in the same layer as the isolation region of the bipolar transistor buried in the substrate; a second semiconductor region of the first conductivity type with a low impurity concentration formed in the same layer as the well region of the complementary MISFET, the bottom surface of which is in contact with the second semiconductor region; A mixed type, characterized in that it has a diode element constituted by a source region and a drain region of the complementary MISFET, and a third semiconductor region of a second conductivity type with a high impurity concentration and formed in the same layer. Semiconductor integrated circuit device. 2. The mixed semiconductor integrated device according to claim 1, wherein the third semiconductor region of the diode element of the electrostatic breakdown prevention circuit is connected to each of the external terminal and the input stage circuit. circuit device. 3. The first semiconductor region of the diode element of the electrostatic breakdown prevention circuit is formed in the same manufacturing process as the isolation region of the bipolar transistor, and the second semiconductor region is formed in the same manufacturing process as the well region of the complementary MISFET. The mixed semiconductor integrated circuit according to claim 1 or 2, wherein the third semiconductor region is formed in the same manufacturing process as the source region and drain region of the complementary MISFET. Method of manufacturing the device. 4. Claim 3, characterized in that the first semiconductor region of the diode element of the electrostatic breakdown prevention circuit is formed by introducing impurities by ion implantation.
A method for manufacturing a mixed semiconductor integrated circuit device according to paragraph 1. 5. In a mixed semiconductor integrated circuit device integrating complementary MISFETs and bipolar transistors, which has an electrostatic breakdown prevention circuit between an external terminal and an input stage circuit, the electrostatic breakdown prevention circuit is embedded in a semiconductor substrate. a buried first semiconductor region of a first conductivity type with a high impurity concentration formed in the same layer as the isolation region of the bipolar transistor; and a bottom surface of the first semiconductor region in contact with the main surface of the semiconductor substrate. a diode element comprising a semiconductor region for raising the potential of the buried collector region of the bipolar transistor provided in the bipolar transistor and a second semiconductor region of the second conductivity type with a high impurity concentration formed in the same layer. A mixed semiconductor integrated circuit device characterized by: 6. The second semiconductor region of the diode element of the electrostatic breakdown prevention circuit is connected to the clamp MI connected to the external terminal.
6. The mixed semiconductor integrated circuit device according to claim 5, wherein the mixed semiconductor integrated circuit device is a drain region of an SFET. 7. The mixed semiconductor integrated circuit according to claim 5, wherein the second semiconductor region of the diode element of the electrostatic breakdown prevention circuit is a resistance element connected to the external terminal. 8. The junction breakdown voltage of the diode element of the electrostatic breakdown prevention circuit is configured to be lower than the breakdown voltage of the gate insulating film of the complementary MISFET constituting the input stage circuit. Each of the mixed semiconductor integrated circuit devices described in Items 5 to 7. 9. The first semiconductor region of the diode element of the electrostatic breakdown prevention circuit is formed in the same manufacturing process as the step of forming the isolation region of the bipolar transistor, and the second semiconductor region is a semiconductor region for raising the potential of the bipolar transistor. 9. A method of manufacturing a mixed semiconductor integrated circuit device according to claim 5, wherein the method is performed in the same manufacturing process as that of forming a semiconductor integrated circuit device. 10. The second diode element of the electrostatic breakdown prevention circuit
The semiconductor region is formed by forming a sidewall spacer on the gate electrode of the clamp MISFET and its sidewall, and then introducing a second conductivity type impurity using the sidewall spacer as a mask. A method for manufacturing a mixed semiconductor integrated circuit device according to claim 6. 11. In a mixed semiconductor integrated circuit device integrating complementary MISFETs and bipolar transistors, which has an electrostatic breakdown prevention circuit between an external terminal and an input stage circuit and has a dynamic random access memory, the electrostatic breakdown prevention circuit a buried first semiconductor region of a first conductivity type with a high impurity concentration formed in the same layer as the isolation region of the bipolar transistor buried in the semiconductor substrate; a second semiconductor region of a second conductivity type with a high impurity concentration and formed of the same layer as a semiconductor region for raising the potential of the buried collector region of the bipolar transistor whose bottom surface is in contact with the first semiconductor region; a third semiconductor having a junction shallower than a second semiconductor region of the diode element, each of a source region and a drain region of a memory cell selection MISFET of a memory cell of the dynamic random access memory; What is claimed is: 1. A mixed semiconductor integrated circuit device characterized in that it is comprised of regions. 12. The mixed type according to claim 11, wherein the memory cell of the dynamic random access memory is constituted by a series circuit of a memory cell selection MISFET and an information storage capacitive element. Semiconductor integrated circuit device.