JP3779734B2 - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having an SRAM (Static Random Access Memory).
[0002]
[Prior art]
An SRAM as a semiconductor memory device includes a memory cell including a flip-flop circuit and two transfer MISFETs (Metal Insulator Semiconductor Field Effect Transistors) at an intersection between a complementary data line and a word line.
[0003]
In the memory cell transfer MISFET, one of the source region and the drain region is connected to the input / output terminal of the flip-flop circuit, and the other is connected to the complementary data line. A word line is connected to the gate electrode of the transfer MISFET, and the conduction and non-conduction of the transfer MISFET is controlled by this word line.
[0004]
The flip-flop circuit of the memory cell is configured as an information storage unit, and includes two drive MISFETs and two load resistance elements. One of the source region and drain region of one transfer MISFET is connected to the drain region of one drive MISFET, and a reference voltage line is connected to the source region. Further, one of the source region and the drain region of the other transfer MISFET is connected to the gate electrode of the drive MISFET.
[0005]
One of the source region and the drain region of the transfer MISFET is connected to one end side of the load resistance element, and a power supply voltage line is connected to the other end side. The load resistive element is stacked on the top of the driving MISFET in order to reduce the area occupied by the memory cell and improve the degree of integration.
[0006]
Japanese Patent Application Laid-Open No. 3-234055 and Japanese Patent Application No. 5-4502 describe techniques optimal for high integration of the SRAM as described above.
[0007]
In the SRAM described in JP-A-3-234055, the gate electrode of the driving MISFET is constituted by the first conductive film formed on the main surface of the semiconductor substrate, and the second conductive material also formed on the main surface of the semiconductor substrate. The film forms the gate electrode of the transfer MISFET, the word line connected to the gate electrode, and the reference voltage line connected to the source region of the drive MISFET. The gate electrode of the load MISFET is formed by the third conductive film formed on the first and second conductive films, and the channel of the load MISFET is formed by the fourth conductive film formed on the third conductive film. A region, a source region, a drain region, and a power supply voltage line connected to the source region of the load MISFET are configured.
[0008]
That is, the SRAM described in the above publication employs a so-called complete CMOS structure in which the flip-flop circuit of the memory cell is composed of two drive MISFETs and two load MISFETs in order to reduce standby current. Yes.
[0009]
Further, this SRAM has a gate electrode (first conductive film) of a driving MISFET as a first electrode and a dielectric film as an insulating film formed on the gate electrode as a countermeasure against α-ray soft error of the memory cell. A capacitive element having a gate electrode (third conductive film) of a load MISFET formed on the dielectric film as a second electrode is provided.
[0010]
Although not a publicly known technique, the SRAM described in Japanese Patent Application No. 5-4502 comprises a gate electrode of a driving MISFET with a first conductive film formed on the main surface of a semiconductor substrate, A second conductive film formed on the main surface of the substrate constitutes the gate electrode of the transfer MISFET and a word line connected to the gate electrode, and a third film formed on the first and second conductive films. The conductive film forms a reference voltage line, and the fourth conductive film formed on the third conductive film forms the channel region, source region, and drain region of the load MISFET, and is formed on the fourth conductive film. The gate electrode of the load MISFET is formed by the fifth conductive film, the power supply voltage line is formed by the sixth conductive film formed on the fifth conductive film, and the power supply voltage line is overlapped with the load MISFET. Place By, constitute a capacitance element between the power supply voltage line and the load MISFET.
[0011]
That is, this SRAM employs a complete CMOS structure with reduced standby current, and a large-capacity capacitive element is formed between the load MISFET and a large-area power supply voltage line formed thereabove. This greatly improves the resistance of the cell to alpha ray soft errors.
[0012]
[Problems to be solved by the invention]
In the SRAM described in Japanese Patent Laid-Open No. 3-234055, in which a capacitive element is formed between the gate electrode of the memory cell driving MISFET and the gate electrode of the load MISFET, it is difficult to form a large capacity capacitive element. For this reason, there is a problem that it becomes difficult to ensure the resistance to α-ray soft error as the memory cell is miniaturized.
[0013]
In the SRAM described in Japanese Patent Application No. 5-4502, a capacitive element is formed between a load MISFET of a memory cell and a large-area power supply voltage line covering the upper layer thereof, so this SRAM is formed. When power supply noise enters the semiconductor chip from the outside, the power supply noise directly affects the memory cell through the power supply voltage line, and there is a possibility that the operation reliability of the memory cell is lowered.
[0014]
An object of the present invention is to provide a technique capable of improving the resistance to α-ray soft error of an SRAM memory cell.
[0015]
Another object of the present invention is to provide a technique capable of improving the reliability of SRAM circuit operation.
[0016]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0017]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be described as follows.
[0018]
(1). A first conductive film formed on a main surface of a semiconductor substrate in an SRAM in which a memory cell is constituted by a transfer MISFET controlled by a word line and a flip-flop circuit composed of a drive MISFET and a load MISFET. The gate electrode of the driving MISFET is configured, and the gate electrode of the transfer MISFET is configured by the second conductive film formed on the main surface of the semiconductor substrate, and is formed on the first and second conductive films. The third conductive film constitutes the gate electrode of the load MISFET, the fourth conductive film formed on the third conductive film constitutes the channel region, the source region and the drain region of the load MISFET, A plate electrode covering the memory cell array is formed by a fifth conductive film formed on the fourth conductive film, and the load MISFET and the plate current are formed. A capacitive element is formed between the plate electrode and at least a hole is provided in the plate electrode on the channel region on the drain region side of the load MISFET.
[0019]
(2) In the SRAM of (1), a power supply voltage is supplied to the plate electrode from the outside of the memory cell array.
[0020]
(3) In the SRAM of (1), at least a part of the dielectric film of the capacitive element is formed of a silicon nitride film.
[0021]
(4) In the SRAM manufacturing method of (3), after forming the opening in the plate electrode, the silicon nitride film at the bottom of the opening is removed, and then a hydrogenation annealing treatment is performed. Hydrogen is supplied to the conductive film constituting the load MISFET through the opening.
[0022]
(5) In the method of manufacturing an SRAM according to (4), when the silicon nitride film at the bottom of the opening is removed, the silicon nitride film in a region for forming a peripheral circuit is simultaneously removed.
[0023]
(6) In the SRAM manufacturing method of (1), after etching the conductive film constituting the channel region, the source region and the drain region of the load MISFET, the insulating film under the conductive film is etched. A part of the gate electrode of the load MISFET is exposed, and then a dielectric film of the capacitive element is formed on the conductive film.
[0024]
[Action]
According to the above means (1), since the capacitive element is formed between the load MISFET and the large-area plate electrode covering the load MISFET, a large-capacitance capacitive element can be formed. It is possible to improve the alpha ray soft error resistance.
[0025]
Further, by providing an opening in the plate electrode on the channel region on the drain region side of the load MISFET and separating the channel region having the offset structure from the plate electrode, the plate electrode is strongly applied to the offset region of the load MISFET. Since the application of an electric field can be avoided, the generation of a leakage current between the source region and the drain region due to this strong electric field can be prevented, and the off current of the load MISFET can be reduced to ensure a stable operation of the memory cell. Can do.
[0026]
According to the means (2), when the power supply voltage is supplied to the plate electrode from the outside of the memory cell array, when the power supply noise enters the semiconductor chip on which the SRAM is formed from the outside, the memory of the power supply noise is supplied. Since direct influence on the cell can be avoided, stable operation of the memory cell can be ensured.
[0027]
According to the above means (3), at least a part of the dielectric film of the capacitive element is made of a silicon nitride film having a higher withstand voltage than the silicon oxide film, so that it is compared with a case where the silicon oxide film is made of a single layer. The thickness of the dielectric film can be reduced, and the capacity of the capacitive element can be increased.
[0028]
Further, by covering the upper layer of the load MISFET with a silicon nitride film having a higher water resistance than the silicon oxide film, it is possible to suppress the characteristic variation of the load MISFET due to moisture entering from the chip surface.
[0029]
According to the above means (4), hydrogen is added to dangling bonds existing on the crystal grain boundary surface of the conductive film (polycrystalline silicon film) constituting the load MISFET through the openings provided in the plate electrode. MISFET Qp for load by supplying atoms ₁ , Qp ₂ The mutual conductance (Gm) can be improved.
[0030]
According to the above means (5), it is possible to suppress fluctuations in the threshold voltage of the peripheral circuit (a MISFET constituting the peripheral circuit) due to the formation of a silicon nitride film in which hydrogen does not easily pass over the peripheral circuit. The stable operation of the SRAM can be ensured.
[0031]
According to the above means (6), the dielectric film is formed between the load MISFET and the plate electrode by forming the dielectric after removing the insulating film on the gate electrode of the load MISFET. Therefore, the capacitance of the capacitor can be increased.
[0032]
【Example】
Hereinafter, the present invention will be described in detail using examples. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0033]
Example 1
An SRAM according to an embodiment of the present invention is not particularly limited, but has a large capacity of, for example, 4 megabits (Mbit) to 16 megabits (Mbit). FIG. 9 shows an equivalent circuit diagram of the SRAM memory cell MC.
[0034]
As shown in FIG. 9, the memory cell MC has a word line WL (first word line WL). ₁ And the second word line WL ₂ ) And complementary data line DL (first data line DL) ₁ And the second data line DL ₂ ), And a flip-flop circuit and two transfer MISFETs Qt ₁ , Qt ₂ It consists of and. The flip-flop circuit is configured as an information storage unit and stores 1-bit information (“1” or “0”).
[0035]
Two transfer MISFETs Qt of the memory cell MC ₁ , Qt ₂ Is an n-channel type, and one of a source region and a drain region is connected to a pair of input / output terminals of a flip-flop circuit. MISFETQt for transfer ₁ One of the source region to the drain region of the first data line DL ₁ And its gate electrode is connected to the first word line WL. ₁ It is connected to the. MISFETQt for transfer ₂ One of the source region to the drain region of the second data line DL ₂ The gate electrode of which is connected to the second word line WL. ₂ It is connected to the.
[0036]
The flip-flop circuit includes two driving MIS13TQd configured in an n-channel type. ₁ , Qd ₂ And two load MISFETs Qp composed of p-channel type ₁ , Qp ₂ It consists of That is, the SRAM memory cell MC of the present embodiment has a complete CMOS structure.
[0037]
MISFET Qd for driving ₁ And load MISFETQp ₁ Are connected to each other's drain region (one input / output terminal of the flip-flop circuit) and to each other's gate electrodes to form a CMOS inverter. Similarly, MISFET Qd for driving ₂ And load MISFETQp ₂ Are connected to each other's drain region (the other input / output terminal of the flip-flop circuit) and connected to each other's gate electrodes to constitute a CMOS inverter.
[0038]
MISFET Qd for driving ₁ And load MISFETQp ₁ Each of the drain regions of the MISFET Qt for transfer ₁ Connected to the other one of the source region and drain region of the transistor ₂ And load MISFETQp ₂ Are connected to the respective gate electrodes. Similarly, MISFET Qd for driving ₂ And load MISFETQp ₂ Each of the drain regions of the MISFET Qt for transfer ₂ Connected to the other one of the source region and drain region of the transistor ₁ And load MISFETQp ₁ Are connected to the respective gate electrodes.
[0039]
MISFET Qd for driving ₁ , Qd ₂ The source region of each has a reference voltage (V _SS ) And MISFET Qp for load ₁ , Qp ₂ Each source region of the power source voltage (V _CC ) It is connected to the. Reference voltage (V _SS ) Is, for example, 0 V (GND potential) and the power supply voltage (V _CC ) Is, for example, 5V.
[0040]
MISFET Qp for load ₁ , Qp ₂ And the second power supply voltage (V _CC1 ) Between the capacitance element C ₁ , C ₂ Is configured. This capacitive element C ₁ , C ₂ Is intended to improve the resistance to α-ray soft error of the memory cell MC, and its configuration will be described in detail later.
[0041]
Next, a specific configuration of the SRAM memory cell MC will be described with reference to FIGS.
[0042]
As shown in FIG. ^- P on the main surface of a semiconductor substrate (semiconductor chip) 1 made of type silicon single crystal. ^- A mold well 2 is formed and this p ^- On the main surface of the inactive region of the mold well 2, an element isolation field insulating film 4 made of a silicon oxide film is formed. Under the field insulating film 4, a p-type channel stopper region 5 for preventing inversion is formed.
[0043]
MISFET Qd for driving constituting memory cell MC ₁ , Qd ₂ MISFET Qt for transfer ₁ , Qt ₂ And load MISFETQp ₁ , Qp ₂ Drive MISFET Qd ₁ , Qd ₂ And transfer MISFETQt ₁ , Qt ₂ Each of the p is surrounded by the field insulating film 4. ^- It is formed on the main surface of the active region of the mold well 2.
[0044]
MISFET Qd for driving ₁ , Qd ₂ Each of these comprises a gate insulating film 6, a gate electrode 7, a source region and a drain region. The gate electrode 7 is formed in the first layer gate material forming step, and is formed of, for example, a polycrystalline silicon film. An n-type impurity (for example, P) is introduced into the polycrystalline silicon film in order to reduce its resistance value.
[0045]
MISFET Qd for driving ₁ , Qd ₂ An insulating film 8 is formed on the gate electrode 7. The insulating film 8 is made of, for example, a silicon oxide film. Further, sidewall spacers 9 are formed on the sidewalls of the gate electrode 7 in the gate length direction. The sidewall spacer 9 is made of, for example, a silicon oxide film.
[0046]
MISFET Qd for driving ₁ , Qd ₂ The source region and the drain region of each of the n-type semiconductor region 10 having a low impurity concentration and the n-type semiconductor region having a high impurity concentration provided thereon are provided. ⁺ And a type semiconductor region 11. That is, the driving MISFET Qd ₁ , Qd ₂ Each source region and drain region has a so-called double diffused drain structure.
[0047]
The field insulating film 4 and the driving MISFET Qd formed on the main surface of the semiconductor substrate 1 ₁ , Qd ₂ The pattern layout of the gate electrode 7 is shown in FIG. In the figure, two L-shaped regions 3 and 3 surrounded by a field insulating film 4 are active regions for one memory cell MC.
[0048]
As shown in FIG. 2, the driving MISFET Qd ₁ , Qd ₂ One end side of each of the gate electrodes 7 protrudes on the field insulating film 4 by an amount corresponding to at least a mask alignment margin in the manufacturing process. Also, the driving MISFET Qd ₁ Gate electrode 7 (Qd ₁ ) Is connected to the driving MISFET Qd via the field insulating film 4. ₂ Projecting over the drain region of the MISFET Qd for driving ₂ Gate electrode 7 (Qd ₂ ) Is connected to the driving MISFET Qd via the field insulating film 4. ₁ It protrudes up to the drain region 7.
[0049]
As shown in FIG. 1, the transfer MISFET Qt of the memory cell MC ₁ , Qt ₂ Each includes a gate insulating film 12, a gate electrode 13A, a source region, and a drain region. The gate electrode 13A is formed in the second-layer gate material forming step, and is composed of, for example, a laminated film (polycide film) of a polycrystalline silicon film and a refractory metal silicide film. An n-type impurity (for example, P) is introduced into the lower polycrystalline silicon film in order to reduce its resistance value. The upper refractory metal silicide film is, for example, WSi _X , MoSi _X TiSi _X , TaSi _X Etc.
[0050]
Transfer MISFETQt ₁ , Qt ₂ Over the gate electrode 13A, an insulating film 15 and an insulating film 21 are formed. The insulating film 15 and the insulating film 21 are made of, for example, a silicon oxide film. A sidewall spacer 16 is formed on the side wall of the gate electrode 13A. The sidewall spacer 16 is made of, for example, a silicon oxide film.
[0051]
Transfer MISFETQt ₁ , Qt ₂ The source region and the drain region of each of the n-type semiconductor region 17 and the n-type semiconductor region 17 with a low impurity concentration ⁺ And a type semiconductor region 18. That is, the transfer MISFET Qt ₁ , Qd ₂ The source region and the drain region of each have an LDD (Lightly Doped Drain) structure.
[0052]
The transfer MISFET Qt formed on the main surface of the semiconductor substrate 1 ₁ , Qt ₂ The pattern layout of the gate electrode 13A is shown in FIG. As shown in the figure, the transfer MISFET Qt ₁ , Qt ₂ The gate electrode 13A has a gate length (Lg) direction of MISFET Qd for driving. ₁ , Qd ₂ The gate electrode 7 is arranged so as to intersect with the gate length (Lg) direction.
[0053]
As shown in FIGS. 1 and 3, the transfer MISFET Qt ₁ One of the source region to the drain region of the MISFET Qd for driving ₁ The drain region is integrally formed. Similarly, transfer MISFETQt ₂ One of the source region to the drain region of the MISFET Qd for driving ₂ The drain region is integrally formed.
[0054]
MISFETQt for transfer ₁ Gate electrode 13A (Qt ₁ ) Includes the first word line WL. ₁ Are connected, and the transfer MISFET Qt ₂ Gate electrode 13A (Qt ₂ ) Includes the second word line WL. ₂ Is connected. MISFETQt for transfer ₁ The gate electrode 13A of the first word line WL ₁ MISFET Qt for transfer ₂ The gate electrode 13A of the second word line WL ₂ It is composed integrally with.
[0055]
The first word line WL ₁ And the second word line WL ₂ Between the two drive MISFETs Qd ₁ , Qd ₂ A reference voltage line (V _SS ) 13B is arranged. Reference voltage line (V _SS ) 13B is a transfer MISFET Qt ₁ , Qt ₂ Gate electrode 13A and word line WL (first word line WL) ₁ , Second word line WL ₂ ) And the second layer gate material forming step, and extends on the field insulating film 4 in the same direction as the word lines WL. Reference voltage line (V _SS ) 13B is a driving MISFET Qd ₁ , Qd ₂ MISFET Qd for driving through a contact hole 14 opened in the same insulating film as the gate insulating film 6 of ₁ , Qd ₂ Source regions (n ⁺ Type semiconductor region 11).
[0056]
As shown in FIG. 1, the two load MISFETs Qp of the memory cell MC ₁ , Qp ₂ MISFET Qp for load ₁ Is the MISFET Qd for driving ₂ MISFET Qp for load ₂ Is the MISFET Qd for driving ₁ It is arranged on the area. MISFET Qp for load ₁ , Qp ₂ Each includes a gate electrode 23A, a gate insulating film 24, a channel region 26N, a source region 26P, and a drain region 26P.
[0057]
MISFET Qp for load ₁ , Qp ₂ The gate electrode 23A is formed in the third-layer gate material forming step, and is formed of, for example, a polycrystalline silicon film. An n-type impurity (for example, P) is introduced into the polycrystalline silicon film in order to reduce its resistance value. MISFET Qp for load ₁ , Qp ₂ A pattern layout of the gate electrode 23A is shown in FIG.
[0058]
As shown in FIGS. 1 and 4, the load MISFET Qp ₁ The gate electrode 23A includes an insulating film 21, an insulating film 8, and an insulating film (transfer MISFETQt ₁ , Qt ₂ Through the contact hole 22 formed in the same insulating layer as the gate insulating film 12). ₁ Gate electrode 7 and transfer MISFET Qt ₂ Is connected to one of the source region and the drain region. Similarly, MISFET Qp for load ₂ The gate electrode 23A includes an insulating film 21, an insulating film 8, and an insulating film (transfer MISFETQt ₁ , Qt ₂ MISFET Qd for driving through a contact hole 22 opened in the same insulating layer as the gate insulating film 12). ₂ Gate electrode 7 and transfer MISFET Qt ₁ Is connected to one of the source region and the drain region.
[0059]
Transfer MISFETQt ₁ , Qt ₂ In the other upper part of the source region to the drain region, the load MISFET Qp ₁ , Qp ₂ A pad layer 23B formed in the same third-layer gate material forming step as that of the gate electrode 23A is disposed. The pad layer 23B includes an insulating film 21 and an insulating film (transfer MISFETQt ₁ , Qt ₂ MISFET Qt for transfer through a contact hole 22 formed in the same insulating layer as that of the gate insulating film 12). ₁ , Qt ₂ Is connected to the other one of the source region and the drain region.
[0060]
As shown in FIG. 1, the load MISFET Qp ₁ , Qp ₂ On the upper part of the gate electrode 23A, the load MISFET Qp ₁ , Qp ₂ The gate insulating film 24 is formed. The gate insulating film 24 is made of, for example, a silicon oxide film.
[0061]
MISFET Qp for load ₁ , Qp ₂ The upper portion of the gate insulating film 24 has a load MISFET Qp. ₁ , Qp ₂ Channel region 26N, source region 26P and drain region 26P are formed. The channel region 26N is formed in the fourth-layer gate material forming step, and is made of, for example, a polycrystalline silicon film. This polycrystalline silicon film has a load MISFET Qp. ₁ , Qp ₂ An n-type impurity (for example, P) is introduced in order to make the threshold voltage of the enhancement type. MISFET Qp for load ₁ , Qp ₂ FIG. 5 shows a pattern layout of the channel region 26N, source region 26P, and drain region 26P.
[0062]
As shown in FIGS. 1 and 5, the load MISFET Qp ₁ , Qp ₂ A drain region 26P is formed on one end side of the channel region 26N, and a source region 26P is formed on the other end side. The drain region 26P and the source region 26P are formed in the same fourth-layer gate material (polycrystalline silicon) forming step as the channel region 26N, and are configured integrally with the channel region 26N. The polycrystalline silicon film constituting the drain region 26P and the source region 26P has ap type impurity (for example, BF ₂ ) Has been introduced. In order to make it easier to see the arrangement of the channel region 26N, the drain region 26P, and the source region 26P, the drain region 26P and the source region 26P excluding the channel region 26N are shaded in FIG. Thus, the load MISFET Qp of the memory cell MC of the present embodiment. ₁ , Qp ₂ Is a so-called so-called channel region 26N, source region 26P, and drain region 26P formed in the fourth-layer gate material forming step are arranged above the gate electrode 23A formed in the third-layer gate material forming step. It has a bottom gate structure.
[0063]
MISFET Qp for load ₁ , Qp ₂ Is the power supply voltage (V _CC ) In the OFF state, a leakage current is generated between the source region 26P and the drain region 26P by applying a strong electric field between the gate electrode 23A and the drain region 26P in the state of the reference voltage (Vss) on the gate electrode 23A. In order to prevent this, the drain region 26P and the gate electrode 23A are separated from each other through the channel region 26N. That is, MISFET Qp for load ₁ , Qp ₂ Has a so-called offset structure in which the drain region 26P and the gate electrode 23A are separated without overlapping. Hereinafter, MISFET Qp for load ₁ , Qp ₂ Of these channel regions 26N, a region separated from the gate electrode 23A is referred to as an offset region 26off (a region shaded in FIG. 6).
[0064]
MISFET Qp for load ₁ The drain region 26P of the load MISFET Qp is connected to the load MISFET Qp through a contact hole 25 opened in the same insulating film as the gate insulating film 24 ₂ Connected to the gate electrode 23A. Similarly, MISFET Qp for load ₂ The drain region 26P of the load MISFET Qp is connected to the load MISFET Qp through a contact hole 25 opened in the same insulating film as the gate insulating film 24 ₁ Connected to the gate electrode 23A.
[0065]
MISFET Qp for load ₁ , Qp ₂ The source region 26P of the power supply voltage line (V _CC ) 26P is connected. Power supply voltage line (V _CC ) 26P is formed in the same fourth layer gate material (polycrystalline silicon) forming step as the channel region 26N, the drain region 26P, and the source region 26P, and is configured integrally therewith.
[0066]
As shown in FIG. 1, the load MISFET Qp ₁ , Qp ₂ An insulating film 27 is formed on the upper portion. The insulating film 27 is composed of, for example, a laminated film of a silicon oxide film and a silicon nitride film, and a capacitive element C described later. ₁ , C ₂ The dielectric film is configured.
[0067]
A plate electrode 28 is formed on the insulating film 27. The plate electrode 28 is formed in the fifth-layer gate material forming step, and is composed of, for example, a polycrystalline silicon film. An n-type impurity (for example, P) is introduced into the polycrystalline silicon film. The pattern layout of the plate electrode 28 is shown in FIG. In the figure, the gate material (load MISFET Qp for the fourth layer) among the conductive layers under the plate electrode 28 is shown for easy understanding of the drawing. ₁ , Qp ₂ Channel region 26N, source region 26P, drain region 26P and power supply voltage line (V _CC ) 26P and the gate material of the third layer (load MISFET Qp ₁ , Qp ₂ Only the gate electrode 23A and the pad layer 23B) are shown.
[0068]
As shown in FIGS. 1 and 6, the plate electrode 28 is formed so as to cover the entire area of the memory cell MC. The plate electrode 28 has a power supply voltage line (V _CC ) Is applied, but in this embodiment, the power supply voltage (V _CC1 ) Is applied.
[0069]
As shown in FIG. 9, the memory cell MC includes two capacitive elements C. ₁ , C ₂ Is provided. In the case of the SRAM of this embodiment, this capacitive element C ₁ , C ₂ Is the load MISFETQp ₁ , Qp ₂ Formed between the gate electrode 23 </ b> A and the plate electrode 28. That is, this capacitive element C ₁ , C ₂ Is the load MISFETQp ₁ , Qp ₂ The gate electrode 23A is a first electrode, the plate electrode 28 is a second electrode, and the insulating film 27 between the gate electrode 23A and the plate electrode 28 is a dielectric film.
[0070]
As described above, the SRAM of this embodiment has the load MISFET Qp. ₁ , Qp ₂ And a large-area plate electrode 28 covering the upper portion of the capacitor element C ₁ , C ₂ The capacitive element C ₁ , C ₂ Can be increased in capacity, and the resistance to α-ray soft error of the memory cell MC can be greatly improved.
[0071]
As shown in FIGS. 1, 6, and 7, an opening 29 </ b> A and an opening 29 </ b> B are formed in a part of the plate electrode 28. In the opening 29A, the plate electrode 28 has a load MISFET Qp. ₁ , Qp ₂ In order not to cover the offset region 26off of the load, the load MISFET Qp ₁ , Qp ₂ Is formed above the drain region 26P. On the other hand, the opening 29B is a load MISFET Qp. ₁ , Qp ₂ The gate electrode 23A is formed on the pad layer 23B formed in the same third-layer gate material formation step as the gate electrode 23A.
[0072]
As described above, the SRAM of this embodiment has the load MISFET Qp. ₁ , Qp ₂ An opening 29A is formed in the plate electrode 28 on the upper side of the drain region 26P, and the offset region 26off is separated from the plate electrode 28 through the opening 29A.
[0073]
With this configuration, the power supply voltage (V _CC ) MISFET Qp for load to which is applied ₁ , Qp ₂ In the OFF state, it is possible to avoid the application of a strong electric field between the plate electrode 28 and the offset region 26off, so that the generation of a leakage current between the source region 26P and the drain region 26P due to this strong electric field is prevented. be able to. As a result, the load MISFET Qp ₁ , Qp ₂ Since the source-drain current (OFF current) in the OFF state can be reduced, the ON current / OFF current ratio can be improved and the stable operation of the memory cell MC can be ensured.
[0074]
The other opening 29B formed in the plate electrode 28 has a complementary data line DL (first data line DL) in the upper layer of the pad electrode 23B and the upper layer of the plate electrode 28. ₁ And the second data line DL ₂ ) Are openings provided so as to be connected to the plate electrode 28 without short-circuiting.
[0075]
As shown in FIG. 8, the plate electrode 28 is integrally formed so as to cover the entire area of the memory cell array composed of a large number of memory cells MC. Further, as shown in the figure, one end of the plate electrode 28 extends to the upper part of a guard ring 30 formed of an n-type well formed along the periphery of the memory cell array. The power supply voltage (V from the guard ring 30 through the contact hole 29C opened in the _CC ) Is supplied.
[0076]
That is, the SRAM of the present embodiment has a load MISFET Qp for the memory cell MC. ₁ , Qp ₂ Power supply voltage line (V _CC The power supply voltage (V) is applied to the plate electrode 28 from outside the memory cell array, not from 26P. _CC ). With this configuration, even when power supply noise enters the semiconductor chip 1 in which the SRAM is formed from the outside, it is possible to prevent the power supply noise from directly affecting the memory cell MC through the plate electrode 28, so that the stable operation of the memory cell MC is achieved. Can be secured.
[0077]
As shown in FIG. 1, an intermediate conductive layer 33, a sub word line SWL, and a main word line MWL are formed above the plate electrode 28 via an insulating film 31 and an interlayer insulating film 32. The intermediate conductive layer 33 is connected to the pad layer 23 </ b> B through a contact hole 34 opened in the interlayer insulating film 32, the insulating film 31, and the insulating film 27.
[0078]
Each of the intermediate conductive layer 33, the sub word line SWL, and the main word line MWL is formed in the first layer wiring material forming step, and is formed of a refractory metal film such as tungsten (W). The insulating film 31 is made of, for example, a silicon oxide film, and the interlayer insulating film 32 is made of, for example, a BPSG (Boron-doped Phospho Silicate Glass) film.
[0079]
As shown in FIG. 1, complementary data lines DL (first data lines DL) are disposed above the intermediate conductive layer 33, the sub word line SWL, and the main word line MWL via a second-layer interlayer insulating film 35. ₁ And the second data line DL ₂ ) Is arranged. The complementary data line DL is connected to the intermediate conductive layer 33 through a contact hole 36 opened in the interlayer insulating film 35.
[0080]
The complementary data line DL is formed in the second-layer wiring material forming step, and is composed of, for example, a three-layer metal film in which a barrier metal film, an aluminum alloy film, and a barrier metal film are sequentially stacked. The barrier metal is made of, for example, TiW, and the aluminum alloy is made of, for example, aluminum to which Cu and Si are added. The interlayer insulating film 35 is made of, for example, a three-layer insulating film in which a silicon oxide film, a spin on glass (SOG) film, and a silicon oxide film are sequentially stacked.
[0081]
Among the complementary data lines DL, the first data line DL ₁ Transfer MISFETQt ₁ One of the source region and drain region (n ⁺ Type semiconductor region 18) and connected to the second data line DL ₂ Transfer MISFETQt ₂ One of the source region and drain region (n ⁺ Type semiconductor region 18). Complementary data line DL and transfer MISFETQt ₁ , Qt ₂ N ⁺ The connection to the type semiconductor region 18 is made through the intermediate conductive layer 33 and the pad layer 23B.
[0082]
A final passivation film 37 that protects the surface of the semiconductor chip 1 is formed on the complementary data line DL. The final passivation film 37 is made of, for example, a laminated film of a silicon oxide film and a silicon nitride film.
[0083]
Next, an example of a specific method for manufacturing the SRAM will be described with reference to FIGS.
[0084]
First, n having a specific resistance value of about 10 [Ω / cm]. ^- A semiconductor substrate 1 made of silicon single crystal is prepared, and p is formed in a part of a memory cell array formation region and a peripheral circuit formation region (not shown). ^- A type well 2 is formed, and an n-type well is formed in another part of the peripheral circuit formation region. p ^- The mold well 2 is a BF in which ions are implanted into the main surface of the semiconductor substrate 1. ₂ The n-type well is formed by stretching and diffusing ions implanted into the main surface of the semiconductor substrate 1.
[0085]
Then p ^- A field insulating film 4 for element isolation is formed on the main surface of the inactive region of the mold well 2. At this time, a p-type channel stopper region 5 for preventing inversion is formed under the field insulating film 4. The field insulating film 4 is formed by growing a silicon oxide film to a thickness of about 420 to 480 nm using a thermal oxidation method (LOCOS method) using a silicon nitride film as an oxidation resistant mask.
[0086]
Then p ^- MISFET Qd for driving on the main surface of the active region of the mold well 2 ₁ , Qd ₂ BF for adjusting the threshold voltage of ₂ After ion implantation, MISFET Qd for driving ₁ , Qd ₂ The gate insulating film 6 is formed. This gate insulating film 6 is formed by a thermal oxidation method, and its film thickness is set to about 13 to 14 nm (FIG. 10).
[0087]
Next, a polycrystalline silicon film as a first layer gate material is deposited on the entire surface of the semiconductor substrate 1. This polycrystalline silicon film is formed by the CVD method, and the film thickness is about 90 to 110 nm. In this polycrystalline silicon film, P is introduced during deposition in order to reduce its resistance value.
[0088]
Next, an insulating film 8 made of a silicon oxide film is deposited on the polycrystalline silicon film. This insulating film 8 is formed by the CVD method, and the film thickness is about 135 to 165 nm. The insulating film 8 is formed of a driving MISFET Qd ₁ , Qd ₂ The gate electrode 7 is formed in order to electrically isolate the conductive layer formed thereon.
[0089]
Next, using the photoresist film formed on the insulating film 8 as a mask, the insulating film 8 and the polycrystalline silicon film below the insulating film 8 are sequentially etched, and then the photoresist film is removed by ashing, thereby driving. MISFETQd ₁ , Qd ₂ The gate electrode 7 is formed (FIG. 11).
[0090]
Next, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1. This silicon oxide film is formed by the CVD method, and the film thickness is about 160 to 200 nm. Next, this silicon oxide film is etched by anisotropic etching such as RIE (Reactive Ion Etching), so that the driving MISFET Qd ₁ , Qd ₂ Side wall spacers 9 are formed on the side walls of the gate electrode 7.
[0091]
Next, the driving MISFET Qd ₁ , Qd ₂ After the gate insulating film 6 on the main surface of the active region except under the gate electrode 7 is removed by etching with a dilute hydrofluoric acid aqueous solution, a new silicon oxide film is formed on the main surface of the active region. This silicon oxide film is formed by thermal oxidation and has a thickness of about 9 to 11 nm.
[0092]
Next, a photoresist film is formed on the main surface of the semiconductor substrate 1, and this is used as a mask to drive the MISFET Qd for driving. ₁ , Qd ₂ P of the formation region of ^- P ions are implanted into the main surface of the mold well 2. Next, after removing the photoresist film by ashing, p ^- P introduced into the main surface of the mold well 2 is expanded and diffused to drive the MISFET Qd ₁ , Qd ₂ N-type semiconductor region 10 is formed (FIG. 12).
[0093]
Then p ^- Transfer MISFET Qt on the main surface of the active region of the mold well 2 ₁ , Qt ₂ BF for adjusting the threshold voltage of ₂ Then, the silicon oxide film on the main surface of the active region is removed by etching with dilute hydrofluoric acid aqueous solution, and the transfer MISFET Qt ₁ , Qt ₂ The gate insulating film 12 is formed. This gate insulating film 12 is formed by a thermal oxidation method, and its film thickness is about 13 to 14 nm.
[0094]
Next, a second-layer gate material is deposited on the entire surface of the semiconductor substrate 1. This gate material is a laminated film (polycide film) of a polycrystalline silicon film and a tungsten silicide film. At this time, after a polycrystalline silicon film is first deposited to a thickness of about 36 to 44 nm, a photoresist film is formed on the main surface of the semiconductor substrate 1, and this is used as a mask to drive the MISFET Qd. ₁ , Qd ₂ The insulating film on the n-type semiconductor region 10 (insulating film in the same layer as the gate insulating film 12) is etched to form a contact hole.
[0095]
Next, the photoresist film is removed by ashing, and a polycrystalline silicon film is further deposited by about 36 to 44 nm. This polycrystalline silicon film is formed by the CVD method, and P is introduced during deposition in order to reduce the resistance value. Next, a tungsten silicide film is deposited on the polycrystalline silicon film. The tungsten silicide film is formed by the CVD method, and the film thickness is about 72 to 88 nm.
[0096]
Next, an insulating film 15 made of a silicon oxide film is deposited on the tungsten silicide film. This insulating film 15 is formed by the CVD method, and the film thickness is about 270 to 330 nm. The insulating film 15 is composed of a transfer MISFET Qt ₁ , Qt ₂ The gate electrode 12 is formed to electrically isolate the conductive layer formed thereon.
[0097]
Next, a photoresist film is formed on the insulating film 15, and the insulating film 15 and the second-layer gate material (polycide film) under the insulating film 15 are sequentially etched using the photoresist film as a mask. Is removed by ashing, thereby transferring the MISFET Qt for transfer. ₁ , Qt ₂ Gate electrode 13A, word line WL (first word line WL) ₁ , Second word line WL ₂ ) And reference voltage line (V _SS ) 13B is formed (FIG. 13).
[0098]
Next, a photoresist film is formed on the main surface of the semiconductor substrate 1, and this is used as a mask to transfer the MISFET Qt. ₁ , Qt ₂ P of the formation region of ^- P ions are implanted into the main surface of the mold well 2. Next, after removing the photoresist film by ashing, p ^- P introduced into the main surface of the mold well 2 is stretched and diffused to transfer MISFET Qt ₁ , Qt ₂ N-type semiconductor region 17 is formed.
[0099]
Next, a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1. This silicon oxide film is formed by the CVD method, and the film thickness is about 270 to 330 nm. Next, this silicon oxide film is etched by anisotropic etching such as RIE to transfer MISFET Qt. ₁ , Qt ₂ Gate electrode 13A, word line WL (first word line WL) ₁ , Second word line WL ₂ ) And reference voltage line (V _SS ) Side wall spacers 16 are formed on the respective side walls of 13B.
[0100]
Next, a photoresist film is formed on the main surface of the semiconductor substrate 1, and this is used as a mask to drive the MISFET Qd. ₁ , Qd ₂ Formation region and transfer MISFETQt ₁ , Qt ₂ P in each of the formation regions of ^- As ions are implanted into the main surface of the mold well 2. Next, after removing the photoresist film by ashing, p ^- As introduced into the main surface of the mold well 2 is stretched and diffused to drive the MISFET Qd. ₁ , Qd ₂ P of the formation region of ^- N on the main surface of the mold well 2 ⁺ Type semiconductor region 11 and transfer MISFET Qt ₁ , Qt ₂ P of the formation region of ^- N on the main surface of the mold well 2 ⁺ Each type semiconductor region 18 is formed.
[0101]
MISFET Qd for driving ₁ , Qd ₂ P of the formation region of ^- Since the n-type semiconductor region 10 is formed in advance on the main surface of the mold well 2, n ⁺ Drive semiconductor MISFET Qd having a source region and a drain region of a double diffusion drain structure by forming a type semiconductor region 11 ₁ , Qd ₂ Is completed. Also, the transfer MISFET Qt ₁ , Qt ₂ P of the formation region of ^- Since the n-type semiconductor region 17 is formed in advance on the main surface of the mold well 2, n ⁺ Transfer type MISFET Qt having a source region and a drain region of an LDD structure by forming the semiconductor region 18 ₁ , Qt ₂ Is completed (FIG. 14).
[0102]
Next, an insulating film 21 made of a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1. This insulating film 21 is formed by the CVD method, and its film thickness is about 54 to 66 nm. Next, a photoresist film is formed on the insulating film 21, and using this as a mask, the insulating film 21, the insulating film 8, and the insulating film (transfer MISFET Qt ₁ , Qt ₂ MISFET Qt for transfer by etching the insulating film in the same layer as the gate insulating film 12 of ₁ , Qt ₂ A contact hole 22 is formed on one of the source region and the drain region. At the same time, using the photoresist film as a mask, the insulating film 21 and the insulating film (transfer MISFET Qt ₁ , Qt ₂ MISFET Qt for transfer by etching the insulating film in the same layer as the gate insulating film 12 of ₁ , Qt ₂ The other of the source region to the drain region (driving MISFET Qd ₁ , Qd ₂ A contact hole 22 is formed above one of the source region and the drain region.
[0103]
Next, a polycrystalline silicon film as a third-layer gate material is deposited on the entire surface of the semiconductor substrate 1. This polycrystalline silicon film is formed by the CVD method, and the film thickness is about 63 to 77 nm. In this polycrystalline silicon film, P is introduced during deposition in order to reduce its resistance value. Next, after etching the polycrystalline silicon film using the photoresist film formed on the polycrystalline silicon film as a mask, the photoresist film is removed by ashing, whereby the load MISFET Qp ₁ , Qp ₂ The gate electrode 23A and the pad layer 23B are respectively formed (FIG. 15).
[0104]
Next, the load MISFET Qp is formed on the entire surface of the semiconductor substrate 1. ₁ , Qp ₂ After depositing the gate insulating film 24 by the CVD method, a photoresist film is formed on the gate insulating film 24, and the gate insulating film 24 is etched using the photoresist film as a mask to thereby load the MISFET Qp for load. ₁ , Qt ₂ A contact hole 25 is formed above the gate electrode 23A.
[0105]
Next, a polycrystalline silicon film which is a fourth-layer gate material is deposited on the entire surface of the semiconductor substrate 1. This polycrystalline silicon film is formed by the CVD method, and the film thickness is about 36 to 44 nm. Next, using the photoresist film formed on the polycrystalline silicon film as a mask, the load MISFET Qp ₁ , Qp ₂ P is ion-implanted into the polycrystalline silicon film in the region where the channel region 26N is to be formed. Next, the photoresist film is removed by ashing, and then the load MISFET Qp is formed using the photoresist film newly formed on the polycrystalline silicon film as a mask. ₁ , Qp ₂ Source region 26P, drain region 26P and power supply voltage line (V _CC BF on the polycrystalline silicon film in the region where 26P is formed ₂ Ion implantation.
[0106]
Next, after removing the photoresist film by ashing, the polycrystalline silicon film is etched using the photoresist film newly formed on the polycrystalline silicon film as a mask, thereby loading the MISFET Qp for load. ₁ , Qp ₂ Channel region 26N, source region 26P, drain region 26P and power supply voltage line (V _CC ) 26P is formed. At the same time, using this photoresist film as a mask, the MISFET Qp for loading under the polycrystalline silicon film ₁ , Qp ₂ The gate insulating film 24 is etched to form a load MISFET Qp formed under the gate insulating film 24. ₁ , Qp ₂ A part of each of the gate electrode 23A and the pad layer 23B is exposed (FIG. 16).
[0107]
Next, after the photoresist film is removed by ashing, a load MISFET Qp ₁ , Qp ₂ A thin oxide film is formed by thermal oxidation on each surface of the channel region 26N, the source region 26P, the drain region 26P and the gate electrode 23A partially exposed. This oxide film is a load MISFET Qp. ₁ , Qp ₂ It is formed to improve the breakdown voltage.
[0108]
Next, the capacitive element C is formed on the entire surface of the semiconductor substrate 1. ₁ , C ₂ An insulating film 27 to be a dielectric film is deposited by the CVD method. The insulating film 27 is composed of a laminated film of a silicon oxide film and a silicon nitride film. The thickness of the lower silicon oxide film is about 13 to 17 nm, and the thickness of the upper silicon nitride film is about 5 to 7 nm. .
[0109]
Next, using the photoresist film formed on the insulating film 27 as a mask, the insulating film 27 on the pad layer 23B is removed by etching, and then the photoresist film is removed by ashing. Next, a polycrystalline silicon film as a fifth-layer gate material is deposited on the entire surface of the semiconductor substrate 1. This polycrystalline silicon film is formed by the CVD method, and the film thickness is about 27 to 33 nm. This polycrystalline silicon film introduces P at the time of deposition in order to reduce its resistance value.
[0110]
Next, the polycrystalline silicon film is etched using the photoresist film formed on the polycrystalline silicon film as a mask. As a result, the load MISFET Qp ₁ , Qp ₂ A plate electrode 28 having an opening 29A above the drain region 26P and an opening 29B above the pad layer 23B is completed. This also causes the load MISFET Qp. ₁ , Qp ₂ The capacitor element C having a stack structure in which the gate electrode 23A is a first electrode, the plate electrode 28 is a second electrode, and the insulating film 27 between the gate electrode 23A and the plate electrode 28 is a dielectric film. ₁ , C ₂ Is completed.
[0111]
At the same time, only the upper silicon nitride film of the insulating film 27 (laminated film of silicon oxide film and silicon nitride film) below the polycrystalline silicon film is etched using the photoresist film as a mask. By this etching, only the upper silicon nitride film is removed from the insulating film 27 exposed at the bottom of the opening 29A and the opening 29B of the plate electrode 28 and the peripheral circuit forming region. In addition, this etching is performed by overetching the lower silicon oxide film to load MISFET Qp. ₁ , Qp ₂ In order to prevent the channel region 26N, the gate electrode 23A, and the like from being exposed, _Four + O ₂ Isotropic etching using an etching gas such as is performed (FIG. 17).
[0112]
As described above, the SRAM of this embodiment includes the capacitor element C. ₁ , C ₂ A part of the insulating film 27 constituting the dielectric film is made of a silicon nitride film having a higher withstand voltage than the silicon oxide film. With this configuration, the insulating film 27 can be made thinner as compared with the case where the dielectric film is formed of a single layer of silicon oxide film. ₁ , C ₂ Capacity can be increased.
[0113]
Also, MISFET Qp for load ₁ , Qp ₂ A part of the insulating film 27 covering the upper layer is made of a silicon nitride film having higher water resistance than the silicon oxide film, so that the load MISFET Qp can be formed from the surface of the semiconductor chip 1. ₁ , Qp ₂ Since it is possible to prevent moisture from entering the MISFET Qp for loading due to moisture penetration ₁ , Qp ₂ Thus, stable operation of the memory cell MC can be ensured.
[0114]
Further, the manufacturing method of the SRAM of the present embodiment is the same as that of the load MISFET Qp. ₁ , Qp ₂ After the gate insulating film 24 on the gate electrode 23A is etched to expose a part of the gate electrode 23A, the load MISFET Qp ₁ , Qp ₂ Capacitor C on the upper layer ₁ , C ₂ An insulating film 27 constituting the dielectric film is deposited. With this configuration, the load MISFET Qp ₁ , Qp ₂ Since the dielectric film between the electrode plate 28 and the plate electrode 28 can be thinned, the capacitive element C ₁ , C ₂ Capacity can be increased.
[0115]
In addition, in the SRAM manufacturing method of this embodiment, when the plate electrode 28 covering the memory cell array is formed by etching the polycrystalline silicon film which is the fifth-layer gate material, the insulation under the polycrystalline silicon film is formed. The silicon nitride film constituting a part of the film 27 is etched at the same time, and the silicon nitride film at the bottom of the opening 29A and the opening 29B of the plate electrode 28 and the peripheral circuit forming region is removed. With this configuration, it is possible to suppress fluctuations in the threshold voltage of the peripheral circuit (a MISFET constituting the peripheral circuit) due to the provision of a silicon nitride film through which hydrogen does not easily pass over the peripheral circuit, thereby ensuring stable operation of the SRAM. be able to.
[0116]
Next, after removing the photoresist film used for etching the plate electrode 28 by ashing, an insulating film 31 made of a silicon oxide film and an interlayer insulating film 32 made of BPSG are sequentially deposited on the entire surface of the semiconductor substrate 1. The insulating film 31 is formed by the CVD method, and the film thickness is about 135 to 165 nm. The interlayer insulating film 32 is formed by the CVD method, and the film thickness is about 270 to 330 nm.
[0117]
Next, using the photoresist film formed on the interlayer insulating film 32 as a mask, the interlayer insulating film 32 and the insulating film 31 are etched, and the transfer MISFET Qt ₁ , Qt ₂ After the contact hole 34 is formed on the pad layer 23B disposed on the upper layer of one of the source region and the drain region, the photoresist film is removed by ashing.
[0118]
Next, a tungsten film which is a first layer wiring material is deposited on the entire surface of the semiconductor substrate 1. This tungsten film is formed by sputtering and has a thickness of about 300 nm. Next, the tungsten film is etched using the photoresist film formed on the tungsten film as a mask to form the intermediate conductive layer 33, the sub word line SWL, and the main word line MWL, and then the photoresist film is removed by ashing ( FIG. 18).
[0119]
Next, an interlayer insulating film 35 composed of a three-layer film in which a silicon oxide film, a spin-on-glass film, and a silicon oxide film are sequentially stacked is deposited on the entire surface of the semiconductor substrate 1. The silicon oxide film is oxygen (O ₂ ) And tetraethoxysilane (Si (OC ₂ H _Five ) _Four ) With a source gas as the source gas, and the thickness of the lower silicon oxide film is about 450 to 550 nm and the upper silicon oxide film is about 360 to 440 nm. The film thickness of the spin-on-glass film is about 235 to 265 nm.
[0120]
By forming the silicon oxide film constituting a part of the interlayer insulating film 35 by the above-described plasma CVD method using the source gas, a large amount of hydrogen ions are contained in the film of the interlayer insulating film 35 and will be described later. Since the hydrogen supplied in the hydrogen annealing step is easily transmitted through the interlayer insulating film 35, the load MISFET Qp ₁ , Qp ₂ Sufficient hydrogen atoms can be supplied to dangling bonds (dangling bonds) existing on the crystal grain boundary surface of the polycrystalline silicon film constituting.
[0121]
Next, the interlayer insulating film 35 is etched using the photoresist film formed on the interlayer insulating film 35 as a mask to form a contact hole 36 above the intermediate conductive layer 33, and then the photoresist film is removed by ashing. .
[0122]
Next, a second-layer wiring material is deposited on the entire surface of the semiconductor substrate 1. This wiring material is composed of a three-layer film in which a TiW film, an aluminum alloy film, and a TiW film are sequentially laminated. The TiW film is formed by sputtering, and the film thickness is about 60 nm for the lower TiW film and about 200 nm for the upper TiW film. The aluminum alloy film is formed by sputtering, and the film thickness is about 800 nm. Subsequently, by using the photoresist film formed on the TiW film as a mask, the TiW film, the aluminum alloy film, and the TiW film are sequentially etched, thereby completing the complementary data line DL (first data line DL). ₁ And the second data line DL ₂ ).
[0123]
Next, after the photoresist film is removed by ashing, a final passivation film 37 made of a laminated film of a silicon oxide film and a silicon nitride film is deposited on the entire surface of the semiconductor substrate 1. The silicon oxide film is formed by a plasma CVD method using oxygen and tetraethoxysilane as source gases, and the silicon nitride film is monosilane (SiH _Four ) And nitrogen (or ammonia) as a source gas. By forming the silicon oxide film and the silicon nitride film constituting the final passivation film 37 by the plasma CVD method, a large amount of hydrogen ions are contained in the final passivation film 37, and this is the load MISFET Qp. ₁ , Qp ₂ It becomes a hydrogen supply source to the polycrystalline silicon film constituting the film.
[0124]
In this embodiment, hydrogen annealing is performed in the middle of the process of depositing the final passivation film 37, and the load MISFET Qp ₁ , Qp ₂ Hydrogen is supplied to the polycrystalline silicon film constituting the film. First, after depositing a silicon oxide film of about 360 to 440 nm, hydrogen annealing is performed in a nitrogen atmosphere containing hydrogen at about 400 ° C. for about 30 minutes, and then a silicon oxide film is deposited about 360 to 440 nm. Finally, a silicon nitride film is deposited on the silicon oxide film by about 1.2 μm.
[0125]
By the hydrogen annealing, the load MISFET Qp is passed through the interlayer insulating film 35, the interlayer insulating film 32, and the insulating film 31. ₁ , Qp ₂ Hydrogen is supplied to the polycrystalline silicon film constituting the film. Note that the SRAM of this embodiment has a load MISFET Qp. ₁ , Qp ₂ Between the polycrystalline silicon film (fourth layer gate material) and the upper layer plate electrode 28 (fifth layer gate material) constituting the channel region 26N, source region 26P and drain region 26P A part of the film (insulating film 27) is made of a silicon nitride film that is difficult for hydrogen atoms to permeate. By providing an opening 29A in a part of the plate electrode 28, a load is applied through the opening 29A. MISFETQp ₁ , Qp ₂ Sufficient hydrogen can be supplied to the polycrystalline silicon film constituting the film.
[0126]
As described above, the SRAM of the present embodiment is loaded with hydrogen supplied in the hydrogen annealing step and hydrogen contained in the interlayer insulating film 35 and the final passivation film 37 through the opening 29A provided in a part of the plate electrode 28. MISFETQp ₁ , Qp ₂ To supply. With this configuration, the load MISFET Qp ₁ , Qp ₂ Since sufficient hydrogen atoms can be supplied to dangling bonds (dangling bonds) existing on the crystal grain boundary surface of the polycrystalline silicon film constituting the MISFET, the load MISFET Qp ₁ , Qp ₂ The mutual conductance (Gm) is improved, and the characteristics of the SRAM memory cell MC are improved.
[0127]
Through the above steps, the SRAM memory cell MC shown in FIG. 1 is completed. Thereafter, the semiconductor chip 1 is sealed in a package with a resin (not shown).
[0128]
(Example 2)
MISFET Qp for load of memory cell MC of the first embodiment ₁ , Qp ₂ Has a so-called bottom gate structure in which a channel region, a source region, and a drain region are arranged on the upper portion of a gate electrode. ₁ , Qp ₂ Has a so-called top gate structure in which a gate electrode is arranged above the channel region, the source region, and the drain region.
[0129]
FIG. 19 is an overall schematic configuration (chip layout) diagram of the SRAM of this embodiment, and FIG. 20 is an enlarged schematic configuration diagram showing a part thereof.
[0130]
The main surface of the rectangular semiconductor chip 1 is not particularly limited. For example, an SRAM having a large capacity of 16 megabits (Mbit) is formed. The memory cell array of this SRAM has four memory blocks MB (MB ₁ ~ MB _Four Each memory block MB is composed of 32 subarrays SMA. Each subarray SMA is composed of memory cells of 1024 rows × 128 columns.
[0131]
A load circuit LOAD is disposed at one end of each memory block MB, and a Y selector circuit YSW, a Y decoder circuit YDEC, and a sense amplifier circuit SA are disposed at the other end. In addition, an X decoder circuit XDEC is arranged at the center of each memory block MB.
[0132]
As shown in FIG. 20, a word decoder circuit WDEC is arranged at one end of each subarray SMA constituting the memory block MB. The word decoder circuit WDEC is selected by the X decoder circuit XDEC via a main word line MWL extending in the column direction above the memory block MB.
[0133]
The word decoder circuit WDEC selects a word line WL extending in parallel with the sub word line SWL via a sub word line SWL extending in the column direction above the sub array SMA. The word line WL is arranged for each memory cell MC arranged in the column direction, and two word lines WL (first word line and second word line) to which the same selection signal is applied are provided to each memory cell MC. Is connected.
[0134]
A complementary data line DL extending in a direction (row direction) intersecting the main word line MWL, the sub word line SWL, and the word line WL is disposed on the subarray SMA. The complementary data lines DL include two data lines (first data lines DL) extending in parallel with each other. ₁ Second data line DL ₂ For each memory cell MC arranged in the row direction. One end of the complementary data line DL is connected to the load circuit LOAD, and the other end is connected to the sense amplifier circuit SA via the Y selector circuit YSW.
[0135]
As shown in FIGS. 19 and 20, the SRAM of this embodiment selects one of the word decoder circuits WDEC of the subarray SMA via the main word line MWL by the X decoder circuit XDEC, and this selected word decoder. The circuit WDEC uses the word line WL (first word line WL) via the sub word line SWL. ₁ And the second word line WL ₂ ) Is selected. As will be described later, the word line WL is composed of a second-layer gate material, and the sub-word line SWL is composed of a first-layer wiring material.
[0136]
That is, the SRAM of the present embodiment has a set of word lines WL (first word lines WL) among a plurality of word lines WL extending on the subarray SMA. ₁ And the second word line WL ₂ ) Is selected by the word decoder circuit WDEC and the X decoder circuit XDEC, and this set of first word lines WL is adopted. ₁ And the second word line WL ₂ A double word line system is used in which the word decoder circuit WDEC is connected through the sub word line SWL.
[0137]
The X decoder circuit XDEC, Y selector circuit YSW, Y decoder circuit YDEC, sense amplifier circuit SA, load circuit LOAD, etc. arranged in each memory block MB constitute SRAM peripheral circuits. These peripheral circuits are formed of CMOS, and control information writing operation, holding operation, reading operation and the like of the memory cell MC.
[0138]
FIG. 21 is a cross-sectional view of the main part of the semiconductor substrate showing the memory cell MC of the SRAM of this embodiment, and FIGS. 22 to 28 show the pattern layout of the conductive layer constituting the memory cell MC separately for each conductive layer. It is a principal part top view.
[0139]
As shown in FIG. ^- The main surface of the semiconductor substrate 1 made of type silicon single crystal is p ^- A mold well 2 is formed and this p ^- On the main surface of the inactive region of the mold well 2, an element isolation field insulating film 4 made of a silicon oxide film is formed. Under this field insulating film 4, a p-type channel stopper region 5 for preventing inversion is formed.
[0140]
Transfer MISFETQt constituting SRAM memory cell MC ₁ , Qt ₂ , MISFET Qd for driving ₁ , Qd ₂ And load MISFETQp ₁ , Qp ₂ MISFET Qt for transfer ₁ , Qt ₂ And MISFET Qd for driving ₁ , Qd ₂ Each of which is p surrounded by the field insulating film 4. ^- MISFET Qp for load formed on the main surface of the active region of the mold well 2 ₁ , Qp ₂ Is the MISFET Qd for driving ₁ , Qd ₂ It is formed in the upper layer.
[0141]
As shown in FIGS. 21 and 22, the driving MISFET Qd ₁ , Qd ₂ Consists of a gate insulating film 6, a gate electrode 7, a source region and a drain region. The source region and the drain region are n above the n-type semiconductor region 10. ⁺ A double diffusion drain structure in which a type semiconductor region 11 is formed. FIG. 21 shows two drive MISFETs Qd. ₁ , Qd ₂ Drive MISFET Qd ₁ One of the semiconductor regions (10, 11) and the driving MISFET Qd ₂ The gate electrode 7 and one semiconductor region (10, 11) are shown.
[0142]
MISFET Qd for driving ₁ , Qd ₂ The gate electrode 7 is formed in the first-layer gate material forming step, and is formed of, for example, a polycrystalline silicon film. In this polycrystalline silicon film, an n-type impurity (phosphorus or arsenic) is introduced in order to reduce the resistance value. An insulating film 8 for electrically separating the gate electrode 7 from the upper conductive layer is formed on the gate electrode 7. The insulating film 8 is made of, for example, a silicon oxide film.
[0143]
As shown in FIGS. 21 and 23, the transfer MISFET Qt of the memory cell MC. ₁ , Qt ₂ P is surrounded by the field insulating film 4 ^- It is formed on the main surface of the active region of the mold well 2. MISFETQt for transfer ₁ , Qt ₂ Consists of a gate insulating film 12, a gate electrode 13A, a source region and a drain region. The source region and the drain region are composed of a low impurity concentration n-type semiconductor region 17 and a high impurity concentration n-type semiconductor region 17. ⁺ And a type semiconductor region 18. That is, the transfer MISFET Qt ₁ , Qd ₂ The source region and drain region of each have an LDD structure. FIG. 21 shows two transfer MISFETs Qt. ₁ , Qt ₂ MISFET Qt for transfer ₁ The gate insulating film 12, the gate electrode 13A, and one semiconductor region (17, 18) are shown.
[0144]
Transfer MISFETQt ₁ , Qt ₂ The gate electrode 13A is formed in the second-layer gate material forming step, and is made of, for example, a polycide film. An n-type impurity (phosphorus or arsenic) is introduced into the polycrystalline silicon film constituting a part of the polycide film in order to reduce its resistance value. The gate electrode 13A is configured integrally with the word line WL. That is, the transfer MISFET Qt ₁ The gate electrode 13A of the first word line WL ₁ MISFET Qt for transfer ₂ The gate electrode 13A of the second word line WL ₂ It is composed integrally with.
[0145]
An insulating film 15 for electrically separating the gate electrode 13A from the upper conductive layer is formed on the gate electrode 13A. The insulating film 15 is made of, for example, a silicon oxide film. Further, a sidewall spacer 16 made of a silicon oxide film is formed on the side wall in the gate length direction of the gate electrode 13A.
[0146]
As shown in FIGS. 21 and 24, the driving MISFET Qd ₁ , Qd ₂ And the transfer MISFETQt ₁ , Qt ₂ In the upper layer, a reference voltage line (V _SS 40A is arranged. This reference voltage line (V _SS 40A is a driving MISFET Qd ₁ , Qd ₂ Drive MISFET Qd through contact hole 14 formed in the same insulating film as gate insulating film 6 of ₁ , Qd ₂ Source region (n ⁺ Type semiconductor region 11). Reference voltage line (V _SS 40A is formed in the third-layer gate material forming step, and the transfer MISFETQt ₁ , Qt ₂ Like the gate electrode 13A, for example, a polycide film is used. An n-type impurity (phosphorus or arsenic) is introduced into the polycrystalline silicon film constituting a part of the polycide film in order to reduce the resistance value.
[0147]
Transfer MISFETQt ₁ , Qt ₂ N of ⁺ On the upper layer of the type semiconductor region 18 (drain region), a reference voltage line (V _SS ) A pad layer 40B formed of the same third-layer gate material as 40A is disposed. This pad layer 40B is composed of a transfer MISFET Qt. ₁ , Qt ₂ N through the contact hole 22 formed in the same insulating film as the gate insulating film 12 ⁺ It is connected to the type semiconductor region 18 (drain region).
[0148]
As shown in FIGS. 21 and 25, the load MISFET Qp of the memory cell MC ₁ , Qp ₂ MISFET Qp for load ₁ Is the MISFET Qd for driving ₂ MISFET Qp for load ₂ Is the MISFET Qd for driving ₁ It is arranged on the area. MISFET Qp for load ₁ , Qp ₂ Each of these comprises a p-type source region 41P, a drain region 41P, an n-type channel region 41N, a gate insulating film 42, and a gate electrode 43. FIG. 21 shows the load MISFET Qp. ₁ Source region 41P, drain region 41P, channel region 41N and gate insulating film 42, and load MISFET Qp ₂ The gate electrode 43 is shown.
[0149]
MISFET Qp for load ₁ The channel region 41N is connected to the driving MISFET Qd via the insulating film 44 and the insulating film 45. ₂ It is formed in the upper layer. MISFET Qp for load ₂ The channel region 41N of the MISFET Qd for driving is interposed through the insulating film 44 and the insulating film 45. ₁ It is formed in the upper layer. The insulating film 44 and the insulating film 45 are made of, for example, a silicon oxide film.
[0150]
MISFET Qp for load ₁ , Qp ₂ Each of the channel regions 41N is formed in the fourth-layer gate material forming step, and is made of, for example, a polycrystalline silicon film. On part (source side) or the entire surface of this polycrystalline silicon film, a load MISFET Qp ₁ , Qp ₂ An n-type impurity (for example, P) is introduced to set the threshold voltage of the enhancement type to the enhancement type.
[0151]
MISFET Qp for load ₁ , Qp ₂ A drain region 41P is formed on one end side of each channel region 41N, and a source region 41P is formed on the other end side. The drain region 41P and the source region 41P are composed of the same fourth-layer gate material (polycrystalline silicon film) as the channel region 41N, and are configured integrally with the channel region 41N. Of the fourth-layer gate material, p-type impurities (boron) are introduced into the polycrystalline silicon film in the regions constituting the drain region 41P and the source region 41P.
[0152]
MISFET Qp for load ₁ , Qp ₂ Each of the gate insulating films 42 of the MISFET Qp for load ₁ , Qp ₂ The channel region 41N, the drain region 41P, and the source region 41P are formed on the polycrystalline silicon film. The gate insulating film 42 is made of, for example, a silicon oxide film having a thickness of about 10 to 60 nm.
[0153]
As shown in FIGS. 21 and 26, the load MISFET Qp ₁ , Qp ₂ Each of the gate electrodes 43 is formed in an upper layer of the gate insulating film 42.
[0154]
The gate electrode 43 is formed in the fifth-layer gate material forming step, and is composed of, for example, a polycrystalline silicon film. In this polycrystalline silicon film, an n-type impurity (for example, phosphorus) is introduced in order to reduce the resistance value.
[0155]
MISFET Qp for load ₁ , Qp ₂ The power supply voltage (V _CC ) MISFET Qp for load to which is applied ₁ , Qp ₂ In the OFF state, a strong electric field is applied between the gate electrode 43 and the drain region 41P in the state of the reference voltage (Vss) below the gate electrode 43, so that a leakage current is generated between the source region 41P and the drain region 41P. In order to prevent problems that occur, the drain region 41P and the gate electrode 43 are separated from each other via the channel region 41N. That is, MISFET Qp for load ₁ , Qp ₂ Has a so-called offset structure in which the drain region 41P and the gate electrode 43 are separated without overlapping. FIG. 27 shows the load MISFET Qp. ₁ , Qp ₂ The offset area 41off is shown in a shaded pattern.
[0156]
MISFET Qp for load ₁ , Qp ₂ MISFET Qp for load ₁ The gate electrode 43 is connected to the driving MISFET Qd through the contact hole 46. ₂ One semiconductor region (drain region) 11 (transfer MISFET Qt ₂ Is connected to one of the semiconductor regions 18). Although not shown in FIG. 21, similarly, the load MISFET Qp ₂ The gate electrode 43 is connected to the driving MISFET Qd through a contact hole 46 formed by opening the gate insulating film 42, the insulating film 45, the insulating film 8, and the like. ₁ One semiconductor region (drain region) 11 (transfer MISFET Qt ₁ Is connected to one of the semiconductor regions 18).
[0157]
MISFET Qp for load ₂ Gate electrode 43 and driving MISFET Qd ₁ One semiconductor region (drain region) 11 (transfer MISFET Qt ₁ The load MISFET Qp is formed on the side wall of the contact hole 46 that is connected to one of the semiconductor regions 18). ₁ The exposed drain region 41P is exposed, and the exposed drain region 41P and the gate electrode 43 are electrically connected by the wall surface of the side wall of the contact hole 46. Further, the drive MISQd is provided on the side wall of the contact hole 46. ₂ The main surface of one end of the gate electrode 7 is exposed, and the exposed gate electrode 7 and the load MISFET Qp ₂ The gate electrode 43 is electrically connected to the wall surface of the side wall of the contact hole 46.
[0158]
That is, MISFET Qp for load ₂ Gate electrode 43 and driving MISFET Qd ₁ One semiconductor region (drain region) 11 (transfer MISFET Qt ₁ One semiconductor region 18) and a load MISFET Qp ₁ Drain region 41P and driving MISQd ₂ The gate electrodes 7 are connected to each other through one contact hole 46.
[0159]
Although not shown in FIG. 21, similarly, the load MISFET Qp ₁ Gate electrode 43 and driving MISFET Qd ₂ One semiconductor region (drain region) 11 (transfer MISFET Qt ₂ The load MISFET Qp is formed on the side wall of the contact hole 46 connecting to one of the semiconductor regions 18). ₂ The exposed drain region 41P is exposed, and the exposed drain region 41P and the gate electrode 43 are electrically connected by the wall surface of the side wall of the contact hole 46. Further, on the side wall of the contact hole 46, a driving MISFET Qd ₁ The main surface of one end of the gate electrode 7 is exposed, and the exposed gate electrode 7 and the load MISFET Qp ₁ The gate electrode 43 is electrically connected to the wall surface of the side wall of the contact hole 46.
[0160]
That is, MISFET Qp for load ₁ Gate electrode 43 and driving MISFET Qd ₂ One semiconductor region (drain region) 11 (transfer MISFET Qt ₂ One semiconductor region 18) and a load MISFET Qp ₂ Drain region 41P and driving MISQd ₁ The gate electrodes 7 are connected to each other through one contact hole 46.
[0161]
As shown in FIGS. 21 and 27, the load MISFET Qp ₁ , Qp ₂ A plate electrode 48 is disposed above the gate electrode 43 with an insulating film 47 interposed therebetween. The plate electrode 48 is formed in the sixth-layer gate material forming step, and is composed of, for example, a polycrystalline silicon film. An n-type impurity (for example, P) is introduced into the polycrystalline silicon film. The plate electrode 48 is formed so as to cover the entire area of the memory cell MC. The plate electrode 48 is used for the power supply voltage (V _CC ) It is connected to the. In the SRAM memory cell MC of this embodiment, the power supply voltage (Vcc) and the second power supply voltage (Vcc) shown in FIG. ₁ ) Is commonly used.
[0162]
The SRAM memory cell MC of this embodiment includes two capacitive elements C. ₁ , C ₂ Is provided. In the case of the SRAM of this embodiment, this capacitive element C ₁ , C ₂ Is the load MISFETQp ₁ , Qp ₂ And the plate electrode 48. That is, this capacitive element C ₁ , C ₂ Is the load MISFETQp ₁ , Qp ₂ The gate electrode 43 is a first electrode, the plate electrode 48 is a second electrode, and the insulating film 47 between the gate electrode 43 and the plate electrode 48 is a dielectric film. The insulating film 47 is composed of, for example, a laminated film of a silicon oxide film having a thickness of about 5 to 30 nm and a silicon nitride film having a thickness of about 3 to 10 nm. In the present embodiment, the capacitive element C is formed between the upper surface (entire surface) and the side surface of the gate electrode 43 and the plate electrode 48. ₁ , C ₂ Can be formed.
[0163]
As described above, the SRAM of this embodiment has the load MISFET Qp. ₁ , Qp ₂ Between the gate electrode 43 and the large-area plate electrode 48 covering the upper portion of the gate electrode 43 ₁ , C ₂ The capacitive element C ₁ , C ₂ Can be increased in capacity, and the resistance to α-ray soft error of the memory cell MC can be greatly improved.
[0164]
An aperture 49A and an aperture 49B are formed in a part of the plate electrode 48. The opening 49A is a load MISFET Qp. ₁ , Qp ₂ The drain electrode 41 </ b> P is formed on the drain region 41 </ b> P so that the plate electrode 48 does not cover the offset region 41 off. The opening 49B is formed in the upper part of the pad layer 40B formed in the same third-layer gate material forming step as the reference voltage line 40A (Vss).
[0165]
As described above, the SRAM of this embodiment has the load MISFET Qp. ₁ , Qp ₂ An opening 49A is formed in the plate electrode 48 on the upper side of the drain region 41P, and the offset region 41off and the plate electrode 48 are separated from each other through the opening 49A. With this configuration, the power supply voltage (V _CC ) MISFET Qp for load to which is applied ₁ , Qp ₂ In the OFF state, it is possible to prevent a strong electric field from being applied between the plate electrode 48 and the offset region 41off, thereby preventing a leak current from being generated between the source region 41P and the drain region 41P due to the strong electric field. The stable operation of the memory cell MC can be ensured.
[0166]
Note that the other opening 49B formed in the plate electrode 48 includes a pad layer 40B below the plate electrode 48 and a complementary data line DL (first data line DL) above the plate electrode 48. ₁ And the second data line DL ₂ ) Are openings provided so as to be connected to the plate electrode 48 without short-circuiting.
[0167]
As shown in FIGS. 21 and 28, a sub word line SWL is arranged above the plate electrode 48 with an interlayer insulating film 50 interposed therebetween. The sub word line SWL is formed in the first layer wiring material forming step, and is composed of, for example, a laminated film of a barrier metal film and a refractory metal film. The barrier metal is made of, for example, titanium tungsten (TiW), and the refractory metal is made of, for example, tungsten (W). The interlayer insulating film 50 is composed of, for example, a laminated film of a silicon oxide film and a BPSG film.
[0168]
Transfer MISFETQt ₁ , Qt ₂ An intermediate conductive layer 51 formed of the same first-layer wiring material as that of the sub word line SWL is disposed on the upper layer of one of the semiconductor regions (drain regions) 18. The intermediate conductive layer 51 is connected to the transfer MISFET Qt through the interlayer insulating film 50, the insulating film 47, the insulating film 45, and the contact hole 52 formed in the insulating film 44. ₁ , Qt ₂ Are connected to the pad layer 40B formed on one of the semiconductor regions (drain regions) 18.
[0169]
A complementary data line DL is disposed above the sub word line SWL and the intermediate conductive layer 51 via a second-layer interlayer insulating film 53. The complementary data line DL is connected to the intermediate conductive layer 51 through a contact hole 54 opened in the interlayer insulating film 53. The complementary data line DL is formed in the second-layer wiring material forming step, and includes, for example, a three-layer film in which a barrier metal film, an aluminum alloy film, and a barrier metal film are sequentially stacked. The barrier metal is made of, for example, TiW, and the aluminum alloy is made of, for example, aluminum to which Cu and Si are added. The interlayer insulating film 53 is made of, for example, a three-layer film in which a silicon oxide film, a spin-on-glass film, and a silicon oxide film are sequentially stacked. This silicon oxide film is formed by a plasma CVD method using oxygen and tetraethoxysilane as source gases.
[0170]
The complementary data line DL is connected to the transfer MISFET Qt of the memory cell MC. ₁ , Qt ₂ Is connected to one semiconductor region (drain region) 18. Of the complementary data lines DL, the first data line DL ₁ Transfer MISFETQt ₁ Is connected to one semiconductor region (drain region) 18. Although not shown, similarly, the second data line DL ₂ Transfer MISFETQt ₂ Is connected to one semiconductor region (drain region) 18. Complementary data line DL and transfer MISFETQt ₁ , Qt ₂ The connection to one of the semiconductor regions (drain regions) 18 is made through the intermediate conductive layer 51 and the pad layer 40B.
[0171]
A main word line MWL is arranged above the complementary data line DL via a third-layer interlayer insulating film 55. The main word line MWL is formed in the third-layer wiring material forming step, and is composed of, for example, a three-layer film in which the same barrier metal film, aluminum alloy film, and barrier metal film as the second-layer wiring material are sequentially stacked. . The interlayer insulating film 55 is composed of, for example, a four-layer film in which a silicon oxide film, a silicon oxide film, a spin-on glass film, and a silicon oxide film are sequentially stacked. This silicon oxide film is formed by a plasma CVD method using oxygen and tetraethoxysilane as source gases.
[0172]
A final passivation film 56 is formed on the main word line MWL. The final passivation film 56 is composed of, for example, a four-layer film in which a silicon oxide film, a silicon oxide film, a silicon nitride film, and a polyimide resin film are sequentially stacked. The silicon oxide film is formed by a plasma CVD method using oxygen and tetraethoxysilane as source gases, and the silicon nitride film is formed by a plasma CVD method using monosilane and nitrogen (or ammonia) as source gases.
[0173]
In this embodiment, as in the first embodiment, hydrogen annealing is performed during the process of depositing the final passivation film 56, and the load MISFET Qp ₁ , Qp ₂ Hydrogen is supplied to the polycrystalline silicon film constituting the film. By this hydrogen annealing, the load MISFET Qp is passed through the interlayer insulating film 55, the interlayer insulating film 53, and the interlayer insulating film 50. ₁ , Qp ₂ Hydrogen is supplied to the polycrystalline silicon film constituting the film.
[0174]
As described above, the SRAM of the present embodiment has the load MISFET Qp through the opening 49A provided in part of the plate electrode 48 with the hydrogen supplied in the hydrogen annealing step and the hydrogen contained in the interlayer insulating films 55 and 53. ₁ , Qp ₂ To supply. With this configuration, the load MISFET Qp ₁ , Qp ₂ Since sufficient hydrogen atoms can be supplied to dangling bonds (dangling bonds) existing on the crystal grain boundary surface of the polycrystalline silicon film constituting the MISFET, the load MISFET Qp ₁ , Qp ₂ The mutual conductance (Gm) is improved, and the characteristics of the SRAM memory cell MC are improved.
[0175]
Example 3
FIG. 29 is a plan view of the principal part showing the pattern layout of the plate electrode of the present embodiment formed in the fifth-layer gate material forming step, and FIG. 30 shows the arrangement of the plate electrode and the load MISFET below it It is a schematic sectional drawing shown typically.
[0176]
As shown in FIGS. 29 and 30, the SRAM memory cell MC of the present embodiment is different from that of the first embodiment in the shape of the opening 29A provided in the plate electrode 28 (Vcc). In other words, the opening 29A has a load MISFET Qp. ₁ , Qp ₂ The channel region 26N is provided over the entire area. This opening 29A is similar to that of the first embodiment in that the plate electrode 28 (Vcc) is connected to the load MISFET Qp. ₁ , Qp ₂ The channel region 26N is provided so as not to be covered.
[0177]
According to the third embodiment having the opening 29A having the above-described shape, the same effect as that of the first embodiment can be obtained, and the load MISFET Qp in which the reference voltage (Vss) is applied to the gate electrode 23A. ₁ , Qp ₂ In the ON state, since the electric field from the plate electrode 28 located above the channel region 26N does not affect the channel region 26N, the current (ON current) between the source region 26P and the drain region 26P is improved. Can be made. That is, with this configuration, the load MISFET Qp ₁ , Qp ₂ Since the ON current can be improved and the OFF current can be reduced, the load MISFET Qp ₁ , Qp ₂ The stable operation of the memory cell MC can be ensured by improving the ON current / OFF current ratio.
[0178]
The invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Not too long.
[0179]
In the first embodiment, when the polycrystalline silicon film on the dielectric film is etched to form the plate electrode, the silicon nitride film which is a part of the dielectric film is removed at the same time, but this silicon nitride film is not necessarily removed. It is not necessary to do this, and a part of it may remain without being etched.
[0180]
The opening formed in the plate electrode is not limited to the square pattern as shown in FIGS. 8 and 29, and may be a pattern as shown in FIGS. 31 and 32, for example. By forming the opening 29A in a band-like pattern as shown in FIG. 32, the mask alignment margin when forming the opening 29A can be increased.
[0181]
In the first to third embodiments, the memory cell MC in which the plate electrode is formed in the upper layer of the load MISFET has been described. However, the plate electrode may be disposed in the lower layer of the load MISFET. That is, in the first or third embodiment, the gate electrode of the driving MISFET is configured by the first conductive film formed on the main surface of the semiconductor substrate, and the second conductive film formed on the main surface of the semiconductor substrate. The gate electrode of the transfer MISFET is constituted, the plate electrode is formed by the third conductive film formed on the first and second conductive films, and the load MISFET is formed by the fourth conductive film formed on the third conductive film. And the channel region, the source region, and the drain region of the load MISFET are formed by the fifth conductive film formed on the fourth conductive film, and the capacitive element is provided between the load MISFET and the plate electrode. In addition, an opening may be formed in the plate electrode at least under the region where the offset region of the load MISFET is formed.
[0182]
Alternatively, in the second embodiment, the gate electrode of the driving MISFET is configured by the first conductive film formed on the main surface of the semiconductor substrate, and the transfer MISFET is formed by the second conductive film formed on the main surface of the semiconductor substrate. A gate electrode is formed, a plate electrode is formed with a third conductive film formed on the first and second conductive films, a channel region of the load MISFET is formed with a fourth conductive film formed on the third conductive film, A source region and a drain region are configured, a gate electrode of the load MISFET is configured by the fifth conductive film formed on the fourth conductive film, and a capacitive element is configured between the load MISFET and the plate electrode. Alternatively, an opening may be formed in the plate electrode at least under the region where the offset region or channel region of the load MISFET is formed.
[0183]
In the first and third embodiments, the second power supply voltage (Vcc ₁ ) To the same voltage as the power supply voltage (Vcc), but the second power supply voltage (Vcc) ₁ ) May be a voltage different from the power supply voltage (Vcc). For example, the second power supply voltage (Vcc ₁ ) To 1/2 Vcc, the storage node n shown in FIG. ₁ , n ₂ Capacity can be attached to either of them.
[0184]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0185]
(1) According to the present invention, a capacitive element can be formed between the load MISFET and a large-area plate electrode covering the load MISFET, so that a capacitive element can be formed. The α-ray soft error resistance of the memory cell can be improved.
[0186]
(2) According to the present invention, an opening is formed in the plate electrode on the drain region of the load MISFET, and the offset region and the plate electrode are separated from each other so that when the power supply voltage is turned OFF, Application of a strong electric field can be avoided. As a result, leakage current between the source region and the drain region due to this strong electric field can be prevented and the OFF current can be reduced, so that the ON current / OFF current ratio is improved and the stable operation of the memory cell is ensured. can do.
[0187]
(3) According to the present invention, when power is supplied to the plate electrode from the outside of the memory cell array, when power noise enters the semiconductor chip on which the SRAM is formed from the outside, the power noise is supplied to the memory cell. Since direct influence can be avoided, stable operation of the memory cell can be ensured.
[0188]
(4) According to the present invention, by forming a part of the insulating film constituting the dielectric film of the capacitive element with a silicon nitride film having a higher withstand voltage than the silicon oxide film, the dielectric film is formed into a silicon oxide film. Since the thickness can be reduced as compared with a single layer structure, the capacitance of the capacitor can be increased.
[0189]
(5) According to the present invention, the upper layer of the load MISFET is covered with a dielectric film including a silicon nitride film having a higher water resistance than the silicon oxide film, thereby suppressing fluctuations in the characteristics of the load MISFET due to moisture intrusion. Therefore, stable operation of the memory cell can be ensured.
[0190]
(6) According to the present invention, since the dielectric film is formed after removing a part of the gate insulating film on the gate electrode of the load MISFET, the dielectric film can be thinned, and the capacitive element Capacity can be increased.
[0191]
(7) According to the present invention, hydrogen atoms are supplied to dangling bonds (dangling bonds) existing on the grain boundary surface of the polycrystalline silicon film constituting the load MISFET through the openings provided in the plate electrode. As a result, the mutual conductance (Gm) of the load MISFET can be improved.
[0192]
(8) According to the present invention, when the plate electrode covering the memory cell array is formed, the silicon nitride film constituting a part of the dielectric film underneath is simultaneously etched to remove the silicon nitride film on the peripheral circuit. As a result, fluctuations in the threshold voltage of the peripheral circuit (a MISFET constituting the peripheral circuit) due to the provision of a silicon nitride film that hardly allows hydrogen to pass over the peripheral circuit can be suppressed, so that stable operation of the SRAM is ensured. be able to.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a principal part of a semiconductor substrate showing a memory cell of a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 2 is a plan view of a principal part showing a pattern layout of a memory cell of a semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 3 is a plan view of a principal part showing a pattern layout of a memory cell of a semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 4 is a plan view of relevant parts showing a pattern layout of memory cells of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 5 is a plan view of relevant parts showing a pattern layout of memory cells of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 6 is a plan view of a principal part showing a pattern layout of a memory cell of a semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view schematically showing the arrangement of a load MISFET and a plate electrode formed thereon.
FIG. 8 is a plan view of relevant parts showing a pattern layout of a memory cell array in a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 9 is an equivalent circuit diagram of a memory cell in a semiconductor integrated circuit device according to an embodiment of the present invention.
10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the semiconductor integrated circuit device which is one embodiment of the present invention;
FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention;
18 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention; FIG.
FIG. 19 is an overall schematic configuration (chip layout) diagram of a semiconductor integrated circuit device according to another embodiment of the present invention;
20 is an enlarged schematic configuration (chip layout) diagram showing a part of FIG. 19; FIG.
FIG. 21 is a fragmentary cross-sectional view of a semiconductor substrate showing a memory cell of a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 22 is a plan view of relevant parts showing a pattern layout of a memory cell in a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 23 is a plan view of relevant parts showing a pattern layout of a memory cell in a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 24 is a plan view of relevant parts showing a pattern layout of a memory cell in a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 25 is a plan view of relevant parts showing a pattern layout of a memory cell of a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 26 is a plan view of relevant parts showing a pattern layout of a memory cell in a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 27 is a plan view of relevant parts showing a pattern layout of a memory cell in a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 28 is a plan view of relevant parts showing a pattern layout of memory cells in a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 29 is a plan view of relevant parts showing a pattern layout of memory cells in a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 30 is a schematic cross-sectional view schematically showing an arrangement of a load MISFET and a plate electrode formed thereon.
FIG. 31 is a plan view of relevant parts showing a pattern layout of a memory cell array in a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 32 is a plan view of relevant parts showing a pattern layout of a memory cell array in a semiconductor integrated circuit device according to another embodiment of the present invention;
[Explanation of symbols]
1 Semiconductor substrate (semiconductor chip)
2 p ^- Type well
3 areas
4 Field insulation film
5 p-type channel stopper region
6 Gate insulation film
7 Gate electrode
8 Insulating film
9 Sidewall spacer
10 n-type semiconductor region
11 n ⁺ Type semiconductor region
12 Gate insulation film
13A Gate electrode
13B Reference voltage line (V _SS )
14 Contact hole
15 Insulating film
16 Sidewall spacer
17 n-type semiconductor region
18 n ⁺ Type semiconductor region
21 Insulating film
22 Contact hole
23A Gate electrode
23B pad layer
24 Gate insulation film
25 Contact hole
26N channel region
26off offset area
26P source area
26P drain region
26P power supply voltage line (V _CC )
27 Insulating film
28 Plate electrode
29A opening
29B opening
29C contact hole
30 guard ring
31 Insulating film
32 Interlayer insulation film
33 Intermediate conductive layer
34 Contact hole
35 Interlayer insulation film
36 Contact hole
37 Final passivation film
40A Reference voltage line (V _SS )
40B pad layer
41N channel region
41off offset area
41P source region
41P drain region
42 Gate insulation film
43 Gate electrode
44 Insulating film
45 Insulating film
46 Contact hole
47 Insulating film
48 Plate electrode
49A opening
49B opening
50 Interlayer insulation film
51 Intermediate conductive layer
52 Contact hole
53 Interlayer insulation film
54 Contact hole
55 Interlayer insulation film
56 Final passivation film
C ₁ Capacitance element
C ₂ Capacitance element
DL complementary data line
DL ₁ First data line
DL ₂ Second data line
MC memory cell
MWL main word line
Qd ₁ MISFET for driving
Qd ₂ MISFET for driving
Qp ₁ MISFET for load
Qp ₂ MISFET for load
Qt ₁ MISFET for transfer
Qt ₂ MISFET for transfer
SWL sub word line
WL Word line
WL ₁ 1st word line
WL ₂ Second word line
LOAD load circuit
MB memory block
MB ₁ ~ MB _Four Memory block
SA sense amplifier circuit
SMA subarray
WDEC word decoder circuit
XDEC X decoder circuit
YDEC Y decoder circuit
YSW Y selector circuit

Claims (10)

A semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by a transfer MISFET controlled by a word line and a flip-flop circuit composed of a driving MISFET and a load MISFET, which is formed on a main surface of a semiconductor substrate. The first conductive film constitutes the gate electrode of the driving MISFET, the second conductive film formed on the main surface of the semiconductor substrate constitutes the gate electrode of the transfer MISFET, and the first and second conductive films A gate electrode of the load MISFET is formed by a third conductive film formed on the upper layer, and a channel region, a source region, and a drain region of the load MISFET are formed by a fourth conductive film formed on the third conductive film. A plate electrode that covers the memory cell array with a fifth conductive film formed on the fourth conductive film, and the load MI Together constituting a capacitance element between the plate electrode and the FET, the semiconductor integrated circuit device which is characterized by providing an opening in said plate electrode on the channel region on the drain region side of at least the load MISFET. A semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by a transfer MISFET controlled by a word line and a flip-flop circuit composed of a driving MISFET and a load MISFET, which is formed on a main surface of a semiconductor substrate. The first conductive film constitutes the gate electrode of the driving MISFET, the second conductive film formed on the main surface of the semiconductor substrate constitutes the gate electrode of the transfer MISFET, and the first and second conductive films A channel region, a source region and a drain region of the load MISFET are constituted by a third conductive film formed on the upper layer, and a gate electrode of the load MISFET is formed by a fourth conductive film formed on the third conductive layer. A plate electrode that covers the memory cell array with a fifth conductive film formed on the fourth conductive film, and the load MI Together constituting a capacitance element between the plate electrode and the FET, the semiconductor integrated circuit device which is characterized by providing an opening in said plate electrode on the channel region on the drain region side of at least the load MISFET. A semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by a transfer MISFET controlled by a word line and a flip-flop circuit composed of a driving MISFET and a load MISFET, which is formed on a main surface of a semiconductor substrate. The first conductive film constitutes the gate electrode of the driving MISFET, the second conductive film formed on the main surface of the semiconductor substrate constitutes the gate electrode of the transfer MISFET, and the first and second conductive films A plate electrode covering the memory cell array is formed with a third conductive film formed on the upper layer, and a channel region, a source region, and a drain region of the load MISFET are configured with a fourth conductive film formed on the third conductive film. The fifth conductive film formed on the fourth conductive film constitutes the gate electrode of the load MISFET, and the load MI Together constituting a capacitance element between the plate electrode and the FET, the semiconductor integrated circuit device which is characterized by providing an opening in said plate electrode under the channel region on the drain region side of at least the load MISFET. A semiconductor integrated circuit device having an SRAM in which a memory cell is constituted by a transfer MISFET controlled by a word line and a flip-flop circuit composed of a driving MISFET and a load MISFET, which is formed on a main surface of a semiconductor substrate. The first conductive film constitutes the gate electrode of the driving MISFET, the second conductive film formed on the main surface of the semiconductor substrate constitutes the gate electrode of the transfer MISFET, and the first and second conductive films A plate electrode covering the memory cell array is formed by a third conductive film formed on the upper layer, a gate electrode of the load MISFET is formed by a fourth conductive film formed on the third conductive film, and the fourth conductive film is formed. A channel region, a source region and a drain region of the load MISFET are constituted by a fifth conductive film formed on the upper layer of the film, and the load MI Together constituting a capacitance element between the plate electrode and the FET, the semiconductor integrated circuit device which is characterized by providing an opening in said plate electrode under the channel region on the drain region side of at least the load MISFET. 5. The semiconductor integrated circuit device according to claim 1, wherein a power supply voltage is supplied to the plate electrode from outside the memory cell array. 2. The semiconductor integrated circuit device according to claim 1, wherein at least a part of the dielectric film of the capacitive element is formed of a silicon nitride film. After forming the opening in the plate electrode, the silicon nitride film at the bottom of the opening is removed, and then hydrogen is applied to the conductive film constituting the load MISFET through the opening by hydrogenation annealing. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device is supplied. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein when the silicon nitride film at the bottom of the opening is removed, the silicon nitride film in a region for forming a peripheral circuit is simultaneously removed. After etching the conductive film constituting the channel region, source region and drain region of the load MISFET, the insulating film under the conductive film is etched to expose a part of the gate electrode of the load MISFET, and 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a dielectric film of the capacitive element is formed on the conductive film. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a drain region of the load MISFET has an offset structure separated from a gate electrode through a channel region.

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