JP3425157B2 - Semiconductor memory circuit device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to a semiconductor memory circuit device, particularly DRAM (D ynamic R andom
A particularly effective technique to adapt to A ccess M emory).

[0002]

2. Description of the Related Art A memory cell of a DRAM holding 1 [bit] of information is composed of a series circuit of a memory cell selecting MISFET and an information storing capacitive element. The gate electrode of this memory cell selecting MISFET is connected to a word line extending in the row direction. MI for memory cell selection
One semiconductor region of the SFET is connected to the complementary data line which is the first metal wiring layer. The other semiconductor region is connected to one electrode of the information storage capacitive element. A predetermined potential is applied to the other electrode of the information storage capacitive element. Also, the word line is a MISFE for selecting a memory cell.
It is composed of two layers of a gate electrode of T and a second metal wiring layer.

This type of DRAM tends to be highly integrated to reduce the size of memory cells in order to increase the capacity.
When the size of the memory cell is reduced, the size of the information storage capacitive element is also reduced, so that the amount of charge accumulated as information is reduced. Decreasing the amount of accumulated charge decreases the α-ray soft error resistance, especially for large capacity DRA of [1 Mbit] or more.
For M, improving the resistance to α-ray soft error is one of the important technical issues.

On the basis of the above technical problems, a stacked structure (S
The TC structure) tends to be adopted. This information storage capacitor having a stacked structure is configured by sequentially stacking a lower electrode layer, a dielectric film, and an upper electrode layer. The lower electrode layer is connected to the other semiconductor region of the memory cell selecting MISFET and extends to above the gate electrode. The lower electrode layer is patterned to have a predetermined planar shape by subjecting a polycrystalline silicon film deposited by the CVD method to a photolithography technique and an etching technique. The dielectric film is provided along the upper surface and the side surface of the lower electrode layer. The upper electrode layer is provided on the surface of the dielectric film. The upper electrode layer is integrally formed with the upper electrode layer of the information storage capacitor of the stacked structure of another adjacent memory cell, and is used as a common plate electrode. The upper electrode layer is formed of a polycrystalline silicon film like the lower electrode layer.

In such a stacked structure DRAM, in order to achieve higher integration and large capacity, the lower electrode layer is made fin-shaped or the lower electrode layer is extended to the sky, and the side surface of the lower electrode layer is positively connected. A technology for using it as a capacitive portion has been developed. Such a DRAM is disclosed in U.S. Pat. S. P. 4,742,018 or IEDM8
8, page 592-595.

[0006]

According to the study of the present inventor, it was found that the above-mentioned DRAM has the following problems.

In the above-mentioned DRAM, since the lower electrode layer of the information storage capacitive element of the memory cell is extended above the sky, the step difference (elevation difference) between the memory cell array region and the peripheral circuit region becomes very large. . In particular, the step between the gate electrode of the memory cell selecting MISFET in the memory cell array region and the upper and lower electrode layers of the information storage capacitor and the source and drain regions of the MISFET in the peripheral circuit region is significantly large. Become. Here, attention is paid to the step difference when the first metal wiring layer is formed.

If there is a large step between the memory cell array region and the peripheral circuit region as described above, the memory cell array region and the peripheral circuit region do not fall within the depth of focus of the exposure apparatus during the exposure process, for example. There is a problem that the regions cannot be processed at the same time.

Incidentally, the depth of focus of the exposure apparatus for forming a pattern of about 0.5 μm is considered to be about 1.5 μm. Therefore, the step between the memory cell array region and the peripheral circuit region must be set to 0.75 μm or less from the predetermined reference position.

Further, there is a problem in that the manufacturing yield is lowered due to partial etching residue in the etching process due to the above-mentioned step difference or undercoat damage due to overetching.

Further, in the exposure process and the etching process, since the processing accuracy is different between the memory cell array region and the peripheral circuit region, dimensional variations occur between the memory cell array region and the peripheral circuit region, and the processing margin is reduced.
As a result, there is a problem that the degree of integration is reduced.

Further, due to the disconnection of the metal wiring (for example, aluminum) extending over the memory cell array region and the peripheral circuit region due to the above-mentioned step, there is a problem that the manufacturing yield is lowered or the reliability is lowered.

The objects of the present invention are as follows.

(1) To provide a technique capable of improving the degree of integration in a semiconductor memory circuit device.

(2) It is an object of the present invention to provide a technique capable of improving the manufacturing yield of a semiconductor memory circuit device.

(3) To provide a technique capable of improving the electrical reliability of a semiconductor memory circuit device.

(4) To provide a technique capable of improving a processing margin in a semiconductor memory circuit device.

(5) To provide a technique for shortening the manufacturing process of a semiconductor memory circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0020]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) In a semiconductor memory circuit device in which a memory cell is constituted by a series circuit of a memory cell selecting MISFET and a stacked structure information storage capacitive element, a gate electrode is provided in a first area which is a memory cell array area. A first MISFET having source and drain regions, first and second capacitance electrodes and a dielectric film extending on the first insulating film on the gate electrode, and a first MISFET located on the second capacitance electrode. There is a second insulating film and a first wiring located on the second insulating film, and a second region which is a peripheral circuit region has a second MISFE having a gate electrode, a source and a drain region.
T, a first insulating film on the gate electrode, a third insulating film on the first insulating film, a second insulating film on the third insulating film,
There is a second wiring on the second insulating film.

(2) In a semiconductor memory circuit device having a memory cell array in the first region and a peripheral circuit in the second region of the main surface of the semiconductor substrate, the MI located in the second region
The distance from the back surface of the semiconductor substrate of the second wiring connected to the source or drain region of the SFET and the distance from the back surface of the semiconductor substrate of the first wiring in the same layer as the second wiring located in the first region. The difference is 1.5 μm or less.

(3) First MISFET connected in series
A memory cell array in which a memory cell array composed of a memory cell and an information storage capacitive element are arranged in a matrix, and a plurality of second M cells.
In a semiconductor memory circuit device having a peripheral circuit composed of an ISFET, (a) a first gate electrode of a first MISFET and a second gate electrode in a first and second regions on a semiconductor substrate of a first conductivity type, respectively. Forming a second gate electrode of the MISFET of (1), and (b) first conductivity type first electrode in the first and second regions in a self-aligned manner with respect to the first and second gate electrodes. Forming a semiconductor region, (c) forming a sidewall insulating film on the end portions of the first and second gate electrodes, and (d) forming a sidewall insulating film on the second gate electrode and the sidewall insulating film. And (e) forming a third insulating film on the first and second regions on the semiconductor substrate in a self-aligned manner to form a second semiconductor region of the second conductivity type, (e) f) to expose one of the source and drain regions of the first MISFET A step of forming a first opening in the third insulating film, and (g) the information storage for contacting with one of the source and drain regions of the first MISFET through the first opening. Forming a first capacitance electrode of the capacitance element, (h) forming a dielectric film and a second capacitance electrode of the information storage capacitance element on the first capacitance electrode, and (i) Forming a second insulating film on the third insulating film in the first region and the second region of the semiconductor substrate, and (j) the second insulating film in the first and second regions. And a step of forming a wiring layer on the film.

[0024]

According to the above-mentioned means (1) or (3), the second MISF is provided in the second area which is the peripheral circuit area.
Since the third insulating film is provided between the first insulating film and the second insulating film on the gate electrode of ET, the first region in which the memory cell array is located and the first insulating film in the peripheral circuit region are formed. The step difference (elevation difference) between the two regions can be reduced. As a result, the wiring of the memory cell array and the peripheral circuit region can be processed with high accuracy. Further, it is possible to prevent stairs of metal wiring extending over the memory cell array region and the peripheral circuit region.

According to the above-mentioned means (2), the difference in distance between the first wiring located in the first region and the second wiring located in the second region from the back surface of the semiconductor substrate is 1.5 μm. By the following, the step difference between the first region where the memory cell array is located and the second region where the peripheral circuit region is located can be reduced. As a result, the wiring of the memory cell array region and the peripheral circuit region can be processed with high precision, and the step of the metal wiring extending over the memory cell array region and the peripheral circuit region can be prevented.

[0026] In the following, the structure of the present invention, Memoriare
DRA is a memory cell composed of a series circuit of the information storage capacitor of selecting MISFET and stacked structure in Lee
An example in which the present invention is applied to M will be described.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0028]

(Embodiment I) A resin-encapsulated semiconductor device for encapsulating a DRAM according to an embodiment I of the present invention is shown in FIG. 2 (partial sectional plan view).

As shown in FIG. 2, a DRAM (semiconductor pellet) 1 is sealed with an SOJ (Small Out-line J-bend) type resin-sealed semiconductor device 2. The DRAM 1 is mounted on the surface of the tab 3A of the resin-sealed semiconductor device 2 with an adhesive interposed.

The DRAM 1 has a large capacity of 4 [Mbit]. The DRAM 1 is encapsulated in a 350 [mil] resin-encapsulated semiconductor device 2. On the main surface of the DRAM 1, a memory cell array is arranged in which a plurality of memory cells (storage elements) that store 1 [bit] of information are arranged in a matrix. DRAM other than the memory cell array
Direct peripheral circuits and indirect peripheral circuits are arranged on the main surface of 1. The direct peripheral circuit is a circuit for directly controlling the information writing operation and the information reading operation of the memory cell, and includes a row address decoder circuit, a column address decoder circuit, a sense amplifier circuit and the like. The indirect peripheral circuit is a circuit that indirectly controls the operation of the direct peripheral circuit, and includes a clock signal generation circuit, a buffer circuit, and the like.

At the most peripheral portion of the DRAM 1, D
External terminals (bonding pads) BP are arranged on the short side and long side of the RAM 1, respectively. The external terminal BP is connected to the inner lead 3B with the bonding wire 4 interposed. The bonding wire 4 uses an aluminum (Al) wire. Moreover, as the bonding wire 4, a gold (Au) wire, a copper (Cu) wire, a wire covered with an insulating resin on the surface of a metal wire, or the like may be used. The bonding wire 4 is bonded by a bonding method using thermocompression and ultrasonic vibration.

The inner lead 3B is integrally formed with the outer lead 3C. This inner lead 3
B, the outer lead 3C, and the tab 3A are cut from the lead frame and molded. Lead frame
For example, Cu, Fe-Ni (for example, Ni content 42
[%]) Formed of an alloy or the like. A tab suspension lead 3D is connected to the tab 3A on the short side.

Signals to be applied to the outer leads 3C are defined and numbered according to the standard. In FIG. 2, the upper left end is the 1st terminal, the lower left end is the 10th terminal, the lower right end is the 11th terminal, and the upper right end is the 20th terminal.

The DRAM 1, the tab 3A, the bonding wire 4, the inner lead 3B, and the tab suspension lead 3D.
Is sealed with a resin sealing portion 5. The resin sealing portion 5 uses an epoxy resin to which a phenol type curing agent, silicone rubber and a filler are added in order to reduce the stress. Silicone rubber has the effect of reducing the coefficient of thermal expansion of the epoxy resin. The filler is formed of spherical silicon oxide particles and similarly has a function of lowering the coefficient of thermal expansion.

Next, a schematic structure of the DRAM 1 which is a semiconductor memory circuit device in the resin-sealed semiconductor device 2 is shown in FIG.
(Chip layout diagram).

As shown in FIG. 3, a memory cell array (MA) 11 is arranged on the surface of the central portion of DRAM 1. Although not limited to this, the DRAM 1 of the present embodiment is composed of a total of 16 memory cell arrays 11. Each memory cell array 11 has 256 [kbit]
It is composed of a capacity of.

The two memory cell arrays 11 are arranged on both sides of the column address decoder circuit (YDEC) 12 and the sense amplifier circuit (SA) 13. The sense amplifier circuit 13 is composed of complementary MISFET (CMOS),
A part of the sense amplifier circuit 13 is an n-channel MISFET
It is composed of. The p-channel MISFET, which is the other part of the sense amplifier circuit 13, is arranged at the end of the memory cell array 11 at a position facing the part. From the one end side of the sense amplifier circuit 13, the complementary data line (2
The data lines of the book extend over the memory cell array 11, and the DRAM 1 of this embodiment adopts the folded bit line system (two-intersection system).

A row address decoder circuit (XDEC) 14 and a word driver circuit (WD) are provided at one end on the center side of each of the 16 memory cell arrays 11.
15 are arranged.

[0039] Then, column address de-coder circuit (Y
DEC) 12, and sense amplifier circuit (SA) 13,
A memory mat is composed of two memory cell arrays 11 arranged so as to sandwich them, and a row address decoder circuit (XDEC) 14 and a word driver circuit (WD) 15 arranged at the end of the memory cell array 11. .
Therefore, the DRAM 1 of this embodiment is composed of eight memory mats.

Peripheral circuit 1 constituting these memory mats
2 to 16 are called direct peripheral circuits of the DRAM 1.

An upper peripheral circuit 1 is provided on the upper side of the DRAM 1.
6, the lower side peripheral circuit 17 is arranged on the lower side. DR
An intermediate peripheral circuit 18 is arranged between the four memory mats arranged on the upper side of AM1 and the four memory mats arranged on the lower side. In addition, between two memory mats arranged on the upper side of the DRAM 1, two arranged on the lower side.
A central peripheral circuit 19 is arranged between each memory mat. These peripheral circuits 16 to 19 are the DRAM 1
Is configured as an indirect peripheral circuit of.

Next, a main part of the memory mat of the DRAM 1 and a main part of the indirect peripheral circuit will be described with reference to FIG. 4 (equivalent circuit diagram of main part).

As shown in FIG. 4, in the DRAM 1 which adopts the folded bit line system, complementary data lines DL and inversion DL are extended in the column direction in the memory cell array (MA) 11. Plural sets of the complementary data lines DL are arranged in the row direction. The complementary data line DL is connected to the sense amplifier circuit (SA) 13.

In the memory cell array 11, the work
The drain lines WL extend in the row direction crossing the complementary data lines DL. A plurality of word lines WL are arranged in the column direction. Although not shown in FIG. 4, each word line WL is connected to the row address buffer circuit.

A pair of complementary data lines DL and word lines WL
A memory cell (storage element) M that stores 1 [bit] of information is arranged at the intersection with and. The memory cell M is composed of a series circuit of a memory cell selection n-channel MISFET Qs and an information storage capacitive element C.

MISF for selecting memory cell of memory cell M
ETQs connects one semiconductor region to one of complementary data lines DL. The other semiconductor region is connected to one electrode of the information storage capacitive element C. The gate electrode is connected to the word line WL. The other electrode of the information storage capacitive element C is connected to a constant potential of 1/2 Vcc. The constant potential 1/2 Vcc is the reference voltage Vss and the power supply voltage Vc.
The intermediate potential with respect to c is, for example, about 2.5 [V]. Constant potential 1
/ 2Vcc can reduce the strength of the electric field applied between the electrodes of the information storage capacitive element C and can reduce the deterioration of the dielectric strength of the dielectric film.

The sense amplifier circuit 13 is configured to amplify the information of the memory cell M transmitted by the complementary data line DL. The information amplified by the sense amplifier circuit 13 is an n-channel MISFET for column switch.
It is output to the common data line I / O and the inverted I / O through Qy. The column switch MISFET Qy is controlled by a column address decoder circuit (YDEC) 12.

The common data line I / O is connected to the main amplifier circuit (MAP) 1620. The main amplifier circuit 1620 is connected to the output signal external terminal (Dout) BP through the switch MISFET (not denoted by reference numeral), the output signal line DOL, the inversion DOL, and the data output buffer circuit (DoB) 1604. . That is, the information of the memory cell M further amplified by the main amplifier circuit 1620 is DRAM through the output signal line DOL, the data output buffer circuit 1604, and the external terminal BP.
1 is output to the outside.

Next, the specific structure of the elements constituting the memory cell M and the peripheral circuits (sense amplifier circuit, decoder circuit, etc.) of the DRAM 1 will be described. The planar structure of the memory cell array 11 is shown in FIG. 5 (plan view of relevant parts). The sectional structure of the memory cell array 11 and the sectional structure of the elements of the peripheral circuit are shown in FIG. 1 (main part sectional view). The cross-sectional structure of the memory cell M shown on the left side of FIG. 1 is the cross-sectional structure taken along the line I-I of FIG. The right side of FIG. 1 shows a cross-sectional structure of a CMOS that constitutes a peripheral circuit.
As shown in FIGS. 1 and 5, the DRAM 1 is composed of a p − type semiconductor substrate 20 made of single crystal silicon. The semiconductor substrate 20 uses the (100) crystal plane as an element formation surface and is formed with a resistance value of, for example, about 10 [Ω-cm].

N-channel MISF of the semiconductor substrate 20
A p − type well region 22 is provided on the main surface of each ETQn forming region. An n − type well region 21 is provided in the main surface portion of the formation region of the p channel MISFET Qp of the semiconductor substrate 20. That is, the DRA of this embodiment
M1 has a twin well structure.

An insulating film (field insulating film) 23 for element isolation is provided on the main surface between the semiconductor element forming regions of the well regions 21 and 22. p- type well region 2
In the main surface of No. 2, p is formed under the insulating film 23 for element isolation.
A mold channel stopper area 24A is provided. Parasitic MOS using inter-element isolation insulating film 23 as gate insulating film
Since it is easy to invert the n-type, the channel stopper region 24A is provided at least in the main surface portion of the p- type well region 22.

In the memory cell formation region of the memory cell array 11, a p-type semiconductor region 24B is provided on the main surface of the p-- type well region 22. p-type semiconductor region 2
4B is provided on substantially the entire surface of the memory array 11. The p-type semiconductor region 24B is formed by the same manufacturing process and the same manufacturing mask as the p-type channel stopper region 24A, and is formed by lateral diffusion of p-type impurities (B) forming the p-type channel stopper region 24A. There is. That is, due to the lateral diffusion of the p-type impurity, the p-type semiconductor region 24B is formed substantially on the entire surface of the memory cell M. This p semiconductor region 24B is p
- impurity concentration than the semiconductor substrate 20 is formed at a higher impurity concentration than the higher p- type well region 22. The p-type semiconductor region 24B is a MIS for memory cell selection.
The threshold voltage of the FET Qs can be increased, and the charge storage amount of the information storage capacitive element C can be increased. The p-type semiconductor region 24B also acts as a potential barrier region for minority carriers generated inside the semiconductor substrate due to the penetration of α rays.

MISF for selecting memory cell of memory cell M
The ETQs are formed on the main surface of the p − type well region 22 (actually, p type semiconductor region 24B) as shown in FIGS. MISFETQs for selecting memorial cells
Is formed in a region defined by the element isolation insulating film 23 and the p-type channel stopper region 24A. The MISFETQs for memory cell selection are mainly p- type well regions 2
2, a gate insulating film 25, a gate electrode 26, and a pair of n-type semiconductor regions 28 which are source regions or drain regions.

The p-- type well region 22 is used as a channel forming region. The gate insulating film 25 is formed by oxidizing the main surface of the p-- type well region 22 for 15 to 20 [n.
Gate electrode 2 formed of a silicon oxide film having a thickness of m]
6 is provided on the gate insulating film 25. The gate electrode 26 is formed of, for example, a polycrystalline silicon film deposited by the CVD method and has a film thickness of about 200 [nm]. This polycrystalline silicon film is introduced with an n-type impurity (P or As) that reduces the resistance value. In addition, the gate electrode 26
Is a high melting point (Mo, Ti, Ta, W) film or a high melting point metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WS).
i ₂ ) It may be composed of a single layer of film. Also, the gate electrode 2
6 may be composed of a composite film in which the refractory metal film or refractory silicide film is laminated on the polycrystalline silicon film.

As shown in FIG. 5, the gate electrode 26 is formed integrally with the word line (WL) 26 extending in the row direction. That is, the gate electrode 26 and the word line 26 are formed of the same conductive layer. The word line 26 is a memory cell selection M for a plurality of memory cells M arranged in the row direction.
The gate electrodes 26 of the ISFETs Qs are configured to be connected.

As shown in FIG. 5, the MI for memory cell selection
The gate length dimension of the gate electrode 26 of the SFET Qs is thicker than the width dimension of the word line 26. For example,
The gate electrode 26 has a gate length dimension of 1.0 [μm] and a word line width dimension of 0.6 [μm].

The n-type semiconductor region 28 has a lower impurity concentration than the n + -type semiconductor region (37) of the MISFET Qn forming the peripheral circuit. Specifically, the n-type semiconductor region 28 is formed by an ion implantation method of phosphorus with a low impurity concentration of less than 1 × 10 ¹⁴ [atoms / cm ² ].

The source and drain regions of the memory cell selecting MISFET Qs are composed of an n-type semiconductor region 28 and n + -type semiconductor regions 33A and 41 described later. That is, in the source and drain regions of the memory cell selecting MISFET Qs, there is no n + type semiconductor region 37 that is an ion-implanted layer of As existing in the source and drain regions of the MISFET forming the peripheral circuit. This is formed so that the generation of crystal defects due to the introduction of high-concentration impurities can be reduced and the crystal defects can be sufficiently recovered by the heat treatment after the introduction of the impurities. Therefore, since the n-type semiconductor region 28 has a small amount of leak current at the pn junction with the p- type well region 22, the n-type semiconductor region 28 can stably hold the electric charge as information stored in the information storage capacitive element C. You can

The n-type semiconductor region 28 is the gate electrode 2
6 is formed in self-alignment with, since the channel forming region side is composed of a low impurity concentration, LDD (L IgH
tly D oped D rain) constituting the memory cell selecting MISFETQs structure.

Further, the memory cell selecting MISFET
The n-type semiconductor region 28 on one side (connection side of the complementary data line) of Qs is formed integrally with the n + -type semiconductor region 41. The other n-type semiconductor region 28 (connection side of the information storage capacitive element C) is formed integrally with the n + -type semiconductor region 33A. The n + type semiconductor region 41 is a complementary data line 5
0 and one of the n-type semiconductor regions 28 is connected to the connection hole 4
It is formed in the area defined by 0A. n +
The type semiconductor region 41 is configured to prevent a short circuit between the complementary data line 50 and the p- type well region 22. The n + type semiconductor region 33A is formed in a region defined by a connection hole 32 for connecting the lower electrode layer 33 of the information storing capacitive element C having a stacked structure described later and another n type semiconductor region 28. There is. n + type semiconductor region 33A
Are formed by diffusing the n-type impurities introduced into the lower electrode layer 33.

An insulating film 27 is provided on the gate electrode 26 of the memory cell selecting MISFET Qs,
A sidewall is formed on each side wall of the gate electrode 26 and the insulating film 27.
A luspacer 29 is provided. The insulating film 27 has a thickness of about 200 nm and is mainly configured to electrically separate the gate electrode 26 and each electrode (especially 33) of the information storage capacitive element C formed thereon. ing. The side wall spacer 29 mainly constitutes a memory cell selecting MISFET Qs having an LDD structure. The insulating film 27 and the sidewall spacer 29 are respectively
C using inorganic silane gas and nitric oxide gas as source gas
It is formed of a silicon oxide film deposited by the VD method.

[0062] Saidowo - Rusupe - Sa 29, after depositing a silicon oxide film by CVD, RIE (R eactive
- by subjecting I on- the E tching), gate - is formed on the side wall of the gate electrode 26 and the insulating film 27.

Information storage capacitor C of the memory cell M
As shown in FIGS. 1 and 5, is mainly the lower electrode layer 3
3, the dielectric film 34, and the upper electrode layer 35 are sequentially laminated. The information storage capacitive element C has a so-called stacked structure (stacked type: STC).

A part (center part) of the lower layer electrode 33 of the information storing capacitive element C of the stacked structure is connected to the other n-type semiconductor region 28 of the memory cell selecting MISFET Qs. This connection is made through a connection hole 31A formed in the interlayer insulating film 31 and a connection hole 32 defined by the side wall spacer 29. The opening size of the connection hole 32 in the column direction is MISFETQs for memory cell selection.
Of the gate electrode 26 and the width of the word line 26 adjacent thereto. The difference between the opening size of the connection hole 31A and the opening size of the connection hole 32 is larger than at least the amount corresponding to the mask alignment margin in the manufacturing process. The edge portion (peripheral portion) of the lower electrode layer 33 is a gate.
The electrode 26 and the word wire 26 are extended to the respective upper portions.

The interlayer insulating film 31 is the underlying insulating film 2
7. An insulating film similar to each of the sidewall spacers 29 is formed to a film thickness of about 500 [nm]. That is,
C using inorganic silane gas and nitric oxide gas as source gas
It is formed of a silicon oxide film deposited by the VD method.

The lower electrode 33 is formed of, for example, a polycrystalline silicon film deposited by a CVD method, and an n-type impurity (As or P) for reducing the resistance value is introduced into this polycrystalline silicon film at a high concentration. ing. The lower electrode layer 33 increases the charge storage amount of the information storage capacitive element C having a stacked structure by utilizing the step shape of the base and the side wall of the connection hole 31A of the interlayer insulating film 31. The lower electrode layer 33 has a film thickness of about 100 [nm].

As described above, the interlayer insulating film 31 is formed thick and the lower electrode layer 33 is formed along the side wall of the connection hole 31A, whereby the plane area (planar lower layer electrode) of the information storage capacitive element C is formed. The size of 33) can increase the amount of accumulated charge while keeping it small.

In the information storage capacitive element C having such a structure, increasing the film thickness of the interlayer insulating film 31 leads to an increase in the capacitance value, but on the other hand, the step difference between the memory cell array region and the peripheral circuit region ( The altitude difference) becomes large.

The present invention is characterized in that the interlayer insulating film 31 is left in the peripheral circuit region without being removed. By doing so, the step difference between the memory cell array region and the peripheral circuit region can be reduced.

Further, in the information storage capacitive element C utilizing the side wall of the interlayer insulating film 31, the lower electrode layer is thickened, and the upper and lower electrode layers 35 are formed as compared with the DRAM of the type utilizing the side wall. , 33 can be made thinner. Therefore, from the connection hole 31A of the interlayer insulating film 31,
On the interlayer insulating film 31, upper and lower electrode layers 35, 33
Even with the protruding structure, the step difference between the memory cell array region and the peripheral circuit region can be reduced.

As the dielectric film 34, a silicon nitride film deposited to a thickness of 5 to 10 [nm] on the lower electrode layer 33 by the CVD method, and this silicon nitride film at a pressure of about 1.5 to 10 atm. It has a structure in which silicon oxide films having a film thickness of about 1 to 6 [nm] that are oxidized at a high pressure are stacked. The silicon oxide film may be formed by oxidizing under normal pressure.

Further, the dielectric film 34 is not limited to the laminated film of the silicon nitride film and the silicon oxide film, but may be, for example, a tantalum oxide film having a high dielectric constant.

The upper electrode 35 is provided above the lower electrode layer 33 with the dielectric film 34 interposed therebetween. The upper electrode layer 35 is formed integrally with the upper electrode layer 35 of the information storage capacitive element C of the adjacent memory cell M. A predetermined potential of 1/2 Vc is applied to the upper electrode layer 35.
c is applied. The upper electrode layer 35 is formed of a polycrystalline silicon film deposited by the CVD method, and an n-type impurity of phosphorus or arsenic is introduced into this polycrystalline silicon film in order to reduce the resistance value. The upper electrode layer 35 has a film thickness of 100 [n
m].

MISF for memory cell selection of memory cell M
One of the n-type semiconductor regions 28 of the ETQs is shown in FIGS.
A complementary data line (DL) 50 is connected as shown in FIG. The complementary data line 50 passes through the connection hole 40A formed in each of the interlayer insulating films 39 and 40 and the n-type semiconductor region 2 is formed.
8 is connected. The connection between the complementary data line 50 and the n-type semiconductor region 28 is performed with the n + -type semiconductor region 41 interposed.

The interlayer insulating film 39 is formed of, for example, a silicon oxide film having a thickness of about 200 [nm] deposited by the CVD method. The interlayer insulating film 40 is composed of a silicon oxide film (BPSG) having a film thickness of about 500 [nm] containing phosphorus and boron that can be planarized by reflow. The interlayer insulating film 39 is provided for the purpose of ensuring a dielectric strength and preventing B and P introduced into the interlayer insulating film 40 above it from leaking to an element, for example, the gate insulating film 25.

The complementary data line 50 is composed of a laminated film of a titanium nitride film 50A and a tungsten film 50B. Of the complementary data lines 50, the lower titanium nitride film 50A is a film for preventing the tungsten film 50B and silicon in the n-type semiconductor region 28 from reacting with each other. The titanium nitride film 50A has a film thickness of 100.
[Nm], and the film thickness of the tungsten film is 500 [nm]
And

Further, instead of the combination of the titanium nitride film 50A and the tungsten film 50B, the polysilicon film 5 is used.
A laminated film of 0A and the tungsten film 50B may be used.

The complementary data line 50 is formed of the first metal wiring layer.

Further, a shunt word line (WL) 53 formed of a second metal wiring layer extends in the row direction with an interlayer insulating film 51 interposed above the complementary data line 50. Is configured to. The shunt word line 53 is electrically connected to the word line 26 integrated with the gate electrode 26 of the memory cell selecting MISFET in a predetermined region.
The shunt word line 53 can reduce the resistance value of the word line 26 and can write and read information at high speed.

The second metal wiring layer is 100 [n
m] titanium titanium film 53A, 500 [n
m] of the aluminum film 53B and 100 [nm]
And a titanium-tungsten film having a three-layer structure.

The lower titanium-tungsten film 53A is a film for improving the resistance to electromigration and for preventing the reaction between the tungsten film 50B and the aluminum film 53B.

The aluminum film 53B is an alloy film mainly containing aluminum and containing a trace amount of silicon and copper.

The upper titanium-tungsten film 53C is provided to lower the reflectance of the second metal wiring layer in the exposure process and reduce the diffraction phenomenon.

The interlayer insulating film 51 is composed of a silicon oxide film (deposited insulating film) 51 A, a silicon oxide film (coated insulating film) 5
1B and a silicon oxide film (deposited insulating film) 51C are sequentially laminated to form a composite film.

A silicon oxide film 51 under the interlayer insulating film 51.
Each of A and the upper silicon oxide film 51C is formed of a silicon oxide film deposited by a plasma CVD method. Silicon oxide film 51B of the middle layer base was coated with SOG (S pin O n G lass ) method - is formed of a silicon oxide film subjected to click process. The intermediate silicon oxide film 51B is formed for the purpose of flattening the surface of the interlayer insulating film 51. Intermediate silicon oxide film 51
B is formed such that after coating, it is baked and then the entire surface is etched so that it is embedded only in the concave portion of the stepped portion. In particular, the intermediate silicon oxide film 51B is the first
It is removed by etching so that it does not remain in the connection portion (connection hole 52) between the wiring (50) of the layer and the wiring (53) of the second layer. That is, the silicon oxide film 50B in the middle layer is formed of the wiring (50,
The intermediate silicon oxide film 58B is not exposed on the side wall of the connection hole 52 so as to reduce the corrosion of the aluminum film 53).

On the upper layer of the shunt word line 53, a passivation film 54 made of a silicon nitride film is provided. The passivation film 54 has a film thickness of about 1 [μm] by the plasma CVD method.

CM constituting the peripheral circuit of the DRAM 1
The OS is configured as shown on the right side of FIG. C
The MOS n-channel MISFET Qn has a p- type well region 22 in a region surrounded by the element isolation insulating film 23 and the p-type channel stopper region 24A.
The main surface of the. n-channel MISFET
Qn is mainly composed of the p- well region 22 and the gate insulating film 2.
5, a gate electrode 26, a pair of n-type semiconductor regions 28 which are a source region and a drain region, and a pair of n + -type semiconductor regions 37.

P − type well region 22, gate insulating film 2
5, the gate electrode 26 and the n-type semiconductor region 28,
It is constructed in the same manufacturing process as the memory cell selecting MISFET Qs and has substantially the same function. That is, the n-channel MISFET Qn has an LDD structure.

The high-impurity-concentration n + type semiconductor region 37 is configured to reduce the resistance value of each of the source region and the drain region. The n + type semiconductor region 37 is defined by the sidewall spacer 29 formed on the side wall of the gate electrode 26 in a self-aligned manner, and is self-aligned with the gate electrode 26 and the sidewall spacer 29. It is formed.

The wiring 50 to which the reference voltage Vss is applied is connected to the n + type semiconductor region 37 used as the source region through the connection hole 40A provided in the interlayer insulating films 31, 39 and 40. Interlayer insulating films 31, 39, 40 are formed in the n + type semiconductor region 37 used as the drain region.
Wiring 5 for output signal through connection hole 40A provided in
0 is connected. n + type semiconductor region 37 and wiring 50
And n + formed in the area defined by the connection hole 40A.
They are electrically connected via the type semiconductor region 41. The wiring 50 is formed of the same conductive layer as the complementary data line 50.

CMOS p-channel MISFET Qp
Is formed on the main surface of the n − type well region 21 in the region surrounded by the element isolation insulating film 23. The p-channel MISFET Qp mainly includes the n- type well region 21, the gate insulating film 25, the gate electrode 26, and the source electrode 26.
Pair of p-type semiconductor regions 3 which are a drain region and a drain region
0 and a pair of p + type semiconductor regions 38.

N − type well region 21, gate insulating film 25
Each of the gate electrode 26 and the gate electrode 26 has a memory cell selection M.
The ISFET Qs and the n-channel MISFET Qn have substantially the same functions.

The p-type semiconductor region 30 having a low impurity concentration is LD
A p-channel MISFET Qp having a D structure is constructed. Source
In the high impurity concentration p + type semiconductor region 38 used as the source region, the wiring 5 to which the power supply voltage Vcc is applied through the connection hole 40A provided in the interlayer insulating films 31, 39 and 40.
0 is connected. P used as drain region
The + type semiconductor region 38 is connected to an output signal wiring 50 formed in the same layer as the data line wiring 50 through a connection hole 40A provided in the interlayer insulating films 31, 39 and 40. The wiring 50 for the output signal is connected to the wiring 53 in the upper layer through the connection hole 52. Wiring 53
Is formed of the same conductive layer as the shunt word line 53.

As described above, the interlayer insulating film 31 provided to increase the capacitance value of the information storage capacitive element C in the memory cell array region is connected to the interlayer insulating films 31, 39 and 40 while being left in the peripheral circuit region. Since the hole 40A is opened, the processing accuracy of the connection hole 40A can be improved. Further, the wiring 5 which is the first metal wiring layer with the interlayer insulating film 31 provided to increase the capacitance value of the information storage capacitive element C in the memory cell array region left in the peripheral circuit region.
Since 0 is patterned, the wiring 50 in the memory cell array area and the wiring 50 in the peripheral circuit area can be simultaneously processed with high precision. This is because the interlayer insulating film 31 is left in the peripheral circuit region. Therefore, even in the memory cell array region and the peripheral circuit region where the step is the largest, the step under the first metal wiring layer is 1.5 μm (predetermined). This is because it can be within 0.75 μm) from the reference position of.

Here, the region having the largest step difference is the region in which the word line 26 in the memory cell array region, the interlayer insulating film 31, the upper and lower electrode layers 35 and 33 overlap, and the source or the peripheral circuit region. It is on the drain region. D of the present invention
In the RAM 1 (semiconductor memory circuit device), the semiconductor substrate 20 is provided in the memory cell array region and the peripheral circuit region.
The difference in the distance from the back surface of the
Since it can be within m, the interlayer insulating films 31, 3
The processing of the connection hole 40A provided in the wirings 9 and 40 and the processing of the wiring 50 which is the first metal wiring layer can be performed with high accuracy. Further, this can improve the degree of integration.

Further, since the step between the memory cell array region and the peripheral circuit region can be reduced during the processing of the second metal wiring layer, it is provided on the first metal wiring layer via the interlayer insulating film 51. Wiring 53 which is the second metal wiring layer
Can also be processed with high precision.

Next, a specific method for manufacturing the above-described DRAM 1 will be described with reference to FIGS. 6 to 14. First, the p- type semiconductor substrate 20 made of single crystal silicon is prepared, the p- type well region 22, the n- type well region 21 and the like are formed, and the gate electrode 26 is formed on the surface of the p- type semiconductor substrate 20.
And the interlayer insulating film 27 is formed. The processes up to this point are described in detail in Japanese Patent Application No. 1-6548.

[Semiconductor Region Forming Step] Next, as shown in FIG. 6, a low impurity concentration n-type semiconductor region 28 is formed in the n-channel MISFET Qn forming region of the memory cell array region and the peripheral circuit region. The n-type semiconductor region 28 is
Self-aligned with the gate electrode 26 by 10 ¹³ [ato
[ms / cm ² ] with an impurity concentration of about 80 to 120 [K
It is formed by implanting ions with the energy of ev].

Next, the p-channel MISF in the peripheral circuit area is formed.
A low impurity concentration p-type semiconductor region 30 is formed in the ETQp formation region.
To form. The p-type semiconductor region 30 is a gate electrode 26.
In a self-aligning manner, BF ₂ (or B) having an impurity concentration of about 10 ¹³ [atoms / cm ² ] is 60 to 100 [K
It is formed by implanting ions with energy of about ev].

Next, side wall spacers 29 are formed on the side walls of the gate electrode 26, the word line 26, and the interlayer insulating film 27 above them. The sidewall spacer 29 can be formed by depositing a silicon oxide film on the entire surface of the semiconductor substrate 20 and performing anisotropic etching such as RIE.

Next, the n-channel MFET in the peripheral circuit area
A high impurity concentration n-type semiconductor region 37 is formed in the Qn formation region. The n-type semiconductor region 37 is used as the gate electrode 26.
And the sidewall spacers 29 are self-aligned with As having an impurity concentration of about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ² ] and ion-implanted at an energy of 70 to 90 [KeV].

The n-type semiconductor region 37 is not formed at both ends of the gate electrode 26 (word line 26) of the memory cell selecting MISFET Qs in the memory cell array region. That is, ion implantation is performed with the memory cell array region covered with a mask layer such as a resist, and the n-type semiconductor region 37 is formed.
To form. This is because a crystal defect occurs on the surface of the p − type semiconductor substrate 20 in this ion implantation step, and a charge leak occurs due to the crystal defect.

Next, a p channel MIS in the peripheral circuit area is formed.
A high impurity concentration p-type semiconductor region 3 is formed in the FET Qp formation region.
8 is formed. The p-type semiconductor region 38 is self-aligned with the gate electrode 26 and the sidewall spacer 29 and has a BF concentration of about 10 ¹⁵ [atoms / cm ² ].
_{It is formed} by using ₂ and implanting ions at an energy of 60 to 90 [KeV].

[Interlayer Insulating Film Forming Step] Next, as shown in FIG. 7, on the interlayer insulating film 27 and the sidewall spacer 29.
An interlayer insulating film 31 is formed on the entire surface of the substrate including the above, and a connection hole 31A is provided in the formation region of the information storage capacitive element C.

The interlayer insulating film 31 is a silicon oxide film or a silicon nitride film formed by the CVD method, and its film thickness is about 50.
It is 0 [nm]. The interlayer insulating film 31 is used as an etching stopper layer when processing the respective electrode layers of the information storage capacitive element C having the stacked structure in the memory cell array region and the peripheral circuit region. Also, the connection hole 3
In 1A , utilizing the side surface of the interlayer insulating film 31,
It is used to increase the capacitance value of the information storage capacitive element C.

[Information Storage Capacitive Element Forming Step] Next, as shown in FIG. 8, the lower electrode layer 33 of the information storage capacitive element C is formed in the connection hole 31 A provided in the interlayer insulating film 31. The lower electrode layer 33 is formed by depositing an n-type impurity such as P on a polycrystalline silicon film deposited to a thickness of about 100 [nm] by a CVD method.
(Phosphorus) is introduced, and thereafter, it is formed by using a photolithography technique and an etching technique. Lower electrode layer 33
Are patterned so that their ends extend on the interlayer insulating film 31.

The sidewall spacer 2 is formed on one of the source / drain regions of the memory cell selecting MISFET Qs.
The n-type impurity diffuses from the lower electrode layer 33 through the connection hole 32 defined by 9 to form the n + semiconductor region 33A.

Next, as shown in FIG. 9, the dielectric film 3 is formed on the entire surface of the substrate including the lower electrode layer 33 of the information storage capacitor C.
4 is formed. The dielectric film 34 has a two-layer structure of a silicon nitride film and a silicon oxide film. The silicon nitride film is deposited by the CVD method to have a film thickness of 5 to 10 [nm]. The silicon oxide film has a surface of the silicon nitride film of 1.5 to 10 [atm], 800
It is formed with a film thickness of 1 to 6 [nm] in an oxygen atmosphere of up to 1000 [° C.]. As a result, the thickness of the silicon nitride film is 4 to 8
[Nm]. Here, the silicon oxide film may be formed in an oxidizing atmosphere at normal pressure.

Next, as shown in FIG. 10, a polycrystalline silicon film is deposited on the entire surface of the substrate. This polycrystalline silicon film is deposited to a film thickness of about 100 [nm] by the CVD method, and an n-type impurity such as p is introduced.

Next, an etching mask 67 is formed in the formation region of the information storage capacitive element C. The etching mask 67 is, for example, a photoresist film. Thereafter, using this etching mask 67, the polycrystalline silicon film forming the upper electrode layer 35 and the dielectric film 34 are sequentially etched.

[Interlayer Insulating Film Forming Step] Next, as shown in FIG. 11, interlayer insulating films 39 and 40 are sequentially laminated on the entire surface of the substrate including each element of the DRAM 1. The lower interlayer insulating film 39 is a silicon oxide film deposited to a film thickness of about 200 [nm] by the CVD method. The upper interlayer insulating film 40 is a silicon oxide film (BPSG film) containing impurities (each of P and B) deposited to a film thickness of about 500 [nm] by the CVD method. The upper interlayer insulating film 40 has a thickness of about 90 in a nitrogen gas atmosphere.
Reflow is performed at a temperature of 0 to 1000 [° C.] to flatten the surface. In addition, the lower interlayer insulating film 39
Is the MISFE which has impurities from the upper interlayer insulating film 40 below.
It prevents T from entering.

[Connecting Hole Forming Step] Next, as shown in FIG. 12, a connecting hole 40A is formed in each of the interlayer insulating films 39 and 40 by anisotropic etching.

Next, MISFETQs for memory cell selection
And in the n-channel MISFET Qn forming the peripheral circuit, the n-type semiconductor regions 28, n through the connection hole 40A.
An n + type semiconductor region 41 is formed by introducing an n type impurity into each main surface portion of the + type semiconductor region 37. This n + type semiconductor region 41 has an A of 10 ¹⁵ [atoms / cm ² ].
It is formed by implanting ions using s at an energy of 110 to 130 [KeV]. At this time, the p-channel MISFET Qp forming region is covered with, for example, a photoresist film.

Since the interlayer insulating film 31 is also present in the peripheral circuit region when the connection hole 40A is formed, a value equal to or less than the depth of focus, that is, 1. It is less than 5 [μm]. Therefore, in the exposure process for forming the connection hole 40A, the memory cell array region and the peripheral circuit region can be simultaneously placed within the depth of focus of the exposure apparatus, so that the exposure can be performed at the same time.

Further, since the step difference between the memory cell array region and the peripheral circuit region is small, the processing accuracy of the connection hole 40A in the memory cell array region and the connection hole 40A in the peripheral circuit region can be made substantially the same, so that the processing margin is large. can do.

[Wiring Forming Step] Next, as shown in FIG. 13, the n + type semiconductor regions 41, p + are formed through the connection holes 40A.
A wiring 50, which is a first metal wiring layer and is in contact with the type semiconductor region 38 and extends on the interlayer insulating film 40, is formed. The wiring 50 is used as a complementary data line (DL) 50 in the memory cell array region. Wiring 50 is TiN and W
It is composed of a laminated film of. TiN is formed to a thickness of about 100 nm by the sputtering method, and W is formed to a thickness of 5 by the sputtering method.
The thickness is about 00 [nm].

The wiring 50 is processed by using photolithography technology and etching technology.

Since the interlayer insulating film 31 is present in the peripheral circuit region, the step between the memory cell array region and the peripheral circuit region is small at the time of patterning the wiring 50. In other words, even at the largest step, 1.5 [μ
m] or less. Therefore, in the exposure process for patterning the wiring 50, the memory cell array region and the peripheral circuit region can be simultaneously placed within the depth of focus of the exposure apparatus, so that they can be exposed at the same time.

Further, since the processing precision of the wiring 50 in the memory cell array region and the peripheral circuit region can be made substantially the same, the processing margin can be increased.

Further, since the step between the memory cell array region and the peripheral circuit region is small, disconnection of the wiring 50 extending from the memory cell array region to the peripheral circuit region, for example, the data line, can be prevented.

Thereafter, as shown in FIG. 1, the interlayer insulating film 5 is formed.
The wiring 53, which is the first and second metal wiring layers, and the passivation film 54 are formed, and the semiconductor memory circuit device is completed.

(Embodiment II) This embodiment II is an example in which the capacitance value of the information storage capacitive element C of the memory cell array can be increased in the DRAM of the embodiment I as shown in FIG.

The difference between Example II and Example I is the shape of the interlayer insulating film 31 in the memory cell array region. In the embodiment I, as shown in FIG. 7, the connection hole 31A is provided only in the source or drain region of the memory cell selecting MISFET Qs to which the information storage capacitive element C is connected. On the other hand, in Example II, the memory cell selection MOSFE to which the information storage capacitor C is connected.
A ring-shaped interlayer insulating film 31 is left so as to surround the source or drain region of TQs.

The lower and upper electrode layers 33 and 35 of the information storage capacitor C are formed so as to cover both side walls of the ring-shaped interlayer insulating film 31.

As described above, in the memory cell of this embodiment, since the information storage capacitive element C is formed along both side walls of the interlayer insulating film 31, the occupied area can be reduced and a large capacity can be realized. .

Even in the memory cell having such a structure, the same effect as in the case of the embodiment I can be obtained by leaving the interlayer insulating film 31 in the peripheral circuit region.

Materials of the respective layers of the DRAM 1 of the present Example II,
The film thickness and the like and the manufacturing method are the same as in Example I.

Embodiments I and II are examples of the type of memory cell in which the side wall of the interlayer insulating film 31 is used to increase the capacitance value of the information storage capacitive element C.

In addition to the stacked structure memory cell, there is a memory cell of a type in which the lower electrode layer 33 is extended to the sky to increase the capacitance value.

Next, an example in which the present invention is applied to a memory cell of the type in which the lower electrode layer 33 is extended to the sky to increase the capacitance value will be described.

Example III DRA of this Example III
As shown in FIG. 15, in the M memory cell, the interlayer insulating film 31 is thinner and the lower electrode layer 33 is thicker than the memory cell of the embodiment I. Further, only in the peripheral circuit region, an interlayer insulating film 55 that alleviates a step between the memory cell array region and the peripheral circuit region is provided.

In the case of a memory cell of the type in which the lower electrode layer 33 is extended to the sky to increase the capacitance value, the interlayer insulating film 31
Leaving the memory cell in the peripheral circuit region does not directly reduce the step between the memory cell array region and the peripheral circuit region.

Therefore, the interlayer insulating film 55 for relaxing the step is provided only in the peripheral circuit region. The interlayer insulating film 55 has a film thickness corresponding to the sum of the thicknesses of the lower layer 33 of the information storage capacitor C, the dielectric film 34, and the upper electrode layer 35.

Next, in the DRAM 1 shown in FIG.
Parts of the embodiment I different from those in FIG. 1 will be described.

In Example III, the interlayer insulating film 31
Has a film thickness of 100 [nm], and the lower electrode layer 33 has a film thickness of 500
[Nm], and the interlayer insulating film 55 has a film thickness of 500 [nm].

The interlayer insulating film 55 is the interlayer insulating film 3
It may be between 9 and 40 or above them. That is, the interlayer insulating film 55 may be below the wiring 50 which is the first metal wiring layer.

Next, a method of manufacturing the DRAM 1 of the present embodiment III will be described with reference to FIGS.

[Semiconductor Region Forming Step] As shown in FIG. 16, a low impurity concentration n-type semiconductor region 28 is formed in the n-channel MISFET Qn forming region of the memory cell array region and the peripheral circuit region. Further, a low impurity concentration p-type semiconductor region 30 is formed in the p-channel MISFET Qp formation region of the peripheral circuit region.

This step corresponds to FIG. 6 of Example I, and the method of forming the n, p type semiconductor regions 28 and 30 is the same as that described in Example I.

In Example III, at this stage, the n + type semiconductor region 37 and the p + type semiconductor region 38 in the peripheral circuit region are not formed.

[Interlayer Insulating Film Forming Step] Next, as shown in FIG. 17, an interlayer insulating film 31 is formed in the same manner as in FIG. 7 of the embodiment I. The forming method is as described in Example I, but the film thickness is 100 [nm]. [Information Storage Capacitance Element Forming Step] Next, as shown in FIGS. 18 and 19, the lower electrode layer 33, the dielectric film 34, and the upper pole layer 35 of the information storage capacity element C are sequentially formed.

The manufacturing method is as described in Example I, except that the film thickness of the lower electrode layer 33 is different.
The film thickness is 500 [nm]. In the description of FIG. 10 of Example I, the polycrystalline silicon film forming the upper electrode layer 35 and the dielectric film 34 are sequentially etched using the etching mask 67, but in this example, the interlayer insulating film 3 is further used.
1 is also etched.

[Semiconductor Region Forming Step] Next, n + and p + semiconductor regions are formed in the n and p channel MISFEQn and Qp forming regions in the peripheral circuit region. The manufacturing method is Example I.
Is as described in FIG. [Interlayer insulating film forming step] Next, as shown in FIG. 20, the interlayer insulating film 55 is formed only in the peripheral circuit region. This interlayer insulating film 55 is CV
It is silicon oxide or silicon nitride formed by the D method, and its film thickness is approximately equal to the total thickness of the lower layer of the information storage capacitor C, the dielectric film, and the upper electrode layer. In this embodiment, it is 600 [nm].

As described above, the interlayer insulating film 5 is formed in the peripheral circuit region.
By providing 5, the step difference between the memorial array area and the peripheral circuit area can be reduced.

After that, as shown in FIG. 15, the interlayer insulating film 3 is formed.
9, 40, a wiring 50 which is a first metal wiring layer, an interlayer insulating film 51, a wiring 53 which is a second metal wiring layer, and a passivation film 54 are sequentially formed, and the DRAM 1 of this embodiment is formed.
Is completed. In the third embodiment, the interlayer insulating film 55 may be between the interlayer insulating films 39 and 40 or after them.

Further, the interlayer insulating film 55 may be formed before the lower electrode layer 33 of the information storage capacitive element C is formed, and in that case, the formation of the interlayer insulating film 31 is unnecessary.

The formation of the n + type semiconductor region 37 and the p + type semiconductor region 38 must be performed before the formation of the interlayer insulating films 39, 40 and 55.

In Examples I to III, the level difference between the memory cell array region and the peripheral circuit region means that the first metal wiring layer, which is a wiring layer above the information storage capacitor C, is not formed, that is, the interlayer insulating film 40. It means the step after the formation.

The peripheral circuit region means a region other than the memory cell array region and includes a bonding pad BP forming region as well as the direct peripheral circuit and the indirect peripheral circuit.

The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a microcomputer incorporating a DRAM, an SRAM or the like.

[0152]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described.

(1) The degree of integration of the semiconductor memory circuit device can be improved.

(2) The manufacturing yield of the semiconductor memory circuit device can be improved.

(3) The electrical reliability of the semiconductor memory circuit device can be improved.

(4) The manufacturing process of the semiconductor memory circuit device can be shortened.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional plan view of a resin-encapsulated semiconductor device encapsulating the DRAM.

FIG. 3 is a chip layout diagram of the DRAM.

FIG. 4 is an equivalent circuit diagram of a main part of the DRAM.

FIG. 5 is a plan view of an essential part of the DRAM.

FIG. 6 is a cross-sectional view showing each manufacturing process of the DRAM.

FIG. 7 is a cross-sectional view showing each manufacturing process of the DRAM.

FIG. 8 is a cross-sectional view showing each manufacturing process of the DRAM.

FIG. 9 is a cross-sectional view showing each manufacturing process of the DRAM.

FIG. 10 is a cross-sectional view showing each manufacturing process of the DRAM.

FIG. 11 is a cross-sectional view showing each manufacturing process of the DRAM.

FIG. 12 is a cross-sectional view showing each manufacturing process of the DRAM.

FIG. 13 is a cross-sectional view showing each manufacturing process of the DRAM.

FIG. 14 is a cross-sectional view of essential parts of a DRAM of Example II of the present invention.

FIG. 15 is a cross-sectional view of essential parts of a DRAM according to Example III of the present invention.

FIG. 16 is a cross-sectional view showing each manufacturing process of the DRAM of Example III.

FIG. 17 is a cross-sectional view showing each manufacturing process of the DRAM of Example III.

FIG. 18 is a cross-sectional view showing each manufacturing process of the DRAM of Example III.

FIG. 19 is a cross-sectional view showing each manufacturing step of the DRAM of Example III.

FIG. 20 is a cross-sectional view showing each manufacturing process of the DRAM of the example III.

[Explanation of symbols]

1 ... DRAM, M ... Memory cell, C ... Information storage capacitor element, Qs ... Memory cell selection MISFET, Qn, Qp
... It is a MISFET.

─────────────────────────────────────────────────── ─── Continued Front Page (72) Hiroyuki Miyazawa, 5-20-1 Mizumizuhoncho, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Atsushi Ogishima 5-chome, Mizumizumoto-cho, Kodaira, Tokyo 20-1 Hitachi Ltd. Musashi Plant (72) Inventor Masaki Nagao 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi Ltd. Musashi Plant (72) Inventor Keiichiro Asayama Kodaira, Tokyo 5-20-1 Jousuihonmachi Hitachi Co., Ltd. Musashi Plant (72) Inventor Hiroyuki Uchiyama 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Musashi Plant (72) Inventor Yoshiyuki Kaneko 882 Ichimo, Katsuta-shi, Ibaraki Hitachi Measurement Engineering Co., Ltd. (72) Inventor Kozo Watanabe 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Company Hitachi Ltd. Musashi Plant (72) Inventor Kazuya Endo 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Hiroki Soeda 882 Ichige, Katsuta, Ibaraki Hitachi Measurement Engineering Co., Ltd. (56 ) References JP-A-64-80061 (JP, A) JP-A-3-120864 (JP, A) JP-A-4-134859 (JP, A) JP-A-4-196482 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (21)

(57) [Claims] 1. A semiconductor substrate having: (a) a main surface and a back surface, a first area on which a memory cell array is located and a second area on which a peripheral circuit is located; A first MISFET located in the first region and comprising a gate electrode, a source and a drain region; and (c) a second MISFET located in the second region and comprising a gate electrode, a source and a drain region. A MISFET, (d) a first insulating film located on the respective gate electrodes of the first and second MISFETs, and (e) an electrical connection to one of the source and drain regions of the first MISFET. Connected to the first MI
A gate electrode of the SFET and a first capacitor electrode extending on the first insulating film; (f) a second capacitor electrode located on the first capacitor electrode via a dielectric film; g) a second insulating film located on the second capacitor electrode in the first region and on the first insulating film in the second region, and (h) the second insulating film in the first region. On the second insulating film,
And a first wiring located on the gate electrode of the first MISFET, and a second wiring located on the second insulating film in the second region and on the gate electrode of the second MISFET. A semiconductor memory circuit comprising a first wiring and a second wiring in the same layer, and having a third insulating film between the first and second insulating films in the second region. apparatus. 2. The semiconductor according to claim 1, wherein the thickness of the third insulating film is substantially equal to the total thickness of the first and second capacitance electrodes and the dielectric film between them. Memory circuit device. 3. (a) It has a main surface and a back surface, and memos are provided on the main surface.
The first area where the re-cell array is located and the peripheral circuits are located
And (b) a gate electrode, a source and a source region located in the first region.
And a drain region, and (c) a gate electrode, a source and a source located in the second region.
And a drain region, and (d) is located on the gate electrode of the first MISFET.
A first insulating film, and (e) the source and drain of the first MISFET.
The first MI electrically connected to one of the regions
Extending over the gate electrode of the SFET and the first insulating film
A first capacitance electrode, and (f) positioned on the first capacitance electrode via a dielectric film
A second capacitive electrode, and (g) the first capacitive electrode formed on the second region.
The total thickness of the pole, the dielectric film and the second capacitance electrode.
Approximately equal second insulating film, a third insulating film located on said second insulating film (g) said on said second capacitor electrode of the first region and the second region, ( h) on the third insulating film in the first region,
And located on the gate electrode of the first MISFET
On the first wiring and the third insulating film in the second region,
And on the gate electrode of the second MISFET
Consisting of said first wiring located and second wiring in the same layer
A semiconductor memory circuit device characterized by the above. 4. The semiconductor memory circuit device according to claim 1, wherein the third insulating film is a silicon dioxide film. 5. A semiconductor substrate having: (a) a main surface and a back surface, a first area in which a memory cell array is located, and a second area in which peripheral circuits are located; A first MISFET located in the first region and comprising a gate electrode, a source and a drain region; and (c) a second MISFET located in the second region and comprising a gate electrode, a source and a drain region. A MISFET, (d) a first insulating film located on the respective gate electrodes of the first and second MISFETs, and a second insulating film located on the first insulating film, (e) the Electrically connected to one of the source and drain regions of the first MISFET,
A gate electrode of the SFET and a first capacitor electrode extending on the second insulating film; (f) a second capacitor electrode located on the first capacitor electrode via a dielectric film; g) a third insulating film located on the second capacitor electrode in the first region and on the second insulating film in the second region, and (h) the third insulating film in the first region. On the third insulating film,
And a first wiring located on the gate electrode of the first MISFET, the first wiring located on the third insulating film in the second region, and located on the gate electrode of the second MISFET. A semiconductor memory circuit device comprising: a first wiring and a second wiring in the same layer. 6. The semiconductor memory circuit device according to claim 5, wherein the first and second capacitance electrodes extend to a side portion of the second insulating film in the first region. 7. The semiconductor memory circuit device according to claim 6, wherein the first and second capacitance electrodes extend to a side portion and an upper portion of the second insulating film in the first region. . 8. The semiconductor memory circuit device according to claim 1, wherein the first and second wirings are made of a refractory metal layer. 9. The semiconductor memory circuit device according to claim 8, wherein said first and second wirings are made of a silicon material which is a refractory metal. 10. The semiconductor memory circuit device according to claim 1, wherein the first wiring forms a data line. 11. The first wiring is the first MISF.
11. The semiconductor memory circuit device according to claim 10, being connected to the other of the source and drain regions of ET. 12. The semiconductor memory circuit device according to claim 1, wherein the difference between the maximum values of the distance from the back surface of the semiconductor substrate to the first and second wirings is 1.5 μm or less. 13. A semiconductor substrate having (a) a main surface and a back surface and having first and second regions on the main surface, and (b) a source or drain region located in the first region. A first MISFET having a first insulating film on the gate electrode and a plurality of memory cells connected to either the source or drain region of the first MISFET to form the lower electrode of the capacitor And (c) a peripheral region composed of a plurality of second MISFETs having source and drain regions and having a first insulating film on the gate electrode, the memory cell array being arranged in a matrix. A circuit, and (d) the second MISFET in the second region.
A second wiring that is located on the second insulating film on the first insulating film on the gate electrode and is connected to the source or drain region of the MISFET; and (e) the same as the second wiring. The first MISFET in layers
A first wiring located in the first region on the second insulating film on the first insulating film on the gate electrode of the semiconductor substrate from the back surface of the semiconductor substrate to the first and second wirings. A semiconductor memory circuit device, wherein the difference in distance is 1.5 μm or less. 14. A memory cell array in which memory cells each comprising a first MISFET and an information storage capacitive element connected in series are arranged in a matrix, and a plurality of second MISFETs.
In a method of manufacturing a semiconductor memory circuit device having a peripheral circuit constituted by (a), (a) a first gate electrode of a first MISFET and a first gate electrode of a first MISFET in a first region Second M
Forming a second gate electrode of ISFET; Forming a semiconductor substrate region, and (c) forming a sidewall insulating film on the ends of the first and second gate electrodes, and forming a first insulating film on top of the first and second gate electrodes. And (d) forming a second conductive type second semiconductor region in a self-aligned manner with respect to the first insulating film on the second gate electrode and the sidewall insulating film, e) a step of forming a second insulating film on the first and second regions on the semiconductor substrate, and (f) the second region for exposing one of the source and drain regions of the first MISFET. Forming a first opening in the insulating film, and (g) the first MI through the first opening. FE
Forming a first capacitance electrode of the information storage capacitance element so as to contact one of the source and drain regions of T; and (h) forming the first capacitance electrode of the information storage capacitance element on the first capacitance electrode. Forming a dielectric film and a second capacitor electrode; and (i) forming a third insulating film on the second insulating film in the first region and the second region of the semiconductor substrate. And (j) a step of forming a wiring layer on the third insulating film in the first and second regions, the method for manufacturing a semiconductor memory circuit device. 15. A memory cell array in which memory cells each comprising a first MISFET and an information storage capacitive element connected in series are arranged in a matrix, and a plurality of second MISFETs.
In a method of manufacturing a semiconductor memory circuit device having a peripheral circuit configured in (a), (a) a first gate electrode of a first MISFET and a first gate electrode of a first MISFET in a first and second regions on a semiconductor substrate of a first conductivity type, respectively. Forming a first insulating film on the first gate electrode, a second gate electrode of the second MISFET and a first insulating film on the second gate electrode, and (b) the first and the second Forming a second conductivity type first semiconductor region in the second region in a self-aligned manner with respect to the first and second gate electrodes; and (c) forming the first and second gate electrodes. A step of forming a sidewall insulating film at an end portion, and (d) a step of forming a first capacitance electrode of the information storage capacitance element so as to contact one of a source region and a drain region of the first MISFET, (E) a dielectric film of the information storage capacitive element on the first capacitive electrode; Forming a second capacitor electrode, (f) forming a second insulating film on the first region and the second region of the semiconductor substrate, and (g) forming the first and second regions. A step of forming a wiring layer on the second insulating film in the region, and (h) a second semiconductor region of the second conductivity type in a self-aligned manner with respect to the second gate electrode and the sidewall insulating film. And (i) forming a third insulating film only in the second region, wherein the step (h) is prior to the steps (i) and (f). The step (i) is between the step (c) and the step (g), the method for manufacturing a semiconductor memory circuit device. 16. A memory cell selection MI on the main surface of a semiconductor substrate.
In a semiconductor integrated circuit device having a memory cell array configured by arranging a plurality of memory cells each comprising a series circuit of an SFET and a stacked information storage capacitive element, and a plurality of MISFETs provided around the memory cell array, The memory cell selection MISFET and the plurality of MISFETs are covered with a first interlayer insulating film on the gate electrode, and the first insulating film is covered with a second interlayer insulating film to store information in the memory cell. Each of the capacitance elements for use has one electrode of the capacitance element formed along the inner wall of the connection hole provided in the second interlayer insulating film, and a part of the other electrode of the capacitance element forms the dielectric film. Is formed so as to cover the one electrode via the second interlayer insulating film covering the plurality of MISFETs and a third interlayer insulating film is formed on the other electrode of the capacitive element,
The memory cell selecting MISF is formed on the third insulating film.
A semiconductor integrated circuit device, wherein a wiring layer is formed over the ET and the plurality of MISFETs. 17. A memory cell array region in which a plurality of memory cells are arranged on a main surface of a semiconductor substrate, and each of the plurality of memory cells is a stacked electrode including a first electrode, a dielectric film and a second electrode. A semiconductor integrated circuit device comprising: an information storage capacitive element having a structure; and a memory cell selection MISFET connected in series, and having a peripheral circuit region in which a plurality of MISFETs are arranged in addition to the memory cell array region. A second interlayer insulating film so as to cover the first insulating film on the gate electrode of the memory cell selecting MISFET in the memory cell array region and the first insulating film on the gate electrodes of the plurality of MISFETs in the peripheral circuit region. And a connection hole for forming an information storage capacitive element in each memory cell is provided in the second interlayer insulating film in the memory cell array region, and the inner wall of the connection hole is formed. Along with the stacked information storage capacitor, a third interlayer insulating film is provided in the memory cell array region so as to cover the information storage capacitor, and a third interlayer insulating film is provided in the peripheral circuit region. A semiconductor integrated circuit device comprising a conductor layer provided on a third interlayer insulating film on the second interlayer insulating film. 18. The first electrode is for selecting the memory cell.
18. The semiconductor integrated circuit according to claim 17 , wherein the second electrode is electrically connected to one of a source region and a drain region of the MISFET, and the second electrode is given an intermediate potential between a reference voltage and a power supply voltage. apparatus. 19. The semiconductor integrated circuit device according to claim 17 , wherein the dielectric film has a structure in which a silicon nitride film and a silicon oxide film are laminated. 20. The semiconductor integrated circuit device according to claim 17 , wherein the dielectric film is a tantalum oxide film. 21. A main surface of a semiconductor substrate has a memory cell array region forming a DRAM and a peripheral circuit region, and the memory cell array region has a first MISFET and a gate electrode of the first MISFET. A first interlayer insulating film,
A second interlayer insulating film is provided on the first interlayer insulating film, and a lower electrode of the information storage capacitive element is arranged in the second interlayer insulating film provided on the main surface of the memory cell array region. The second MISFET is connected to one of the source and drain regions of the first MISFET, and the peripheral circuit region includes the second MISFET, the first interlayer insulating film on the gate electrode of the second MISFET, and the first MISFET. A second interlayer insulating film is provided on the interlayer insulating film, a third interlayer insulating film is provided on the second interlayer insulating film in the memory cell array region and the peripheral circuit region, and in the memory cell array region. A wiring connected to the other of the source and drain regions of the first MISFET is formed on the third insulating film, and the second M in the main peripheral circuit region.
A semiconductor integrated circuit device having a built-in DRAM, wherein a wiring connected to one of a source region and a drain region of an ISFET is formed on the third insulating film.