JP2866390B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 The present invention relates to a semiconductor technology, and particularly to a DRAM (Dynamic
Semiconductor integrated circuit device having random access memory)
Technology that is effective when applied to
You. [Prior Art] Memory cells that store 1-bit information of DRAM
Series circuit of MISFET for recell selection and capacitive element for information storage
It is composed of The memory cell selection MISFFT gate
The gate electrode is connected to a word line extending in the row direction.
One semiconductor region of the memory cell selection MISFFT is complementary
Data line. The other semiconductor area contains the information
It is connected to one electrode of the storage capacitor. Information storage
A predetermined potential is applied to the other electrode of the storage capacitor.
You. This type of DRAM is integrated for large capacity,
The size of cells tends to be reduced. Memory cell support
When the size is reduced, the size of the information storage
Since the size is reduced, the amount of charge stored as information decreases. Electric
The decrease in the amount of accumulated load decreases the α-ray soft error withstand voltage,
In addition, large-capacity DRAM of 1 [Mbit] or more is resistant to α ray soft error
Increasing pressure is one of the important technical issues. Based on these technical issues, DRAM memory cells
Stacked structure (STC structure) is adopted for the information storage capacitor
Tend to be used. For information storage of this stacked structure
Capacitors consist of a lower electrode layer, a dielectric film, and an upper electrode layer, respectively.
Are sequentially laminated. The lower electrode layer is
Part is connected to the other semiconductor region of the MISFET for
Another region is extended to above the gate electrode. Underlayer
The electrode layer is formed by photolithography on a polycrystalline silicon film deposited by CVD.
Performs graphic technology and etching technology to achieve a predetermined planar shape
Is patterned. The dielectric film
Provided along the upper surface and side surfaces of the lower electrode layer
You. An upper electrode layer is provided on a surface of the dielectric film.
You. The upper electrode layer is a stack of other adjacent memory cells
Integrated with the upper electrode layer of the capacitor for information storage
And used as a common plate electrode. Upper layer electricity
The pole layer is formed of a polycrystalline silicon film as in the case of the lower electrode layer.
ing. It should be noted that the information storage capacitor of the stacked structure
For the DRAM constituting the cell, see, for example, Japanese Patent Application No. 62-235906.
No. [Problem to be Solved by the Invention] The inventor is developing a DRAM having a large capacity of 4 [Mbit].
Have found the following problems. The DRAM being developed by the inventor is a folded bit
The line system (two-intersection system) is adopted. This kind of DR
AM is an inverted pattern alternately in the direction in which the complementary data lines extend.
Memory cells are arranged in The memory cell stack
The lower electrode layer of the stacked information storage capacitor is planar
The shape is rectangular. The size of adjacent memory cells
Lower electrode layer spacing of tack-structured information storage capacitor
Is complementary to one semiconductor region of the memory cell selection MISFT.
The connection area with the data line is large,
Is defined. That is, in the connection area,
Extra space between the electrode layers in the manufacturing process with the upper electrode layer, connection holes, etc.
Because extra dimensions and dimensions for insulation separation are added
The gap is large. On the other hand, the lower layer
The interlayer is processed to the minimum processing size or a size close to it.
Space is small. For this reason, in the manufacturing process,
Processing the lower electrode layer using photolithography technology
Diffraction phenomenon during the exposure process to form an etching mask
The connection region side of the etching mask is particularly excessive due to
Exposed. Furthermore, the reflected light from the step of the gate electrode layer
Thus, the connection region side is excessively exposed. In other words, before
Processed (etched) using the etching mask
Lower electrode layer is considerably smaller than designed size
The size of the stacked information storage capacitor
The charge storage amount decreases. This decrease in charge accumulation is due to
Deteriorates soft error withstand voltage and induces malfunction of DRAM
In addition, it is necessary to increase the size of the information storage capacitor.
Therefore, the degree of integration of the DRAM is reduced. The objects of the present invention are as follows. (1) In a semiconductor integrated circuit device having a storage function
To provide technologies that can improve the degree of integration
It is in. (2) In the semiconductor harvesting circuit device, a soft error
ー To provide technology that can improve withstand voltage
You. The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.
Would. [Means for Solving the Problems] Among the inventions disclosed in the present application, representative ones
The brief description is as follows. (1) Information on MISFET for memory cell selection and stacked structure
A memory cell is composed of a series circuit with an information storage capacitor
In a semiconductor integrated circuit device having a DRAM, the DRAM
Under the information storage capacitor with the stacked structure of memory cells
A correction pattern that increases the surface area is formed on the electrode layer.
To achieve. [Operation] According to the above-mentioned means (1), the adjacent lower electrode layer
In the area with a large space (data line side),
Diffraction phenomena during exposure of lithography technology
An etching mask for processing the lower electrode layer by irradiation of light.
It is possible to reduce the reduction of the disk size (
Is compensated by the reduction in size), so the lower electrode layer
Capacitance element for information storage with a stacked structure that secures surface area
It is possible to increase the amount of charge stored in the child. As a result, α
Line soft error voltage is improved and memory cell area is reduced.
Therefore, the degree of integration of the DRAM can be improved. Hereinafter, the configuration of the present invention will be described with respect to the memory cell selecting MISF.
Series circuit of ET and stacked information storage capacitor
Application of the present invention to a DRAM that constitutes a memory cell in the embodiment
This is explained with an example. In all the drawings for explaining the embodiments, the same device
Those having functions are given the same reference numerals, and the description of the repetition is given.
Is omitted. [Embodiment of the Invention] (Embodiment I) A resin-sealed mold half for encapsulating a DRAM which is Embodiment I of the present invention.
The conductor device is shown in FIG. 2 (partial sectional plan view). As shown in FIG. 2, the DRAM (semiconductor pellet) 1 has a SO
J (Small Out-line J-bend) type resin-encapsulated semiconductor device
2. DRAM1 is a resin-encapsulated semiconductor device
2 on the surface of the tab 3A with an adhesive
You. The DRAM 1 has a large capacity of 4 [Mbit]. This D
RAM1 is sealed in a 350 [mil] resin-sealed semiconductor device 2.
ing. The main surface of DRAM 1 stores 1 [bit] of information.
Memory with multiple memory cells (storage elements) arranged in rows and columns
A cell array is arranged. Other than memory cell array
In the main surface of DRAM1, direct peripheral circuits and indirect peripheral circuits
Road is located. Peripheral circuits directly store information about memory cells.
This circuit directly controls the information write operation and the information read operation.
Row address decoder circuit, column address decoder
And a sense amplifier circuit and the like. Indirect peripheral circuit
Is a circuit that indirectly controls the operation of the direct peripheral circuit.
Yes, includes clock signal generation circuit, buffer circuit, etc.
You. In the most peripheral part of the DRAM1, the short side of the DRAM1, the long side
External terminals (bonding pads)
C) BPs are arranged. This external terminal BP is connected with the bonding wire 4
Connected to inner lead 3B. Bonding Y
The wire 4 uses aluminum (Al) wire. Also,
Gold (Au) wire, copper (C)
u) Insulating resin coated on the surface of wire and metal wire
A covered wire or the like may be used. Bonding wire 4
Is based on a bonding method that uses ultrasonic vibration in combination with thermocompression bonding.
Bonded. The inner lead 3B is integrated with the outer lead 3C.
Has been established. This inner lead 3B, outer lead
3C, each of the tabs 3A is cut from the lead frame
Is molded. Lead frame is, for example, Cu, Fe-Ni
(For example, a Ni content of 42 [%]).
The tab 3A has a tab hanging on each of the short side and the long side.
Lead 3D is connected. The outer leads 3C are individually
The signals applied are defined and numbered. Same
2 In the figure, the upper left corner is terminal 1; the lower left corner is terminal 10; the lower right corner
Is the 11th terminal, and the upper right end is the 20th terminal. This outer
For the signal applied to the mode 3C, the external terminal BP
This will be described later. The DRAM1, the tab 3A, the bonding wire 4, the inner
-Lead 3B and tab suspension lead 3D are sealed with resin sealing part 5.
Have been. The resin sealing portion 5 is used to reduce the stress.
Adds phenolic curing agent, silicone rubber and filler
The added epoxy resin is used. Silicone goose
Has the effect of lowering the coefficient of thermal expansion of the epoxy resin.
You. The filler is formed of spherical silicon oxide particles.
In this way, it has the effect of lowering the coefficient of thermal expansion. Next, the DRAM encapsulated in the resin-encapsulated semiconductor device 1
FIG. 3 (chip layout diagram) shows a schematic configuration of 1. As shown in FIG. 3, the center of the DRAM 1
A memory cell array (MA) 11 is provided. Of this embodiment
The DRAM 1 includes, but is not limited to, a memory cell array 11
Is roughly divided into four memory cell arrays 11A,
Configuration is adopted. That is, in FIG.
The two memory cell arrays 11A are arranged on the upper side of the
Are provided with two memory cell arrays 11A. this
Each of the four divided memory cell arrays 11A further includes
It is subdivided into four memory cell arrays 11B. Toes
DRAM1 has 16 memory cell arrays 11B arranged.
You. One memory cell array 11B divided into 16 pieces is 2
It has a capacity of 56 [Kbit]. Two memory cell arrays of the 16 subdivided
Column address decoder circuits (YDE
C) 12 and part of the sense amplifier circuit (SA) 13
ing. The sense amplifier circuit 13 is a complementary type MISFFT (CMOS).
And a part of the sense amplifier circuit 13 is an n-channel MISF
Consists of ET. The other part of the sense amplifier circuit 13.
The p-channel MISFET has a
It is arranged at the end of the memory cell array 11B. Sensea
From one end of the amplifier circuit 13, complementary data lines (two data lines)
Line extends over the memory cell array 11B,
The DRAM1 of the embodiment uses a folded bit line method (two
Point method). Each of the memory cell array 11B subdivided into 16 pieces
Row address decoder circuit (XDEC)
14 and a word driver circuit (WD) 15 are provided. Circuits 12 arranged around these memory cell arrays 11
16 are configured as direct peripheral circuits of the DRAM1. The upper side peripheral circuit 16 on the upper side of the DRAM 1 and the lower side on the lower side
A peripheral circuit 17 is provided. Located above DRAM1
Two memory cell arrays 11A and two
Peripheral circuit 18 is arranged between the memory cell array 11A
Is placed. In addition, two of the two
Two memos arranged on the lower side between the memory cell arrays 11A
A central peripheral circuit 19 is arranged between each of the recell arrays 11A.
Have been. These peripheral circuits 16-19 are indirect peripheral of DRAM1
It is configured as a circuit. Next, the specific functions and functions of the external terminal BP of the DRAM 1 described above will be described.
Regarding the specific circuit arrangement of the indirect peripheral circuit and
This will be briefly described with reference to a drawing (an enlarged layout diagram of a main part). First, of the external terminals BP arranged around the DRAM1,
₀~ A₉Is an external terminal BP for an address signal. I / O₁~ I / O
_FourIs an external terminal BP for input / output signals. RAS is row address
External terminals BP and CAS for strobe signal are column address
External terminal BP for strobe signal. WE is light
External terminals BP and OE for enable signal are output enable.
This is an external terminal BP for a bull signal. Vss is the reference potential, for example
External terminals BP and Vcc for circuit ground potential 0 [V]
For example, an external terminal BP for the operating potential 5 [V] of the circuit.
You. Although not shown, especially near the external terminal BP for input signals
Is equipped with an input protection circuit (electrostatic destruction prevention circuit)
I have. Each circuit of the upper peripheral circuit 16 of the indirect peripheral circuit is a basic circuit.
Basically, it is placed near the external terminal BP to which each signal is applied.
Have been. 1601 is a light circuit, 1602 is a RAS control
Circuit. 1603 is the substrate potential V_BBGenerating circuit,
For example, a circuit for generating a potential of -2.5 to 3.5 [V].
1604 is the data output buffer circuit, 1605 is the input / output data circuit
Reference numeral 1606 denotes a data output control circuit. 1607 is
CAS control circuit, 1608 read / write control
Roll circuit, 1609 is test mode control circuit, 16
10 is a main amplifier control circuit. 1611 is IO
Rect circuit, 1612 is mat selection and common source drive circuit
Road. 1614 is the bonding master control circuit, 1616 is
ATD circuit, 1617 is X address buffer circuit, 1619 is Y address
It is a dress buffer circuit. 1620 is the main amplifier circuit,
1621 is a nibble counter circuit, and 1622 is a test logic circuit.
You. In the middle side peripheral circuit 18, 1801 is a Y address buffer.
The circuit, 1802 is an ATD circuit, and 1803 is a mat selection circuit. 1
804 is an X-system predecoder circuit, 1805 is an X-system redundant circuit, 180
6 is a refresh counter circuit, 1807 is a column equalizer
Circuit. 1808 is a decoder monitor circuit, 1809 is X
Address buffer circuit, 1810 common I / O equalization system
Control circuit, 1812 is an X address latch circuit, 1813 is a refresh
Control circuit. In the lower peripheral circuit 17, 1701 is a mat selection circuit and
A common source drive circuit 1702 is a Y predecoder circuit.
You. 1703 is an X address buffer circuit, 1704 is a Y address
It is a buffer circuit. 1705 is ATD circuit, 1706 is Y system redundant
The circuit 1707 is an X predecoder circuit. Next, the subdivided memory cell array 11B of the DRAM 1
Fig. 5 (Main parts)
This will be described using an equivalent circuit diagram). As shown in FIG. 5, the folded bit line
DRAM1 adopting the formula is in memory cell array (MA) 11B
The complementary data lines DL and ▲ ▼ in the column direction.
You. A plurality of sets of the complementary data lines DL are arranged in the row direction.
I have. Complementary data line DL is connected to sense amplifier circuit (SA) 13
It is connected. In the memory cell array 11B, the word lines WL
It extends in the row direction crossing the complementary data line DL. Wa
A plurality of the word lines WL are arranged in the column direction. Illustrated
No, but each word line WL is a row address buffer circuit
(XDFC) connected to 14 and configured to be selected
You. At the intersection of each of the complementary data lines DL and the word line WL
Memory cell (storage element) M for storing 1 [bit] information
Is arranged. The memory cell M is a memory cell selecting n
Series circuit of channel MISFETQs and information storage capacitor C
It is composed of MISFETQs for memory cell selection of memory cell M is one half
The conductor region is connected to the complementary data line DL. The other half
The conductor region is connected to one electrode of the information storage capacitance element C.
Have been. The gate electrode is connected to a word line WL.
The other electrode of the information storage capacitor C is set to the power supply voltage of 1/2 Vcc.
It is connected. The power supply voltage 1 / 2Vcc is equal to the reference voltage Vss.
An intermediate potential with respect to the power supply voltage Vcc, for example, about 2.5 [V]. Electric
A source voltage of 1/2 Vcc is applied between the electrodes of the information storage capacitance element C.
Electric field strength and dielectric breakdown voltage of dielectric film
can do. The sense amplifier circuit 13 is transmitted on the complementary data line DL.
Configured to amplify the information of the memory cell M reached
ing. The information amplified by the sense amplifier circuit 13
Common data line through n-channel MISFFTQy for switch
Output to I / O and ▲ ▼ respectively. Column switch
MISFETQy for column address decoder circuit (YDFC) 12
Controlled. The common data line I / O is connected to the main amplifier circuit (MAP) 16
Connected to 20. Main amplifier circuit 1620 is a switch
MISFET (no symbol), output signal line DOL, ▲
▼, through each of the data output buffer circuits (DoB) 1604
And connected to the output signal external terminal (Dout) BP.
In other words, the memo further amplified by the main amplifier circuit 1620
Information of recell M is output signal line DOL, data output buffer
The circuit 1604 is output to the outside of DRAM1 through each of the external terminals BP.
Is forced. Next, the memory cell M of the DRAM 1 and a peripheral circuit (sensor)
Elements that make up the amplifier and decoder circuits)
A typical structure will be described. Memory cell array 11B
The surface structure is shown in FIG. 6 (plan view of a main part). Memory cell array
B. The cross-sectional structure of 11B and the cross-sectional structure of
FIG. The menu shown on the left side of FIG.
The cross-sectional structure of the molycell M was taken along the line II in FIG.
3 shows a cross-sectional structure of a portion. The right side of FIG.
3 shows a cross-sectional structure of a CMOS constituting a side circuit. As shown in FIGS. 1 and 6, DRAM 1 is made of single crystal silicon.
Consisting of p^-It is composed of a mold semiconductor substrate 20. Semiconductor base
Plate 20 uses (100) crystal plane as the element formation surface, and
For example, it is formed with a resistance value of about 10 [Ω-cm]. Semiconduct
A part of the main surface of the body substrate 20 is approximately 0% by ion implantation.¹⁵[Ato
ms / cm^Two] The above impurities have not been introduced. Part of
The region is at least the region of the memory cell array 11B.
You. The introduction of the impurities causes a large amount of crystal defects,
Introduce impurities because they cause the charge to leak
Are partially restricted. Therefore, to reduce contamination by heavy metals such as Na
Next, the DRAM 1 of this embodiment is obtained in a deep region of the semiconductor substrate 20.
Those having a tarling layer are used. Getterin
The semiconductor layer is located at a depth of about 10 μm from the main surface of the semiconductor substrate 20.
Region (a region deeper than each of the well regions 21 and 22).
Have been. The memory cell M (memory cell array) of the semiconductor substrate 20
11) In the main surface of each forming region of n-channel MISFETQn
Is p^-A mold well region 22 is provided. Semiconductor substrate 20
n is formed on the main surface of the p-channel MISFET Qp formation region.^-Type well
An area 21 is provided. That is, the DRAM 1 of this embodiment is
It has a twin-well structure. The main portion between the respective semiconductor element formation regions of the well regions 21 and 22
On the surface, insulating film for field isolation (field insulating film) 23
Is provided. p^-In the main surface portion of the mold well region 22,
A p-type channel stopper region is formed under the insulating film 23 for element isolation.
24A is provided. Gate insulating film 23 for element isolation
Since the parasitic MOS used as the insulating film is likely to be n-type inverted, the channel
The stopper area 24A is at least p^-Main surface of mold well region 22
Section. In the formation area of the memory cell M of the memory cell array 11
And p^-A p-type semiconductor region 24B
Is provided. The p-type semiconductor region 24B is substantially a memo
It is provided on the entire surface of the recell array 11. p-type semiconductor area
The region 24B is manufactured in the same manner as the P-type channel stopper region 24A.
Process, formed with the same manufacturing mask, p-type channel stop
Lateral diffusion of p-type impurity (B) forming aperture region 24A
Is formed. N-channel that constitutes peripheral circuit
Compared to MISFFTQn, MI for selecting memory cell of memory cell M
The gate width dimension of the SFETQs is configured to be small. Toes
The lateral diffusion of the p-type impurity causes the memory cell
The p-type semiconductor region 24B is formed on substantially the entire surface of M.
It has become so. This p-type semiconductor region 24B has p^-Mold half
P with a higher impurity concentration than the conductor substrate 20^-Mold well area 22
It is formed with an even higher impurity concentration. p-type half
The conductor region 24B is the threshold of the MISFETQs for memory cell selection.
Voltage can be increased, and the voltage of the information storage capacitive element C can be increased.
The load accumulation amount can be increased. Also, a p-type semiconductor region
24B is a potential barrier region for minority carriers
It still works. MISFETQs for selecting a memory cell of the memory cell M is shown in FIG.
6 and 7 (planes of essential parts in predetermined manufacturing process)
P) as shown in the figure)^-Well region 22 (actually p-type semiconductor)
It is formed on the main surface of the body region 24B). Memory cell selection
MISFETQs for selection is insulating film 23 for isolation between elements and P-type channel
It is configured within the area defined by the stopper area 24A.
You. MISFFTQs for memory cell selection is mainly p^-Mold well area 2
2, gate insulating film 25, gate electrode 26, source region or gate
It is composed of a pair of n-type semiconductor regions 28 that are rain regions.
I have. The p^-Mold well region 22 is used as a channel formation region
Have been. Gate insulating film 25 is p^-Main surface of mold well region 22
Formed of a silicon oxide film formed by oxidizing silicon. Gate electrode 26 is provided on gate insulating film 6.
You. The gate electrode 26 is, for example, a polycrystalline film deposited by a CVD method.
It is formed with a silicon film and has a thickness of about 200 to 300 [nm].
ing. This polycrystalline silicon film is an n-type impurity that reduces the resistance value.
(P or As) is introduced. Also, the gate electrode 26
Are high melting point metal (Mo, Ti, Ta, W)
(MoSi_Two, TiSi_Two, TaSi_Two, WSi_Two) Consisting of a single layer of membrane
Is also good. The gate electrode 26 is formed on the polycrystalline silicon film.
Composite of high melting point metal film and high melting point metal silicide film
It may be composed of a film. The gate electrode 26 is, as shown in FIGS.
It is integrated with the word line (WL) 26 extending in the direction
You. That is, each of the gate electrode 26 and the word line 26 has the same conductivity.
It is formed of an electric layer. Word lines 26 are arranged in the row direction.
Of MISFETQs for selecting memory cells of a plurality of memory cells M
It is configured to connect the respective gate electrodes 26. As shown in FIG. 7, the gate of the MISFETQs for memory cell selection is used.
The gate length of the gate electrode 26 is larger than the width of the word line 26.
It is thick and thick. For example, the gate of the gate electrode 26
The long dimension is 1.0 [μm] and the width of the word line is 0.6
[Μm]. Note that the DRAM 1 of the present embodiment
Except for the inter-wire dimension of the word line 26 of 0.6 [μm],
So-called 0.8 [μm] production with a minimum processing dimension of 0.8 [μm]
Employs a process. As shown in FIGS. 6 and 7, the memory cell M is complementary.
Between one data line DL of the sex data line (50) and the word line 26
A first intersection, the other data line of the complementary data line
▼ and another word adjacent to the word line 26 in the column direction
It is located at each of the second intersections with line 26. The husband
Each word line 26 has substantially the same width and a predetermined isolation size.
It is extended in the row direction in parallel while being held. This 2
The word lines 26 correspond to the respective data lines D of the complementary data lines.
L, each data line ▲ ▼ project in the opposite direction
As described above, they extend in the row direction in a zigzag manner. The first
At the intersection, word line 26 is
A protruding portion 26A is provided on the lead line 26 side along the shape of the memory cell M.
Have been killed. Similarly, at the second intersection, the other wires
On the word line 26 side of the memory cell line M along the shape of the memory cell M.
Accordingly, a protruding portion 26A is provided. This projection 26A is actually
Qualitatively as the gate electrode 26 of MISFETQs for memory cell selection
Used, the gate length is longer than the width of the word line 26
The law is being lengthened. Moreover, the protrusion 26A
Is an insulating film for element isolation defining the periphery of the memory cell M
23 and at least a margin in the manufacturing process
Just superimpose to the extent that the memory cell M
Along the shape (the gate width of MISFETQs for memory cell selection)
(To the same extent as the law). That is, as shown in FIG.
The MISFET Qs for memory cell selection
Word line when the width of the word line 26 is purely specified
Compared with the separation dimension A between 26, on the insulating film 23 for element isolation,
Words can be sufficiently secured.
The interval between the memory cells M in the extending direction of the line 26 can be reduced.
Wear. Thus, (claim 24-means 14) for selecting a memory cell
Formed by a series circuit of MISFETQs and capacitive element C for information storage
Folded bit line to place the memory cell M
In the in-type DRAM 1, one of the complementary data lines (50)
A first intersection between the first data line DL and the first word line 26,
The other of the complementary data lines and the second data line
Another second word line adjacent to the first word line 26 in the column direction.
26, the memory cell M is arranged at each of the second intersections with 26,
Each of the first word line 26 and the second word line 26 is substantially
Going in parallel with the same width and the specified separation
And the first data line DL and the second data line
Project in the opposite direction for each of the ▲ ▼
The first word line 26 and the second word line 26 are zigzag
Extending the second word line of the first word line 26 at the first intersection.
Line 26 is projected along the shape of the memory cell M (projection
And the second word line 2 at the second intersection.
6 projecting along the first word line 26 side along the shape of the memory cell M.
Let out. With this configuration, the first word line 26 and its
Of the memory cell selection MIS at the first intersection.
As the gate electrode 26 of the FFTQs, the second word line 26 and its
The protruding portion 26A has a MISFE for selecting a memory cell at the second intersection.
Each is used as a gate electrode 26 of TQs,
To secure the gate length of MISFETQs for memory cell selection
Can reduce short-channel effects.
And at each of the first intersection and the second intersection
Memory cell M intervals can be reduced. this
As a result, the area occupied by the memory cell M is reduced, and
The area occupied by the separation region between the lines M can be reduced.
Thus, the degree of integration of the DRAM 1 can be improved. The n-type semiconductor region 28 is a MISFET constituting a peripheral circuit.
Qn n⁺At least information storage compared to the
The side connecting the storage capacitor C is formed with a low impurity concentration.
I have. Specifically, the n-type semiconductor region 28 is 1 × 10¹⁴[Atoms /
cm^Two] With low impurity concentration ion implantation method
I have. That is, the n-type semiconductor region 28 is caused by the introduction of impurities.
To reduce the occurrence of crystal defects caused by
Shape so that crystal defects can be sufficiently recovered by heat treatment
Has been established. Therefore, the n-type semiconductor region 28^-Type
Low leakage current at pn junction with well region 22
Therefore, the information is stored in the information storage capacitor C.
Charges can be stably held. The n-type semiconductor region 28 is self-
It is formed by matching, and the channel formation region side has a low impurity concentration
LDD (Lightly Doped Drain) structure
MISFETQs for selecting a memory cell. One of the MISFETQs for memory cell selection (complementary
The n-type semiconductor region 28 on the data line connection side) is n⁺Semiconductor area
It is configured integrally with 41. The other (capacitive element for information storage
The n-type semiconductor region 28 on the (connection side of C) is n⁺Type semiconductor region 33A
And is configured integrally. Said n⁺Type semiconductor region 41 is complementary
Connection between the conductive data line (50) and one n-type semiconductor region 28
Formed in the area defined by the connection hole 40A
I have. n⁺Type semiconductor region 41 is connected to complementary data line (50) and p^-Type
It is configured to prevent a short circuit with the well region 22.
You. Said n⁺The semiconductor region 33A has a stacked structure described later.
The lower electrode layer (33) and the other n
Area defined by the connection hole 32 for connection to the die semiconductor region 28.
It is formed in the region. n⁺Type semiconductor region 33A
The n-type impurity introduced into the lower electrode layer 33 is diffused.
Are formed. Upper layer of the gate electrode 26 of the MISFETQs for memory cell selection
Is provided with an insulating film 27, and the gate electrode 26 and the insulating film 27
Side wall spacers 29 are provided on each side wall.
You. The insulating film 27 is mainly formed on the gate electrode 26, on which
Each electrode (especially 33) of the information storage capacitor C is electrically
It is constituted so that it may separate. Sidewalls
Pacer 29 mainly uses MISFETQs for selecting memory cells with LDD structure.
Configuration. The insulating film 27, side wall
Each of the spacer spacers 29 will be described later in a manufacturing method thereof.
The inorganic silane gas and nitric oxide gas
Formed of a silicon oxide film deposited by CVD method
You. This silicon oxide film uses an organic silane gas as a source gas.
Compared to silicon oxide film deposited by CVD method
High step coverage and small film shrinkage
No. Thus, the (10-6) MISFETQs for memory cell selection
An insulating film 27 is formed on the gate electrode 26, and the gate electrode 26
Side wall and the side wall of the insulating film 27 thereover.
In the DRAM 1 forming the spacer 29, the gate electrode 2
Each of the insulating film 26 and the sidewall spacer 29 on
CV using inorganic silane gas and nitric oxide gas as source gas
It is composed of a silicon oxide film deposited by the D method. With this configuration
The insulating film 27 on the gate electrode 26,
The silicon oxide film of each of the pacers 29 is sourced from organic lanthanum
Shrinkage of film compared to silicon oxide film deposited by CVD method using gas
Only the insulating film 27 and the side
The separation between the wall spacer 29 and the gate is reduced.
Between the electrode 26 and another conductive layer (for example, the lower electrode layer 33).
Prevents electrical leakage and improves electrical reliability.
As well as the insulating film 27 on the gate electrode 26,
Step spacers of the silicon oxide film
High coverage enables high uniformity of silicon oxide film thickness
Therefore, the withstand voltage can be improved. Also step
High coverage required to get the same sidewall thickness
Layer thickness can be reduced, the step can be reduced, and the lower layer
Processing of the pole layer 33 becomes easy. The information storage capacitance element C of the memory cell M is a first element.
FIGS. 6, 6 and 8 (plans of main parts in a predetermined manufacturing process).
As shown in the plan view), mainly the lower electrode layer 33, the dielectric film 3
4, each of the upper electrode layers 35 is sequentially laminated.
You. The information storage capacitor C has a so-called stacked structure (laminated structure).
Type: STC). The lower layer capacitor of the information storage capacitor C having the stacked structure
A part (central part) of the pole layer 33 is MISFETQs for memory cell selection.
Is connected to the other n-type semiconductor region 28. This connection
Are connection holes 31A formed in the interlayer insulating film 31 and side walls.
Through the connection hole 32 defined by the
I have. Select the memory cell for the opening size of the connection hole 32 in the column direction.
MISFETQs gate electrode 26, word line 26 adjacent to it
Are defined by the respective separation dimensions. Opening of connection hole 31A
The difference between the size and the opening size of the connection hole 32 is at least
Larger than the mask alignment margin in the process
It's getting worse. The other part (peripheral part) of the lower electrode layer 33 is
The electrode 26 and the word line 26
I have. The interlayer insulating film 31 is formed by a lower insulating film 27 and a side wall.
Formed of the same insulating film as each of the metal spacers 29.
You. In other words, the source of inorganic silane gas and nitric oxide gas
Formed of a silicon oxide film deposited by a CVD method using a gas
You. The lower electrode layer 33 is made of, for example, polycrystalline silicon deposited by a CVD method.
It is formed of an elemental film, and the resistance of this polycrystalline silicon film is reduced.
An n-type impurity (As or P) is introduced at a high concentration. under
The layer electrode layer 33 utilizes the step shape of the base and uses the side wall.
To store the charge in the stacked information storage capacitor C
To increase the volume, for example, a ratio of about 200 to 400 [nm]
It is formed with a relatively thick film thickness. The planar shape of the lower electrode layer 33 is shown in FIG. 6 and FIG.
As shown, in the column direction where the complementary data lines (50) extend
It has a long rectangular shape. As shown in FIG.
Each lower electrode layer 33 arranged in the row direction in which the lead line 26 extends
Is the processing dimension at or near the minimum added dimension in the manufacturing process
Formed by law. Similarly, the complementary data line (50)
Of the lower electrode layers 33 arranged in the extending column direction,
Instead of the complementary data line connection side,
The minimum additional dimension between the lower electrode layers 33 to be interposed is
It is formed with a processing size close to. In contrast, the complement
On the connection side of the conductive data line, between the lower electrode layers 33,
MISFET Qs for recell selection and n-type semiconductor region 28 and complementary data
Connection area with data line (50), upper electrode layer 35 and complementary data
Withstand voltage between the wire (50) and the lower electrode layer 33 and the upper electrode layer 35
And the lower electrode layer 33 and the complementary data line (50)
Are separated by an amount equivalent to the
You. The lower electrode layer 33 is in phase with the n-type semiconductor region 28.
It is formed in a planar square shape on the connection side with the complementary data line (50).
Correction pattern 33A that protrudes in the planar direction from the
Have been. Etching mask for processing lower electrode layer 33
(Photoresist film) in the connection region
Diffraction phenomena and word lines that occur in the region with a large gap between the polar layers
The size is reduced by the reflected light from 26 steps.
U. Therefore, the size of the lower electrode layer 33 is smaller than a predetermined set value.
Information storage capacity in a stacked structure
The charge storage amount of the element C decreases. Therefore, the correction pattern
33A is the lower electrode layer 33
Is configured to increase the size. Correction pattern
In the layout, there is a margin between the lower electrode layers 33 in the layout.
It is arranged on the connection side, but is not limited to this.
It may be arranged on the opposite side to the above-mentioned position. The lower layer of reality
In the planar shape of the electrode layer 33, the corners of the square shape drop considerably
, So as to have a roundness as a whole. Thus, (1-1) MISFETQs for memory cell selection and
A series circuit with a stacked information storage capacitor C
In the DRAM 1 forming the memory cell, the stacked
The surface of the lower electrode layer 33 of the information storage capacitor C having the structure
A correction pattern 33A for increasing the product is formed. to this
The region where the space between adjacent lower electrode layers 33 is large (complementary
Exposure of photolithography technology
Due to the diffraction phenomenon at the time of light and the reflected light from the word line 26,
The size of the etching mask for processing the lower electrode layer 33
Can be reduced (the size is reduced in advance).
The surface area of the lower electrode layer 33
Secure and charge of the stacked information storage capacitor C
The amount of accumulation can be increased. As a result, alpha ray software
The error withstand voltage can be improved and the area of the memory cell M can be reduced.
Thus, the degree of integration of the DRAM 1 can be improved. The dielectric film 34 basically has a lower electrode layer (polycrystalline silicon).
Silicon nitride deposited on the upper layer (on the surface) of film 33 by CVD
Film 34A, silicon oxide film obtained by oxidizing silicon nitride film 34A at high pressure
It has a two-layer structure in which 34B are laminated. actually,
The dielectric film 34 is formed on the surface of the polycrystalline silicon film as the lower electrode layer 33.
Natural silicon oxide film (very thin, less than 3 [nm])
(Not shown in the figure) is formed.
Three layers in which a silicon oxide film 34A and a silicon oxide film 34B are sequentially laminated
It has a structure. The silicon nitride film 34 of the dielectric film 34
Since A is deposited by the CVD method, the underlying polycrystalline silicon film
Regardless of the crystal state and step shape of the layer electrode layer 33).
Can be formed under independent process conditions.
That is, the silicon nitride film 34A oxidizes the surface of the polycrystalline silicon film.
Compared to a silicon oxide film formed by
Leakage current is very low because the number of defects per unit area is small.
Few. Moreover, the silicon nitride film 34A is compared with the silicon oxide film.
It has the characteristic of high dielectric constant. Silicon oxide film 34B is very good
The silicon nitride film 34 can be formed of a high quality film.
The characteristics of A can be further improved. Also,
As described later in detail, the silicon oxide film 34B is formed by high-pressure oxidation (1.5 to 10
[Atmospheric pressure]), so the acid is shorter than normal pressure oxidation.
Formation time, that is, heat treatment time. Oxidation
The silicon film 34B is thin (for example, 2 nm or less) and has a normal pressure (1
(Atmospheric pressure))
When it is within the range, it can also be formed by normal pressure oxidation. The dielectric film 34 extends along the upper surface and side walls of the lower electrode layer 33.
And is formed by utilizing the side wall of the lower electrode layer 33.
Earn area in the direction. The increase in the area of the dielectric film 34
The amount of charge stored in the stacked information storage capacitor C is
Can be improved. The planar shape of this dielectric film 34 is
The upper electrode layer is defined by the planar shape of the upper electrode layer 35 and substantially
It has the same shape as 35. The upper electrode layer 35 is provided with a lower electrode with a dielectric film 34 interposed therebetween.
It is provided on the layer 33 so as to cover it. Upper electrode
The layer 35 includes information on the stacked structure of another adjacent memory cell M.
The information storage capacitor C is formed integrally with the upper electrode layer 35.
I have. A power supply voltage of 1/2 Vcc is applied to the upper electrode layer 35.
You. The upper electrode layer 35 is, for example, polycrystalline silicon deposited by a CVD method.
The polycrystalline silicon film is formed of a film and has a reduced resistance value.
An n-type impurity has been introduced. The upper electrode layer 35 is, for example,
It is formed with a thickness equal to or less than the lower electrode layer 33.
You. Thus, the (11-7) interlayer insulating film (base insulating film) 31
A lower electrode layer 33 formed thereon, on the interlayer insulating film 31 and
The dielectric film 34 formed on the surface of the lower electrode
A switch composed of an upper electrode layer 35 formed on a dielectric film 34
DRAM1 having a capacitive element C for storing information with a tacked structure
Of the information storage capacitor C having the stacked structure.
The dielectric film 34 is composed of a composite film having a silicon nitride film 34A,
The interlayer insulating film 31 is coated with an inorganic silane gas and a nitrogen oxide gas.
It is composed of a silicon oxide film deposited by CVD as a source gas.
You. With this configuration, the stacked structure information storage
Shrinkage of the interlayer insulating film 31 with respect to the dielectric film 34 of the capacitive element C
Only between the dielectric film 34 and the interlayer insulating film 31.
Since the generated stress can be reduced, the dielectric film
34 between the lower electrode layer 33 and the upper electrode layer 35.
Leakage current and improve electrical reliability.
As well as step coverage of the interlayer insulating film 31
High uniformity of the film thickness of the interlayer insulating film 31,
The lower electrode layer 33 on the insulating film 31 and the conductive layer thereunder (for example,
To increase the dielectric strength between the gate electrode 26 and the word line 26).
Can be. The memory cell M is shown in FIG. 1, FIG. 6, FIG.
One other memory cell adjacent in the column direction as shown in the figure
M is connected. That is, two adjacent columns in the column direction
The memory cell M is one of the respective memory cell selecting MISFFTQs.
The other n-type semiconductor region 28 is integrally formed, and the portion is centered.
And a reverse pattern. These two memory cells
The memory cells M are arranged in the row direction.
The other two memory cells M adjacent to each other in the direction
They are displaced by one-half pitch. One n of MISFETQs for memory cell selection of memory cell M
The type semiconductor region 28 is complementary as shown in FIGS.
The sex data line (DL) 50 is connected. Complementary data line
Reference numeral 50 denotes a connection hole 40 formed in each of the interlayer insulating films 36, 39, and 40.
A is connected to the n-type semiconductor region 28 through A. Complementarity
The connection between the data line 50 and the n-type semiconductor region 28 is n⁺Type semiconductor
This is performed with the region 41 interposed. Each of the interlayer insulating films 36 and 39 is deposited by, for example, a CVD method.
It is formed of a silicon oxide film. Interlayer insulation film 40 flows
Oxide containing phosphorus and boron that can be planarized by sputtering
It is composed of a membrane (BPSG). The interlayer insulating film 39 is
Introduced into the inter-layer insulation film 40 to secure the edge withstand voltage and the upper layer
Provided to prevent the leakage of B or P into the device.
Have been. The complementary data line 50 is formed of a transition metal film (barrier metal film).
Film) 50A, aluminum film or aluminum alloy film 50B,
Transition metal film (protective film) 50C each three layers laminated sequentially
It is composed of The lower transition metal film 50A of the complementary data lines 50
Means that the aluminum film 50B and the n-type semiconductor region 28 (actually n
⁺Single-crystal silicon precipitates at the connection with the type semiconductor region 41),
It is configured to prevent the resistance of the connection from increasing.
Have been. That is, the lower transition metal film 50A is a so-called barrier
Used as a metal film. This lower transition metal film
50A is formed before the upper aluminum film 50B is formed.
The melting temperature of the aluminum film 50B.
It is possible to use a CVD method at a temperature close to or higher than
it can. Specifically, the lower transition metal film 50A is deposited by the CVD method.
WSi_TwoUse a membrane. The lower transition metal film 50A is
For example, TaSi_TwoFilm or TiN film (that is,
The transition metal film of the embodiment is a transition metal film, a transition metal silicide film and
Transition metal nitride film). Transition of lower layer deposited by CVD method
The transfer metal film 50A is a portion having a large step shape of the base, particularly,
Step coverage at the connection of the complementary data lines 50
It can be greatly improved. The lower transition metal film
50A has low resistance when deposited by low temperature sputtering.
For the purpose of reducing and stabilizing, a high temperature of about 900 [° C]
Heat treatment must be applied. Lower transition metal film 50A
Represents p in the n-type semiconductor region 28 and the peripheral circuit region.⁺Mold semiconductive
Connected to the body region (38) and formed on the interlayer insulating film 40
Therefore, the heat treatment at a high temperature causes mutual expansion of impurities.
This causes dispersion and increases the resistance value at each connection portion.
Also from this point, the lower transition metal film 50A has a low resistance.
CV not less than 650 ° C and not more than 900 ° C that does not require heat treatment
It is desirable to form by D method. The middle aluminum film 50B of the complementary data line 50
Is basically used as the main part of the wiring and has a low resistance value.
It is formed of a material. The aluminum film 50B
When using an alloy film of Cu, Cu, Cu and
Add Si. Cu reduces migration phenomena
For example, about 0.5% by weight
I have. Si is added to reduce alloy spike phenomenon
For example, about 1 to 1.5 [% by weight] is added.
The aluminum film 50B is deposited by, for example, a sputtering method.
You. The upper transition metal film 50C of the complementary data line 50 is mainly
Aluminum hillrock phenomenon deposited on the surface of the minium film 50B
It is formed for the purpose of reducing. Also, the upper transition gold
The metal film 50C sets the reflectance of the surface of the complementary data line 50 to aluminum.
Compared with the case of the surface of the
Diffraction phenomenon at the time of exposing the etching mask that processes the data line 50
And the reflected light from the step of the adjacent ground
The size of the mask is reduced.
Is configured. The upper transition metal film 50C is
Unlike the transfer metal film 50A, after forming the aluminum film 50B
The aluminum film 50B is not melted.
It is deposited by temperature sputtering. Upper transition metal film
50C substantially reduces the resistance of the complementary data line 50
It is not necessary to use high-temperature heat after deposition by sputtering.
No processing is required. The upper transition metal film 50C is made of MoS
i_TwoIt is formed of a film. The upper transition metal film 50C is
Other transition metal films such as WSi_Two, TaSi_Two, TiSi_TwoWith membrane etc.
It may be formed. As described above, (3-2) the base surface having the step shape
(40) DRAM with complementary data line (wiring) 50 extending on it
In 1, the complementary data lines 50 were deposited by a CVD method.
Transition metal film 50A, aluminum film deposited by sputtering
(Or its alloy film) A composite film in which each of 50B is sequentially laminated
Constitute. With this configuration, the aluminum film 50B
The resistance value is small, and the signal transmission speed of the complementary data line 50 is increased.
Information writing operation speed, information reading speed
It is possible to increase the speed of the feeding operation, and
The transition metal film 50A has a step coverage at the step portion of the base.
To reduce disconnection failure of the complementary data line 50
Therefore, electrical reliability can be improved.
Further, the lower transition metal film 50A of the complementary data line 50 is
Precipitation of Si at the junction with Si such as n-type semiconductor region 28
Elephants can be prevented. (4-3) The complementary data line 50 is formed by a CVD method.
Transition metal film 50A deposited, aluminum deposited by sputtering
Of the transition metal film 50C deposited by the sputtering method
Each is composed of a composite film having a three-layer structure in which layers are sequentially laminated. This structure
As a result, the upper transition metal film 50 of the complementary data line 50 is formed.
C can prevent the occurrence of aluminum hill rock
Wear. Also, the transition metal film 50C on the upper layer of the complementary data line 50
Reduces the reflectance of the surface of the aluminum film 50B or its alloy film.
Etching mask to reduce and process complementary data lines 50
Diffraction Phenomenon During Exposure During Forming
Excessive light exposure can be reduced,
The processing accuracy of the complementary data line 50 can be improved. Ma
The upper transition metal film 50C of the complementary data line 50 is
At a lower temperature than the melting point of the lower aluminum film 50B
The aluminum film 50B is melted because it can be deposited
I will not let you. The complementary data line 50 is the first layer in the manufacturing process.
It is formed by a wiring forming step. This complementarity data
The line 50 is used to reduce the step shape peculiar to the multilayer wiring structure.
The wiring forming process of the second layer in the manufacturing process of the upper layer
Formed with a smaller thickness than the wiring (53)
ing. The DRAM 1 of this embodiment has a two-layer wiring structure (two-layer wiring structure).
Aluminum wiring structure). Also, DRAM
1 is a three-layer gate wiring structure (three-layer polycrystalline silicon film structure).
Has been established. As shown in FIG. 1 and FIG.
An interlayer insulating film 51 is interposed in the upper layer of
The line (WL) 53 is configured to extend in the row direction.
You. Although not shown, the shunt word line 53 is
In a predetermined area corresponding to every 100 memory cells M,
As described above, it is connected to the word line (WL) 26. Wah
The plurality of gate lines 26 extend in the extending direction in the memory cell array 11B.
The shunt word line 53 is divided into
Are connected to each of the plurality of word lines 26. Shi
The word line 53 for shunt reduces the resistance value of the word line 26,
In each of the information writing operation and the information reading operation, the memory
The configuration is such that the selection speed of the cell M can be increased. As shown in FIG. 1, the interlayer insulating film 51 is made of silicon oxide.
Film (deposited insulating film) 51A, silicon oxide film (coated insulating film) 5
1B and silicon oxide film (deposited insulating film) 51C are sequentially laminated
It consists of a composite membrane. The lower silicon oxide film 51A of the interlayer insulating film 51 and the upper silicon oxide film
Each of the elemental films 51C is a silicon oxide film deposited by plasma CVD.
Formed. The middle silicon oxide film 51B is made of SOG (Spin On Glas
s) Formed with a silicon oxide film that has been applied and then baked
To achieve. This middle silicon oxide film 51B is the surface of the interlayer insulating film 51.
It is formed for the purpose of flattening the surface. Silicon oxide in the middle layer
The membrane 51B is applied, baked, and
Etching process and bury only in the recess at the step
It is formed as follows. In particular, the middle silicon oxide film 51B is
Connection between first layer wiring (50) and second layer wiring (53)
Etching process so that the remaining portion (connection hole 52) does not remain.
Has been removed. That is, the middle silicon oxide film 50
B is the wiring (50, 53 husband)
Each) to reduce corrosion of aluminum film
Have been. The shunt word line 53 is connected to the complementary data line 50.
Is formed with a structure similar to the cross-sectional structure of
Film 53A, aluminum film (aluminum alloy film) 53B, transition
A three-layer composite film in which each of the transfer metal films 53C is sequentially laminated.
It is configured. Transition gold under the word line 53 for shunt
Each of the metal film 53A and the upper transition metal film 53C is a lower wiring.
The complementary data lines 50 form an aluminum film 50B.
Therefore, it is deposited by a sputtering method that can be deposited at a low temperature.
You. Each of the lower transition metal film 53A and the upper transition metal film 53C
Is, for example, MoSi_TwoIt is formed of a film. Lower transition metal film 5
3A mainly reduces the resistance at the connection with the lower wiring (50)
It is formed to be. The upper transition metal film 53C is mainly
To reduce aluminum hill rock and lower the reflectance
It is formed to reduce the folding phenomenon. Wafer for shunt
As described above, the lead line 53 is a lower layer wiring, for example, complementary data.
Formed to be thicker than the thickness of wire 53, reducing resistance
It is configured to be. The connection of the word lines 26 and the shunt word lines 53
FIGS. 9 (plan view of the connection region) and FIG. 10 (FIG. 9)
(A cross-sectional view taken along the section line II-II)
It is performed through 50D. That is, the shunt
The lead wire 53 is once drawn to the intermediate conductive layer 50D through the connection hole 52.
Dropped. The connection hole 52 is formed by anisotropic etching.
Lower connection hole 52A having a substantially vertical step shape and
With a loose step shape formed by isotropic etching
It is constituted by a side connection hole 52B. That is, the connection hole 52 is
Improve step coverage of shunt word line 53,
It is configured so that disconnection failure can be reduced. And
The intermediate conductive layer 50D is provided in a direction in which the shunt word line 53 extends.
In a different direction from the connection hole 52.
The connection hole 40A is connected to the word line 26.
The intermediate conductive layer 50D is the same conductive layer as the complementary data line 50,
It is formed in the first-layer wiring forming step. This middle guide
The electrical layer 50D connects the shunt word line 53 and the word line 26.
The step shape at the time of connection is reduced,
It is configured to prevent disconnection failure. Each of the connection portions of the intermediate conductive layer 50D and the word line 26
Around the connection hole 40A, the information of the stacked structure
The upper electrode layer 35 of the storage capacitor C is the memory cell array 11
Stretched from B. Intermediate conductive layer 50D and word line 26
The connection hole 40A for connecting the upper electrode
In the region where the opening 35A formed in the layer 35 is provided
Are located. The memory cell array 11B is a memory cell array.
MISFETQs for selecting a device and a capacitor for storing information in a stacked structure
Each of the daughters C is stacked so that the step shape is larger than other areas.
The shunt word, as described above.
An upper electrode layer 35 is provided in each connection region of the line 53 and the word line 26.
It is stretched. That is, the upper electrode layer 35
Between the array 11B and each of the connection areas,
Second wiring (eg, intermediate conductive layer 50D) 50, second wiring
(For example, shunt word line 53)
Is configured to be able to be flattened. Thus, the (22-13) complementary data line 50 and the word line
A plurality of memory cells M are arranged at the intersection with
The memory array 11 and the memory above the word line 26.
Areas other than recell array 11 (actually memory cell array
11 (a predetermined area in FIG. 11) connected to the word line 26.
In the DRAM 1 in which the word line 53 for
Around the connection between the shunt line 26 and the shunt word line 53.
A difference relaxation layer (the drawn-out upper electrode layer 35) is provided. this
According to the configuration, the word line 26 and the shunt word line 53
And the memory cell array 11 (actually,
The step between the memory cell M and the memory cell M is reduced.
And shunt word lines 53 extending over the respective regions.
Processing wiring and connection holes (40A and 52) for connecting the wiring
Photolithography technology can be stabilized
Therefore, disconnection failure and conduction failure at the step portion of the wiring
The yield can be reduced, and the production yield can be improved. Further, the step relaxation layer (35) is a stack of the memory cell M.
Same as the upper electrode layer 35 of the information storage capacitance element C having a dotted structure
It is formed using a conductive layer. With this configuration, the step relaxation layer is formed.
Since it can be formed by the upper electrode layer 35, the step reduction layer
DRAM1 manufacturing steps
Can be reduced. As shown in FIGS. 9 and 10, the upper electrode
The layer 35 includes the memory cell array 11B and the shunt word.
Between each of the connection areas between the line 53 and the word line 26.
It is connected to the power supply wiring 50E to which the source voltage 1/2 Vcc is applied.
You. 6 and 11 (cut along the line III-III in FIG. 6).
(The upper layer is omitted from the wiring 50)
As shown in the figure, the edge around the memory cell array 11B is
A driving area GL is provided. Guard ring area
GL surrounds the memory cell array 11B and is mainly
Plate potential generation circuit (V_BBGenerator circuit) Released from 1603
It is configured to capture minority carriers.
The guard ring area GL is the memory cell array 11B and peripheral circuits
And is located between. Guard ring area GL
In the insulating film for isolation 23 and the p-type channel stopper region 24A
Within the defined area, p^-Main surface of mold well region 22
N-type semiconductor region 28 (and n⁺Type semiconductor region 33
A). That is, the guard ring area GL
Uses the shape of the memory cell M and repeats the memory cell M
MISF for memory cell selection so as not to disturb the return pattern
FTQs have the same dimensions as the gate width.
You. Although not shown in the guard ring area GL, power supply wiring
A power supply potential of 1/2 Vcc is applied via (50). The husband of the memory cell array 11B and the guard ring region GL
The step reduction layers (33D, 35D) are arranged between them.
The step reducing layers are arranged in two steps in this embodiment.
In other words, the step reduction layer is formed from the memory cell array 11B side.
The first step alleviation layer (33D and
35D) and the second step reduction layer (35D) are sequentially arranged.
ing. The first step reduction layer (33D and 35D) has a two-step structure.
Has been established. The lower layer of the first step relief layer (33D and 35D)
The step reduction layer 33D is a stacked information storage capacitor.
C is composed of the same conductive layer as the lower electrode layer 33, and the upper step
The relaxation layer 35D is formed of the same conductive layer as the upper electrode layer 35.
You. The second step relief layer (35D or 33D may be used)
Same as the upper electrode layer 35 of the information storage capacitor C having the locked structure.
It is composed of one conductive layer. In other words, the step reduction layer (33
D, 35D) from the memory cell array 11B to the guard ring area G
It is configured to gradually reduce the step shape toward L
I have. Thus, the (18-10) MISFFTQs for memory cell selection
Stacked information storage capacity stacked on top of it
Memory cells M, which are composed of a series circuit with an element C, are arranged in a matrix.
The memory cell array 11B in which
DRAM1 with peripheral circuits arranged in the peripheral area of array 11B
Between the memory cell array 11B and peripheral circuits.
Lower electrode layer 3 of stacked storage capacitor C for information storage
3, formed of the same conductive layer as the upper electrode layer 35 or both layers
The step reduction layers (33D, 35D) are provided. With this configuration,
Steps between the memory cell array 11B and peripheral circuits
Relaxed by the step relaxation layers (33D, 35D),
Extending wiring (complementary data line 50 or shunt word line
53) Stabilize photolithography technology for processing
Disconnection failure at the step portion of the wiring
, And the production yield can be improved. (19-11) The memory cell array 11B and the peripheral circuit
Between the road and the former,
The lower electrode layer 33 and the upper layer
The first step reduction layer (33D) formed of the same conductive layer as the pole layer 35
And 35D), the same as the lower electrode layer 33 or the upper electrode layer 35
Each of the second step reduction layers (33D and 35D) formed of conductive layers
Are sequentially arranged. With this configuration, the memory cell array
A step between the peripheral circuit and the first step reducing layer;
(33D and 35D), the second step reduction layer (33D and 35D) respectively
More production yields because it can be relaxed in stages
Can be improved. The (20-12) memory cell array 11B and peripheral circuits
A guard ring region GL is arranged between
(33D, 35D) are arranged in the guard ring area GL. This
The area occupied by the step reduction layers (33D, 35D)
All or part of the area is occupied by the guard ring area GL
Occupation of the step reduction layer (33D, 35D)
The area can be reduced and the degree of integration can be improved. The substantial part of the DRAM 1 including the upper layer of the shunt word line 53
The entire surface is passivated as shown in FIG.
A membrane 54 is provided. FIG. 1 is not shown in detail.
However, as described later, the passivation film
See figure) Silicon oxide film (54A) deposited by CVD method, plasma
Silicon nitride film (54B) deposited by CVD method, applied resin film
(For example, polyimide resin film 54C).
It is composed of a composite membrane. On the passivation film 54
The resin layer (54C) is mainly used for the memory cell array 11B,
In order to reduce the incidence of α-rays on each part of the edge circuit
Has been established. In other words, the resin film 54C has an α-ray soft error
It is configured to improve the breakdown voltage. The resin film 54
C is bonded to the external terminal BP arranged around DRAM1.
The area where the wire 4 is connected is removed.
A detailed description of this area will be described later. The CMOS which constitutes the peripheral circuit of the DRAM 1 is shown in FIG.
It is configured as shown on the right. CMOS n-channel MI
SFETQn is composed of an insulating film 23 for element isolation and a p-type channel
In the region surrounded by the wrapper region 24A, p^-Mold
It is formed on the main surface of the L region 22. n-channel MISF
ETQn is mainly^-Type well region 22, gate insulating film 25,
A pair of gate electrodes 26, a source region and a drain region.
n-type semiconductor region 28 and a pair of n⁺Type semiconductor region 37
Have been. p^-Mold well region 22, gate insulating film 25, gate electrode 26 and
And each of the n-type semiconductor regions 28 is a memory cell selecting MI.
Consists of the same manufacturing process as SFETQs, and has substantially the same function
have. In other words, the n-channel MISFETQn has the LDD structure
It is composed of High impurity concentration n⁺Type semiconductor region 37 is a source region and a drain region.
Are configured to reduce the specific resistance of each of the in-regions.
I have. n⁺The semiconductor region 37 is formed on the side wall of the gate electrode 26 by itself.
Specified by the sidewall spacer 29 formed by the alignment
Formed with self-alignment with the gate electrode 26
You. N used as source region⁺Type semiconductor region 37
Wiring 50 to which reference voltage Vss is applied is connected through connection hole 40A
Have been. N used as drain region⁺Type semiconductor
The output signal wiring 50 is connected to the area 37 through the connection hole 40A.
Has been continued. n⁺Type semiconductor region 37 and wiring 50 are connected to connection hole 40
N formed in the area specified by A⁺Type semiconductor region 41
They are electrically connected with each other. The wiring 50 is the complementary
The conductive data lines 50 are formed of the same conductive layer. CMOS p-channel MISFETQp is an insulating film 23 for element isolation.
N in the area surrounded by^-Type well region 21
The main surface is configured. p-channel MISFETQp
Then n^-Mold well region 21, gate insulating film 25, gate electrode 2
6. A pair of p-type semiconductors that are the source and drain regions
Body region 30 and a pair of p⁺Type semiconductor region 38
You. n^-Type well region 21, gate insulating film 25 and gate electrode 26
Are MISFETQs for memory cell selection, n channel
It has substantially the same function as each of the MISFETQn. The low impurity concentration p-type semiconductor region 30 is a p-channel semiconductor having an LDD structure.
The flannel MISFETQp is formed. Used as source area
High impurity concentration p⁺Through the connection hole 40A
The wiring 50 to which the power supply voltage Vcc is applied is connected.
P used as drain region⁺Type semiconductor region 38
Integrated with the output signal wiring 50 through the connection hole 40A
The output signal wiring 50 is connected. This output
The wiring 50 for the signal passes through the connection hole 52 and the wiring 53 on the upper layer.
Is connected. The wiring 53 is the shunt word line 53
And the same conductive layer. FIG. 12 shows a cross-sectional structure of the DRAM 1 including an output stage circuit.
FIG. In FIG. 12, the left side of FIG.
Similarly, a memory cell M of the memory cell array 11B is shown.
I have. The memory cell M is basically p as described above.^-Type well
The region 22 is provided. p^-The mold well region 22 has
P formed with lower impurity concentration^-Mold semiconductor substrate 20
A potential barrier region is formed between
-The breakdown voltage can be improved. Memory of memory cell M
The MISFETQs for cell selection is the p-type channel stopper region
The main part of the p-type semiconductor region 24B formed by the lateral diffusion of 24A
Since it is formed on the surface, p^-Compared to the mold well region 22
It is formed in a region where the impurity concentration is high. This p-type semiconductor
The body region 24A is a p-type channel stopper region 2 as described above.
The impurity concentration is increased to some extent by the lateral diffusion of 4A.
However, if necessary, only the new memory cell array 11B
Selectively introduces p-type impurities (impurities for adjusting the threshold voltage)
And the impurity concentration may be further increased. Of impurities
The introduction is performed by, for example, an ion implantation method. p-type semiconductor region 24B
Sets high threshold voltage of MISFETQs for memory cell selection
doing. MISFETQ for memory cell selection of DRAM1 of this embodiment
s is for a gate length of 1.0 [μm] (effective channel length is 0.7
0.8 [μm]) and the threshold voltage is about 0.8 [V] or more.
Is set to a higher value. Memory cell of the memory cell M
MISFETQs for selection are not connected to power supply wiring (Vss or Vcc).
State word line 26 or shunt word line 53 (Vss)
At the intersection, based on the noise generated in the power supply wiring,
The potential of the word line 26 or the shunt word line 53 is
Floating and malfunction (erroneous conduction) occur, so the threshold voltage
Is set high. Such unselected memory
The phenomenon in which the cell M malfunctions occurs remarkably with high integration.
You. In the right side of FIG. 12, the peripheral circuits are the same as in FIG.
Shows CMOS. This CMOS n-channel MISFETQn,
Each of the p-channel MISFETQp is a column address decoder
Circuit 12, sense amplifier circuit 13, etc.
It is used in indirect peripheral circuits such as circuit circuits. n channel
MISFETQn reduces short channel effects associated with high integration
In order to p^-Impurity concentration is higher than that of the semiconductor substrate 20
p^-It is provided in the mold well region 22. Also, n channel
MISFETQn, especially part of the direct peripheral circuit (α-ray soft error
N-channel MISFETQn of the circuit to secure
P as well as^-It is provided in the mold well region 22. n
The channel MISFETQn is a standard (standard) MISFE in DRAM1.
Configured as T, p^-To the mold well region 22 and its main surface
The threshold voltage adjustment impurity concentration.
Threshold voltage is set. n-channel MISFETQn
The gate length differs depending on the circuit used, but the gate length is 1.
When converted by 0 [μm] (effective channel length is 0.7 to 0.8
[Μm]), and the threshold voltage is in the range of about 0.3 to 0.8 [V].
Is set. That is, the n-channel MISFETQn
Since high-speed operation performance is required, transfer conductance
The threshold voltage is set to be higher. In the center of FIG. 12, an n-channel constituting an output stage circuit is provided at the center.
This shows the flannel MISFETQo. This n-channel MISFETQo
Is basically the same as the n-channel MISFETQn of the peripheral circuit.
It has a similar LDD structure. That is, n-channel MIS
FETQo is p^-Type semiconductor substrate 20, gate insulating film 25, gate
A pair of n-type electrodes 26, a source region and a drain region
Semiconductor region 28 and a pair of n⁺Type semiconductor region 37
I have. p^-Type semiconductor substrate 20, p^-Compared to the mold well region 22
N-channel MISFFTQo channel formed with low impurity concentration
It is used as a flannel formation region. This n-channel MI
SFETQo constitutes a push-pull type output stage circuit, for example.
I have. The n-channel MISFETQo depends on the circuit used and the requirements.
The gate length differs depending on the specification
When converted in [μm] (effective channel length is 0.7 to 0.8
[Μm]) and the threshold voltage is as low as about 0.3 [V] or less.
Is set to a higher value. That is, n-channel MISFETQo
Reduces the body effect constant and increases the output signal level
It is configured as follows. Also, the p^-Type semiconductor substrate 20
Use is especially recommended for manufacturing processes due to the low impurity concentration on the surface.
Process, set the threshold voltage of n-channel MISFETQo low.
There are features that are easy to determine. Originally adopts twin well method
If you want to reduce the number of manufacturing processes,
MISFETs Qn and Qo have p^-Type well area
22 are formed, but the DRAM 1 of this embodiment is based on the above-described reason.
Come p^-Part of the main surface of the mold semiconductor substrate 20 is used. As described above, the memory cell selection of the (13-8) memory cell M is performed.
Selective MISFETQs, n-channel MISFETQn constituting peripheral circuits
And an n-channel MISFETQo forming an output stage circuit
In DRAM1, each channel type is set to the same n-type, and
Each gate length (effective channel length) size is substantially the same.
MISFETQs for memory cell selection, n channels
Respective thresholds of channel MISFETQn and n-channel MISFETQo
Reduce the voltage sequentially. With this configuration, the power is generated
Based on the noise, the memory cell of the non-selected memory cell M
MISFETQs for device selection can be prevented from erroneously conducting.
Therefore, each of the information writing operation and the information reading operation
And the electrical reliability can be improved.
The substrate effect constant of n-channel MISFETQo in a circuit
The output signal level and drive external devices.
Dynamic capacity can be improved, and further, the memory cell
M chips for peripheral circuits compared to M memory cell selection MISFETQs
Since the threshold voltage of channel MISFETQn has been lowered,
Improving the conductance and increasing the operating speed
it can. (15-9) The n-channel MISFET of the output stage circuit
Qo to p^-The memory cell formed on the main surface of the semiconductor substrate 20
MISFETQs for memory cell selection of M, n-channel of peripheral circuit
Each of the MISFETs Qn is^-On the main surface of the semiconductor substrate 20
P with higher impurity concentration^-Lord of mold well area 22
Make up the surface. With this configuration, n channels of the output stage circuit are provided.
The flannel MISFETQo is p^-Type semiconductor substrate 20 has low impurity concentration
So p^-Impurity concentration on the main surface of the
Easily lower threshold voltage by controlling impurity concentration
And a memory cell selection of the memory cell M.
MISFETQs for selection and n-channel MISFETQn for peripheral circuits
Is p^-Type semiconductor substrate 20 and p^-Impurity concentration with the type well region 22
It is possible to form a potential barrier region due to the difference in power
It is possible to improve the α-ray soft error withstand voltage.
Wear. Improvement of α-ray soft error withstand voltage
Since the area occupied by the cell M can be reduced, the degree of integration
Can be improved. The word driver circuit (WL) 15 of the DRAM 1 (see FIG. 3)
Figure 13 (Equivalent circuit)
Figure). In Fig. 13, ▲ ▼ indicates a word clear message.
No., WD is the word decode signal, XI is the word boost signal
, XP is the self-boost node precharge signal.
You. XIJL is the discharge signal of the word boost potential
is there. XIJ0, XIJ9, XNK, BXlI, BX2I
This is a decode signal of the data circuit. Break in generator circuit
The MISFETs Qc1 and Qc2 for high withstand voltage cut
Each is arranged. MISFET Qc1, Qc2 for high withstand voltage cut
Are composed of n channels. The generator circuit includes a self-boost node
Precharged by charge signal XP (= Low)
And the node N is pre-set to the power supply potential Vcc-threshold voltage Vth.
Charged. Next, the word boost potential XI is
When the voltage rises above Vcc, the gate of the n-channel MISFET Qd
Due to the coupling of the capacitance, the node N becomes a stray capacitance.
It rises to a high potential (about 10 [V] or more) determined by this.
The drain region of each of the high breakdown voltage cut MISFETs Qc1 and Qc2
The region is connected to the node N which has risen to the high potential. MISFETs Qc1 and Q for high withstand voltage cut of the generator circuit
Each of c2 is configured as shown in Fig. 14 (plan view of the main part).
ing. Each of the high-breakdown voltage MISFETs Qc1 and Qc2 is an element
In the insulating film for isolation 23 and the p-type channel stopper region 24A
In the enclosed area, p^-Lord of mold well area 22
The surface is configured. In other words, MISFETQc for high withstand voltage cut
1, each of Qc2 is p_-Mold well region 22, gate insulating film 25,
A pair of a gate electrode 26, a source region and a drain region
N-type semiconductor region 28 and a pair of n⁺Composed of semiconductor region 37
Have been. The gate electrode 26 includes the inter-element isolation insulating film 23 and
In the region surrounded by the p-type channel stopper region 24A
Thus, the planar shape is formed in a ring shape. Gate electrode
26 is provided with a T-shaped branch at a part thereof.
The part (26) formed on the insulating film
No. wiring 50. Used as drain region
N⁺Type semiconductor region 37 is the ring-shaped gate
The electrode 26 is provided in an area defined by the periphery.
You. The other n used as the source region⁺Semiconductor region
37 denotes an element isolation insulating film 23 and a p-type channel
In the region surrounded by the wrapper region 24A,
It is provided on the outer periphery of the gate electrode 26 having a ring shape. Toes
MISFETs Qc1 and Qc2 for high withstand voltage cut each have one of n⁺
Channel formation region around the semiconductor region 37
The other n⁺Are provided with a mold semiconductor region 37. Previous
The other n⁺Type semiconductor region 37 so that a high potential is applied.
, But one of n⁺The type semiconductor region 37 is a type p channel.
Layout that does not touch the stopper area 24A.
I have. N of each of the high-breakdown-voltage cut MISFETs Qc1 and Qc2⁺Mold semiconductive
The signal wiring 50 is connected to the body region 37 through the connection hole 40A.
ing. One of n⁺Type semiconductor region 37 (high voltage side)
The outer peripheral end of the signal wiring 50 is placed on the gate electrode 26 (or the source
(Area side). The ring-shaped
The gate electrode 26 is located at the center of the ring shape due to the step shape.
In the portion, the surface of the interlayer insulating film 40 underlying the signal wiring 50
A recess is formed in the substrate. This recess processes the signal wiring 50
Signal during exposure of etching mask (photoresist film)
Due to the diffraction phenomenon based on the reflection of the surface of the wiring 50, etc.
This reduces the size of the switching mask. Accordingly
And the signal wiring 50 (etching mask to process it)
Processing should be performed in an area where the diffraction phenomenon does not occur
You. Thus, the (32-17) p-type channel stopper region 24
DRA with high withstand voltage cut MISFETQc surrounded by A
In M1, the high withstand voltage cut MISFET Qc
One of the applied n⁺Channel around the semiconductor region 37
Region (p^-Low voltage is applied via the mold well region 22)
The other n⁺Surrounded by the semiconductor region 37, and
The gate electrode is formed with the gate insulating film 25
26, and the p-type channel stopper region
24A to the other n⁺Around the periphery of the semiconductor region 37
To achieve. With this configuration, the high withstand voltage cut MISFET Qc
One of n⁺Semiconductor region 37 is a p-type channel stopper region
Since it does not contact 24A, one of n⁺Type semiconductor region 37
Improved withstand voltage and high withstand voltage of MISFETQc for high withstand voltage cut
Can be (34-18) One of the MISFETQc for high withstand voltage cut
N⁺Outside the upper signal wiring 50 connected to the semiconductor region 37
The peripheral end is arranged on the gate electrode 26 or the other n⁺
The semiconductor device is pulled out to the top of the mold semiconductor region 37 and arranged. In this configuration
From the one n⁺Semiconductor region 37 and the signal distribution of the upper layer
The step of the gate electrode 26 is formed on the surface of the interlayer insulating film 40 between the line 50 and the like.
A concave shape is formed in the difference shape, and the signal of the upper layer is caused by this concave shape.
Etching mask for processing wiring 50
The size is reduced by the light reflected on the surface of the wiring formation layer (50).
Signals in the upper layer can be reduced
The processing accuracy of the wiring 50 can be improved. External terminals (bonding) arranged at the outermost periphery of the DRAM1
Fig. 15 (enlarged cross section of the main part)
Figure). As shown in FIG. 15, the external terminal BP is manufactured.
It is formed by the second layer wiring 53 in the process. DRAM
The wiring 53 used inside 1 is
Transition metal film 53A, aluminum
And a three-layer structure in which each of a transition film 53B and a transition metal film 53C is laminated.
Has been established. On the other hand, the external terminal BP is
After removing the transfer metal film 53C, the lower transition metal film 53A and the middle layer
It has a two-layer structure in which each of the aluminum films 53B is sequentially laminated.
Has been established. The bonding equipment is shown in the table of external terminals BP.
The difference in reflectance between the surface and the surface of the passivation film 54
Thus, the bonding wire 4 is attached to the surface of the external terminal BP.
Positioning for bonding is performed. Wiring of 53
The upper transition metal film 53C has a low reflectance,
Since the difference in reflectance between the external terminal BP and the
The surface has a higher reflectance than the upper transition metal film 53C
The aluminum film 53B is exposed. The surface of the aluminum film 53B of the external terminal BP is exposed.
The process of forming the silicon oxide film 54 of the upper passivation film 54
A and the bonding opening 55 formed in the silicon nitride film 54B.
Performed in the same process as forming (using the same mask
Form). Resin film 54C above passivation film 54
Is larger than that above the bonding opening 55.
A bonding opening 56 of a suitable size is provided. Thus, (7-4) formation on the passivation film 54
Bonding through the bonded opening 55 (and 56)
The same conductive layer as the internal wiring 53 to which the wiring 4 is connected.
In the DRAM 1 having the external terminal BP formed,
Aluminum wiring (or its alloy film) 53B
The transfer metal film 53C is composed of a composite film in which
The external terminal BP is connected to the aluminum with the transition metal film 53C removed.
It is composed of an aluminum film 53B. With this configuration, bonding
In the process, the reflectance of the surface of the external terminal BP is improved,
Due to the difference in reflectance between the terminal BP and the passivation film 54
It is possible to reliably recognize the bonding position of the external terminal BP.
It can reduce bonding defects and assemble DRAM1
The yield of the process can be improved. Also bondi
When the forming wire 4 is formed of aluminum wire,
The surface of the external terminal BP exposes the aluminum film 53B.
Between the external terminal BP and the bonding wire 4
Improve durability and reduce bonding defects
Can be. As a result, the yield of the DRAM1 assembly process can be further improved.
Can be improved. (8-5) The aluminum film 53 of the external terminal BP
The transition metal film 53C on B is formed on the passivation film 54
Within the area defined by the specified bonding opening 55
Remove. With this configuration, the transition of the surface of the external terminal BP
The etching mask for removing the transfer metal film 53C is
Etch to form a bonding opening 55 in the activation film 54
Mask can be used as a mask
To reduce the number of manufacturing steps for DRAM1
be able to. Next, regarding a specific method of manufacturing the above-described DRAM 1, the first method will be described.
6 to 33 (cross-sectional views of main parts for each predetermined manufacturing process)
This will be briefly described with reference to FIG.

[Well formation process]

First, a p ^- type semiconductor substrate 20 made of single crystal silicon is prepared. Next, a silicon oxide film 6 is formed on the main surface of the p ^- type semiconductor substrate 20.
0, each of the silicon nitride films 61 is sequentially laminated. Silicon oxide film 60
Is formed by a steam oxidation method at a high temperature of about 900 to 1000 [° C.], for example, with a film thickness of about 30 to 50 [nm]. This silicon oxide film 60 is used as a buffer layer.
The silicon nitride film 61 is used as an impurity introduction mask and an oxidation resistant mask. The silicon nitride film 61 is deposited by, for example, a CVD method, and is formed with a thickness of about 30 to 60 [nm]. Next, the silicon nitride film 61 in the n ⁻ -type well region (21) formation region
Is removed to form a mask. This mask is formed using a photolithography technique (a technique for forming a photoresist mask) and an etching technique. Next, as shown in FIG. 16, an n-type impurity 21n is introduced into the main surface of the p ⁻ -type semiconductor substrate 20 through the silicon oxide film 60 using the mask (61). The n-type impurity 21n is, for example, 10
Using P having an impurity concentration of about ¹³ [atoms / cm ² ],
It is introduced by an ion implantation method with an energy of about 0 [KeV]. Next, as shown in FIG. 17, a silicon oxide film 60 exposed from the mask is grown using the mask (61), and a silicon oxide film 60A thicker than that is formed. Silicon oxide film 60A
Is formed only in the n ⁻ -type well region (21) formation region, and is used as a mask for removing the mask (61) and an impurity introduction mask. The silicon oxide film 60A has a thickness of about 900 to 1000
It is formed by a steam oxidation method at a high temperature of [° C.], for example, so as to finally have a film thickness of about 110 to 150 [nm]. By the heat treatment step of forming the silicon oxide film 60A, the introduced n-type impurity 21n is slightly diffused, and n ⁻
Semiconductor region (finally becomes n ^- type well region 21) 21
A is formed. Next, the mask (61) is selectively removed. The mask (61) is removed with, for example, hot phosphoric acid. Thereafter, although not shown, an impurity introduction mask (for example, a photoresist film) is formed in a formation region (see FIG. 12) of the n-channel MISFET Qo of the output stage circuit of the DRAM 1. Next, as shown in FIG. 18, using the silicon oxide film 60A and the impurity introduction mask (not shown), a p ^- type semiconductor substrate 20 is formed on the main surface of the p ⁻ type semiconductor substrate 20 through the silicon oxide film 60. Impurity 22p is introduced. The p-type impurity 22p is, for example, 10 ¹² to 10 ¹³
BF ² (or B) having an impurity concentration of about [atoms / cm ² ] is used, and is introduced by ion implantation at an energy of about 50 to 70 [KeV]. The p-type impurity 22p is not introduced into the n ⁻ -type well region (21) formation region because the silicon oxide film 60A has a large thickness. Next, the n-type impurity 21n and the p-type impurity 22p are respectively extended and diffused to form an n ⁻ -type well region 21 and a p ⁻ -type well region 22, as shown in FIG. The n ⁻ -type well region 21 and the p ⁻ -type well region 22 are formed by performing a heat treatment in a high temperature atmosphere of about 1100 to 1300 [° C.]. As a result, the p ^- type well region 22 is formed in self-alignment with the n ^- type well region 21. Thereafter, the impurity introduction mask formed in the region of the output stage circuit is removed.

[Separation region forming step]

Next, a silicon nitride film 62 is formed on the entire surface of the substrate including the silicon oxide film 60 and 60A. This silicon nitride film 62 is used as an impurity introduction mask and an oxidation resistant mask. The silicon nitride film 62 is deposited by, for example, a CVD method,
m]. Next, the silicon nitride film 62 is removed between the MISFET formation regions (inter-element isolation insulating film formation regions), and a mask is formed with the remaining silicon nitride film 62. The formation of the mask (62) is performed using a photolithography technique and an etching technique. Thereafter, using the mask (62), as shown in FIG. 20, the silicon oxide film 60 is formed on the main surface of the p ⁻ -type well region 22.
Through which p-type impurities 24p are introduced. The p-type impurity 24p is
Since silicon oxide film 60A having a larger thickness than silicon oxide film 60 formed on the main surface of p ⁻ -type well region 22, it is not introduced into the main surface of n ⁻ -type well region 21. That is, the p-type impurity 24p is selectively introduced into the main surface of the p ⁻ -type well region 22. The p-type impurity 24p is, for example, 10 ¹³ [atoms
/ cm ² ] and an ion implantation method with an energy of about 50 to 70 [KeV] using BF ₂ having an impurity concentration of about [cm ² ]. When introducing the p-type impurity 24p, an etching mask (photoresist film) obtained by processing the mask (62) may be used together. Next, using the mask (62), each of the silicon oxide films 60 and 60A exposed from the mask (62) is grown to form an inter-element isolation insulating film (field insulating film) 23. The element isolation insulating film 23 is subjected to a heat treatment of about 100 to 140 [min] in a nitrogen gas atmosphere at a high temperature of, for example, about 1000 [° C.]
It can be formed by oxidizing about 140 to 170 [minutes] by a steam oxidation method. Alternatively, the element isolation insulating film 23 may be formed only in a steam oxidation atmosphere. The element isolation insulating film 23 is formed to a thickness of, for example, about 600 to 800 [nm]. The p-type impurity 24p introduced into the main surface portion of the p ⁻ -type well region 22 is stretched and diffused by the same manufacturing process as the process of forming the element isolation insulating film 23 and the p-type channel. A stopper region 24A is formed. When the p-type channel stopper region 24A is formed, since the relatively long heat treatment is performed as described above, the p-type impurity 24p has a large lateral diffusion amount. Therefore, especially in the memory cell array 11B, p
The p-type impurity 24p is diffused to form a p-type semiconductor region 24B. On the other hand, an n-channel MISFET that forms the CMOS of peripheral circuits
In each of the formation regions of Qn and Qo,
Since the size is larger than the memory cell M, the p-type impurity
The lateral diffusion amount of 24p is relatively small, and the p-type impurity 24p is diffused only in the vicinity of the element isolation insulating film 23.
That is, the p-type semiconductor region 24B is not substantially formed in each of the formation regions of the n-channel MISFETs Qn and Qo. Therefore, the p-type semiconductor region 24B is not formed in each of the formation regions of the n-channel MISFETs Qn and Qo of the peripheral circuit.
The memory cell array 11B is selectively formed in the formation region. Moreover, the p-type semiconductor region 24B
It can be formed in the same manufacturing process as the mold channel stopper region 24A. The p-type channel stopper region 24A, p
After the heat treatment, each of the type semiconductor regions 24B has 10 ¹⁶ to 10 ¹⁷ [ato
[ms / cm ³ ]. After this, the 21st
As shown, the mask (62) is removed. Next, a silicon oxide film 60 on the main surface of the p ^- type well region 22 is formed.
Then, the silicon oxide film 60A on the main surface of the n ⁻ -type well region 21 is removed to expose the respective main surfaces of the p ⁻ -type well region 22 and the n ⁻ -type well region 21.

[Gate insulating film forming process]

Next, a silicon oxide film 63 is formed on each of the main surfaces of the exposed p ⁻ -type well region 22 and n ⁻ -type well region 21. The silicon oxide film 63 is formed mainly by a silicon nitride so-called white ribbon formed at the end of the inter-element isolation insulating film 23 by the silicon nitride film (mask) 62 when the inter-element isolation insulating film 23 is formed. Performed to oxidize. The silicon oxide film 63 is, for example, 900 to 1000
[℃] formed by high temperature steam oxidation method, 40 ~ 10
It is formed with a thickness of about 0 [nm]. Next, in the element formation region defined by the element isolation insulating film 23, the p ⁻ -type well region 22 (the memory cell array 11B
In this case, a p-type impurity 64p for adjusting the threshold voltage is introduced into the main surface of the p-type semiconductor region 24B), the main surface of the n ⁻ -type well region 21, and the main surface of the p ⁻ -type semiconductor substrate 20, that is, the entire substrate. This p-type impurity 64p is, for example, 5 × 10 ^{11 to} 9 × 10 ¹¹
Using B having an impurity concentration of about [atoms / cm ² ], 20 to 40 [K
eV] is introduced by ion implantation. This p
The type impurity 64p is mainly introduced to adjust the threshold voltage of each of the n-channel MISFETs Qs, Qn, and Qo. Next, in the element formation region defined by the element isolation insulating film 23, a p-type impurity 65p for adjusting the threshold voltage is introduced into the main surface of the n ⁻ -type well region 21. The p-type impurity 65p is introduced by ion implantation at an energy of about 20 to 40 [KeV] using, for example, B having an impurity concentration of about 10 ¹² [atoms / cm ² ]. p-type impurity 65p is mainly p-channel MISFETQ
A p-threshold voltage has been introduced to adjust. Next, as shown in FIG. 22, in the formation region of the memory cell array 11B defined by the element isolation insulating film 23, p
^- p to adjust the threshold voltage to the main surface of the mold well region 22
A type impurity 66p is introduced. The p-type impurity 66p is, for example, 10 ¹¹
Using B having an impurity concentration of about [atoms / cm ² ], 20 to 40 [K
eV] is introduced by ion implantation. The p-type impurity 66p is mainly MISFETQ for selecting a memory cell of the memory cell M.
S has been introduced to adjust the threshold voltage. The introduction of the p-type impurity 66p can be omitted when the impurity concentration of the p-type semiconductor region 24B is changed or when the amount of introduction of the p-type impurity 65p is close. In addition, the p
The order of introducing the type impurities 64p, 65p, and 66p may be changed. The introduction of each of the p-type impurities 64p, 65p, and 66p may be performed depending on how to set the respective impurity concentrations of the p ⁻ -type semiconductor substrate 20, the p ⁻ -type well region 22, and the n ⁻ -type well region 21. Can be omitted. Next, the silicon oxide film 63 is selectively removed to expose respective main surfaces of the p ⁻ -type well region 22 and the n ⁻ -type well region 21 (not shown, but also including the p ⁻ -type semiconductor substrate 20). Next, the exposed p ^- type well region 22, the n ^- type well region
A gate insulating film 25 is formed on each of the main surfaces 21. The gate entanglement film 25 is formed by a high temperature steam oxidation method of about 800 to 1000 [° C.] and has a thickness of about 15 to 25 [nm].

[Gate Wiring Forming Step 1] Next, a polycrystalline silicon film is formed on the entire surface of the substrate including the gate insulating film 25 and the element isolation insulating film 23. The polycrystalline silicon film is deposited by a CVD method and has a thickness of about 150 to 300 [nm]. An n-type impurity such as P for reducing the resistance value is introduced into the polycrystalline silicon film by a thermal diffusion method. Next, an interlayer insulating film 27 is formed on the entire surface of the polycrystalline silicon film. The interlayer insulating film 27 includes a silicon oxide film 27A formed on the surface of the polycrystalline silicon film and a silicon oxide film 27B laminated on the silicon oxide film 27A. The lower silicon oxide film 27A is 80
20 to 50 in an oxygen gas atmosphere of about 0 to 1000 [° C]
It is formed with a thickness of about [nm]. The upper silicon oxide film 27B is formed by a CVD method using an inorganic silane gas (SiH ₄ or SiH ₂ Cl ₂ ) and a nitrogen oxide gas (N ₂ O) as a source gas. The silicon oxide film 27B as the upper layer of the interlayer insulating film 27 is formed with a thickness of, for example, about 250 to 400 [nm]. Next, as shown in FIG. 23, each of the interlayer insulating film 27 and the polycrystalline silicon film is sequentially etched using an etching mask (not shown) to form a gate electrode 26 and a word line (WL) 26.
To form In addition, an interlayer insulating film 27 is left on each of the gate electrode 26 and the word line 26. The etching is performed by anisotropic etching. In addition, by using a chopping etching method described later, the etching can increase the anisotropy of the etching and reduce the amount of over-etching.

[Low concentration semiconductor region forming step]

Next, in order to reduce contamination due to impurity introduction,
A silicon oxide film (not numbered) is formed on the entire surface of the substrate.
This silicon oxide film is formed on the respective main surfaces of the p ⁻ -type well region 22 and the n ⁻ -type well region 21 exposed by the etching, and on the respective sidewalls of the gate electrode 26 and the word line 26. The silicon oxide film is formed in an oxygen gas atmosphere at a high temperature of, for example, about 850 to 950 [° C.] and has a thickness of about 10 to 80 [nm]. Next, the p ^- type well region 22 is formed in each of the memory cell array 11B, the n-channel MISFETs Qn, and Qo by using the element isolation insulating film 23 and the interlayer insulating film 27 (and the gate electrode 26) as an impurity introduction mask. , P ^- type semiconductor substrate 20 is doped with an n-type impurity into each main surface thereof. By introducing the n-type impurity, an n-type semiconductor region 28 having a low impurity concentration formed by self-alignment with the gate electrode 26 or the word line 26 can be formed. The n-type impurity is, for example, 10 ¹³ [atom
s / cm ² ] of P (or As) with an impurity concentration of about 80 to 1
It is introduced by an ion implantation method with an energy of about 20 [KeV].
As described above, the memory cell selecting MISF of the memory cell M is used.
At least the n-type semiconductor region 28 of the ETQs that is connected to the information storage capacitor C having a stacked structure is 10 ¹⁴ [atoms / cm 2
² ] is formed by ion implantation with a low impurity concentration of less than ² ]. Since the n-type semiconductor region 28 is formed with a low impurity concentration, the MISFET Qs for selecting a memory cell, the n-channel MISFET
Each of Qn and Qo can be configured with an LDD structure. When forming the n-type semiconductor region 28, the formation region of the p-channel MISFET Qp is covered with an impurity introduction mask (photoresist film). By the step of forming the n-type semiconductor region 28, the memory cell selecting MISFETs Qs of the memory cell M are substantially completed. Next, an insulating separation between the device film 23 and the interlayer insulating film 27 (and the gate electrode 26) as an impurity introducing mask, in the formation region of the p-channel MISFET Qp, n ^- a p-type impurity into the main surface of the mold well region 21 Introduce. By introducing the p-type impurity, as shown in FIG. 24, a low-impurity-concentration p-type semiconductor region 30 formed by self-alignment with the gate electrode 26 can be formed. The p-type impurity is, for example, 10 ¹³ [at
oms / cm ² ] of BF ₂ (or B) with an impurity concentration of about 60
It is introduced by an ion implantation method with an energy of about 100 [KeV]. When introducing a p-type impurity, the memory cell array 11
The respective formation regions of the B and n-channel MISFETs Qn and Qo are covered with an impurity introduction mask (photoresist film). Next, although not shown, in the formation region of the electrostatic breakdown prevention circuit added to the input stage circuit (or the output stage circuit) of the DRAM 1, an n-type impurity is added at a high impurity concentration to at least the formation region of the drain region of the n-channel MISFET Qn. Introduce. In the n-channel MISFET Qn, by introducing an additional n-type impurity, an excessive voltage which is input to the drain region and causes electrostatic breakdown can easily escape to the p ⁻ -type well region 22 side. That is, the n-channel MISFETQn can increase the electrostatic breakdown voltage.

[Spacer Forming Step and Connection Hole Forming Step 1] Next, as shown in FIG. 25, the gate electrode 26 and the word line
26, sidewall spacers 29 are formed on the respective side walls of the upper interlayer insulating film 27. The side wall spacer 29 is formed by depositing a silicon oxide film,
The silicon oxide film can be formed by performing anisotropic etching such as RIE by an amount corresponding to the deposited film thickness. The silicon oxide film of the sidewall spacer 29 has the same film quality as the silicon oxide film 27B on the interlayer insulating film 27.
CV using inorganic silane gas and nitric oxide gas as source gas
Formed by D method. This silicon oxide film is, for example, 200 to 400 [n
m]. Side wall spacer 29
Length in the gate length direction (channel length direction) is about 200 to 400
[Nm] is formed. The side wall spacer 29 may be formed in a part of the region, if necessary. Next, a sidewall spacer is formed on the interlayer insulating film 27.
29, an interlayer insulating film 31 is formed on the entire surface of the substrate including the upper surface. This interlayer insulating film 31 is a stacked information storage capacitor C
Are used as etching stopper layers when processing the respective electrode layers. The interlayer insulating film 31 is formed to electrically separate the lower electrode layer (33) of the stacked information storage capacitor C from the gate electrode 26 and the word line 26 of the MISFET Qs for memory cell selection. ing. The interlayer insulating film 31 is formed with a thickness that allows for the amount of shaving due to over-etching during processing of the upper conductive layer, the amount of shaving in the cleaning step, and the like. The interlayer insulating film 31 is formed of a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas. That is, the interlayer insulating film 31 can reduce stress generated based on a difference in linear expansion coefficient between the dielectric film (34) of the stacked information storage capacitor C and the underlying interlayer insulating film 27. it can. The interlayer insulating film 31 is formed with a thickness of, for example, about 100 to 200 [nm]. Next, as shown in FIG. 26, the other n-type semiconductor region (the side to which the lower electrode layer 33 of the information storage capacitance element C is connected) 28 of the memory cell selection MISFET Qs in the memory cell M formation region.
The upper interlayer insulating film 31 is removed, and connection holes 31A and 32 are formed.

[Gate Wiring Forming Step 2] Next, as shown in FIG. 27, the lower electrode layer 33 of the information storage capacitor C having the stacked structure of the memory cell M is formed. The lower electrode layer 33 has a portion connected to the n-type semiconductor region 28 through each of the connection holes 31A and 32, and another portion connected to the interlayer insulating film.
It extends on 27 and 31. The lower electrode layer 33 is formed to be larger than the opening size of the connection hole 31A formed in the interlayer insulating film 31 by at least an amount corresponding to a mask alignment allowance in a manufacturing process. The lower electrode layer 33 is formed of a polycrystalline silicon film deposited by a CVD method, and has a large thickness of about 200 to 400 [nm]. This polycrystalline silicon film is formed by the second-layer gate wiring forming step in the manufacturing process. After depositing the polycrystalline silicon film, the lower electrode layer 33 introduces an n-type impurity for reducing the resistance value, for example, P into the polycrystalline silicon film by a thermal diffusion method. It is formed by processing a polycrystalline silicon film. The photolithography technique includes a step of forming an etching mask (photoresist film) and a step of removing the etching mask. The etching mask removal step is performed by downstream plasma processing using a mixed gas of freon gas (CHF ₃ ) and oxygen gas (O ₂ ).
This process has the effect of reducing damage to each element of the DRAM 1. However, the present inventor has confirmed that the removal of the etching mask by the plasma treatment causes a phenomenon of selectively etching P (n-type impurity) deposited on the surface of the polycrystalline silicon film by the freon gas.
The selective etching of the deposited P is not preferable because it forms minute holes in the surface of the lower electrode layer 33 and deteriorates the dielectric strength of the dielectric film (34). Therefore, the DR of the present embodiment
AM1 deposits a polycrystalline silicon film, introduces an n-type impurity, oxidizes the surface of the polycrystalline silicon film before removing the etching mask, and removes the oxidized silicon film to form a polycrystalline silicon film.
Is removed. Oxidation of the surface of the polycrystalline silicon film may be sufficient to form a silicon oxide film having a thickness of about several nm on the surface of the polycrystalline silicon film. The addition of this oxidation step
Not only the second layer gate wiring forming step (33) but also the first layer
The present invention can be applied to each of the layer gate wiring forming step (26) and the third layer gate wiring forming step (35). Further, the anisotropic etching is used in the step of etching the polycrystalline silicon film. In the etching step, by using a chopping etching method described later, the anisotropy of the etching can be increased, and the amount of over-etching can be reduced, so that the etching residue can be reliably removed. As described above, a method of manufacturing a DRAM 1 in which a polycrystalline silicon film is deposited, an n-type impurity is introduced into the polycrystalline silicon film by thermal diffusion, and then the polycrystalline silicon film is processed using photolithography technology and etching technology A step of removing an n-type impurity deposited on the surface of the polycrystalline silicon film after introducing the n-type impurity into the polycrystalline silicon film and before the step of removing the etching mask by the photolithography technique. With this configuration, minute holes are not formed in the surface of the polycrystalline silicon film due to removal of the etching mask.
That is, in the information storage capacitor C having the stacked structure of the DRAM 1, the dielectric strength of the dielectric film (34) can be improved. In the region defined by the connection hole 32, the n-type impurity introduced into the lower electrode layer 33 is diffused into the main surface of the other n-type semiconductor region 28 of the memory cell selecting MISFET Qs, and the n ⁺ -type The semiconductor region 33A is formed. Each of the n ⁺ -type semiconductor region 33A and the n-type semiconductor region 28 is integrally formed. The n ⁺ type semiconductor region 33A is a MISFET Q for selecting a memory cell.
The ohmic characteristics of the other n-type semiconductor region 28 of s and the lower electrode layer 33 can be improved (reduction of contact resistance value).

[Dielectric film forming process]

Next, as shown in FIG. 28, a dielectric film 34 is formed on the entire surface of the substrate including the lower electrode layer 33 of the information storage capacitor C having the stacked structure of the memory cell M. The dielectric film 34
As described above, basically, the silicon nitride film 34A and the silicon oxide film 3
4B are formed in a two-layer structure in which each of the layers is sequentially laminated. The lower silicon nitride film 34A is deposited by, for example, a CVD method, and
It is formed with a thickness of about [nm]. When forming the silicon nitride film 34A, entrapment of oxygen is suppressed as much as possible. When the silicon nitride film 34A is formed on the lower electrode layer 33 (polycrystalline silicon film) at a normal production level, a very small amount of oxygen is involved, so that a gap between the lower electrode layer 33 and the silicon nitride film 34A is formed. Then, a natural silicon oxide film (not shown) is formed. The upper silicon oxide film 34B of the dielectric film 34 is formed by applying a high pressure oxidation method to the lower silicon nitride film 34A,
m]. When the silicon oxide film 34B is formed, the thickness of the lower silicon nitride film 34A is slightly reduced, so that the silicon nitride film 34A is finally formed with a thickness of about 4 to 8 [nm]. The silicon oxide film 34B is basically formed in an oxygen gas atmosphere at a high pressure of 1.5 to 10 [atm] and a high temperature of about 800 to 1000 [° C]. In this embodiment, the silicon oxide film 34B has a high pressure of 3 to 4 [atm] and an oxygen flow rate (source gas) of 4 to 6 [l / min] and a hydrogen flow rate (source gas) of 3 to 4 [l / min]. It is formed as 10 [l / min]. The silicon oxide film 34B formed by the high-pressure oxidation method can be formed to have a desired thickness in a shorter time than a silicon oxide film formed at normal pressure (1 [atm]). In other words, the high pressure oxidation method
Since the high-temperature heat treatment time can be shortened, the pn junction depth of the source region and the drain region of the memory cell selecting MISFETQs and the like can be reduced. Therefore, the dielectric film 34 has a three-layer structure in which a natural silicon oxide film, a silicon nitride film 34A, and a silicon oxide film 34B are sequentially stacked. The natural silicon oxide film can be made thinner by reducing entrapment of oxygen. Further, although the number of manufacturing steps increases, the natural silicon oxide film is nitrided, and the dielectric film 34 is formed.
In a two-layer structure.

[Gate Wiring Forming Step 3] Next, a polycrystalline silicon film is deposited on the entire surface of the substrate including on the dielectric film 34. Polycrystalline silicon film is deposited by CVD method,
It is formed with a thickness of about 250 [nm]. This polycrystalline silicon film is formed by a third-layer gate wiring forming step in the manufacturing process. Thereafter, an n-type impurity for reducing the resistance value, for example, P is introduced into the polycrystalline silicon film by a thermal diffusion method. Next, an etching mask 67 is formed on the polycrystalline silicon film over the entire surface of the memory cell array 11B except for a connection region between one of the n-type semiconductor regions 28 of the memory cell selecting MISFETQs and the complementary data line (50). . Etching mask 67
Is formed of, for example, a photoresist film using a photolithography technique. Thereafter, the polycrystalline silicon film and the dielectric film 34 are sequentially etched using the etching mask 67, thereby forming the upper electrode layer 35 with the polycrystalline silicon film as shown in FIG. be able to. The polycrystalline silicon film is etched by, for example, a plasma step etching method. By forming this upper electrode layer 35, the information storage capacitor C having a stacked structure is formed.
Are substantially completed, and as a result, the memory cell M of the DRAM 1 is completed. After the completion of the memory cell M, the etching mask
67 remove.

[High concentration semiconductor region forming step]

Next, on the upper electrode layer 35 of the stacked information storage capacitor C, on the n-channel MISFETQn, and on the p-channel MI
An insulating film 36 is formed on the entire surface of the substrate including each of the SFETs Qp.
The insulating film 36 is mainly used as a contamination prevention film when introducing impurities. The insulating film 36 is made of, for example, an organic silane gas (Si (O
A silicon oxide film deposited by a CVD method using C ₂ H ₅ ) ₄ ) as a source gas or a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas, and formed to a thickness of about 30 [nm]. I do. Next, the n-channel M which constitutes the CMOS of the peripheral circuit of the DRAM 1
In the formation region of the ISFET Qn (including Qo), an n-type impurity is introduced into the main surface of the p ⁻ -type well region 22. In order to introduce the n-type impurity, the gate electrode 26 and the interlayer insulating film
7. Each of the sidewall spacers 29 is used as an impurity introduction mask. When introducing an n-type impurity, the formation region of the memory cell M and the formation region of the p-channel MISFET Qp are covered with an impurity introduction mask (photoresist film). As the n-type impurity, for example, As having an impurity concentration of about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ² ] is used, and is introduced by ion implantation at an energy of about 70 to 90 [KeV]. Next, a p-type impurity is introduced into a main surface portion of the n ⁻ -type well region 21 in a formation region of the p-channel MISFET Qp forming the CMOS. In order to introduce the p-type impurity, mainly, the gate electrode 26, the interlayer insulating film 27 thereover,
Are used as impurity introduction masks. When introducing the p-type impurity, the formation region of the memory cell M and the formation region of the n-channel MISFETQn are covered with an impurity introduction mask. The p-type impurity is introduced by ion implantation at an energy of about 60 to 90 [KeV] using, for example, BF ₂ having an impurity concentration of about 10 ¹⁵ [atoms / cm ² ]. Thereafter, the n-type impurity and the p-type impurity are extended and diffused, and as shown in FIG. 30, the n ⁺ -type semiconductor region 37 and the n ⁻ -type well region 21 are formed on the main surface of the p ⁻ -type well region 22. On the main surface of
Each of the p ⁺ type semiconductor regions 38 is formed. The stretching diffusion is performed by heat treatment at a high temperature of about 900 to 1000 [° C.]
Perform about 0 [minutes]. The n channel MISFETQn is substantially completed by the process of forming the n ⁺ type semiconductor region 37, and the p channel MISFETQp is substantially completed by the process of forming the p ⁺ type semiconductor region 38.

[Interlayer Insulating Film Forming Step 1] Next, the interlayer insulating films 39 and 40 are sequentially laminated on the entire surface of the substrate including each element of the DRAM 1. Lower interlayer insulating film 39
Is formed of a silicon oxide film deposited by a CVD method using an organic silane gas as a source gas, for example. The interlayer insulating film 39 is formed by impurities (P and B, respectively) from the upper interlayer insulating film 40 (BPSG).
Is formed to a thickness of, for example, about 150 to 250 [nm] in order to prevent leakage. The upper interlayer insulating film 40 is formed of, for example, a silicon oxide film (BPSG film) deposited by a CVD method. The interlayer insulating film 40 is formed with a thickness of, for example, about 400 to 700 [nm]. In the interlayer insulating film 40, in a nitrogen gas atmosphere,
The flow is performed at a temperature of about 900 to 1000 [° C.], and the surface is flattened.

[Connection Hole Forming Step 2] Next, a connection hole 40A is formed in each of the interlayer insulating films 40 and 39. The connection hole 40A is formed in each of the n-type semiconductor region 28, the n ⁺ -type semiconductor region 37, the p ⁺ -type semiconductor region 38 of each element of the DRAM 1, the upper portion (not shown) of the word line 26, and the like. . The connection hole 40A is formed, for example, in the upper interlayer insulating film 40.
The side is formed by performing isotropic etching, and the lower interlayer insulating film 36 side is formed by performing anisotropic etching. That is, the connection hole 40
A is configured so that the step coverage of the upper layer wiring (for example, the complementary data line 50 or the like) is increased to prevent disconnection failure. Further, the connection hole 40A may be formed only by anisotropic etching. Next, the n-type semiconductor region 2 exposed from the connection hole 40A
8. A silicon oxide film (not numbered) is formed on each main surface of the n ⁺ type semiconductor region 37. In the silicon oxide film, B or P added to the interlayer insulating film 40 by heat treatment in a later process (extension and diffusion of impurities for forming the n ⁺ type semiconductor region 41) is changed to a contact hole.
Through 40A, n-type semiconductor region 28, n ⁺ -type semiconductor region 37, p ⁺
It can be prevented from being introduced into each main surface portion of the mold semiconductor region 38. B is introduced into the main surface of the n-type semiconductor region 28 or the n ⁺ -type semiconductor region 37, or P is introduced into the p ⁺ -type semiconductor region 38.
When introduced into the main surface portion, the effective impurity concentration decreases, and the contact resistance value between each semiconductor region and the wiring (50) connected thereto increases. The silicon oxide film 30 has a thickness of 12 to 50 [n
m]. Next, MISFETQs for memory cell selection, n-channel MISFET
In each of the formation regions of Qn and Qo, an n-type impurity is introduced into the respective main surfaces of the n-type semiconductor region 28 and the n ⁺ -type semiconductor region 37 through the connection hole 40A. The n-type impurities pass through the thin silicon oxide film and are introduced into the respective main surfaces. And
By stretching and diffusing this n-type impurity,
As shown in the figure, an n ⁺ -type semiconductor region 41 having a high impurity concentration is formed. The n ⁺ type semiconductor region 41 is a wiring (50) that is passed through the connection hole 40A when the n ⁺ type semiconductor region 28 and the n ⁺ type semiconductor region 37 are displaced from the connection hole 40A due to mask misalignment in the manufacturing process. It is formed to prevent short-circuit between the p ^- type well region 22 and the p ^- type well region 22. The n-type impurity forming the n ⁺ -type semiconductor region 41 is, for example, As having a high impurity concentration of about 10 ¹⁵ [atoms / cm ₂ ] and is introduced by ion implantation at an energy of about 110 to 130 [KeV]. I do. In the memory cell M, the n ⁺ type semiconductor region 41 is formed integrally with one of the n type semiconductor regions 28 of the MISFETQs for memory cell selection, and forms a part of a source region or a drain region. Since the n ⁺ type semiconductor region 41 is formed with a high impurity concentration, it is possible to reduce the contact resistance value with the upper wiring, for example, the complementary data line (50).

[Wiring Forming Step 1] Next, as shown in FIG. 32, n
A wiring 50 connected to the ⁺ type semiconductor region 41, the p ⁺ type semiconductor region 38 and the like and extending on the interlayer insulating film 40 is formed. The wiring 50 is formed in a first-layer wiring forming step in the manufacturing process. wiring
Reference numeral 50 denotes a complementary data line (DL) 50 between the memory cell array 11B and the column address decoder circuit 12 therewith.
Used as The wiring 50 has a three-layer structure in which a transition metal film 50A, an aluminum film (or an alloy film thereof) 50B, and a transition metal film 50C are sequentially laminated. The transition metal film 50A under the wiring 50 is formed of, for example, a WSi ₂ film deposited by a CVD method and has a thickness of about 50 to 200 [nm]. The reaction generation formula of the WSi ₂ film is as follows. The middle aluminum film 50B is deposited by, for example, a sputtering method and has a thickness of about 300 to 600 [nm]. The upper transition metal film 50C is formed of, for example, a MoSi ₂ film deposited by a sputtering method and has a thickness of about 10 to 40 [nm]. The wiring 50 includes a transition metal film 50A, an aluminum film 50B,
After sequentially stacking the transition metal films 50C, processing is performed using a photolithography technique and an etching technique. The processing technique of the wiring 50 and the wiring 53 thereon will be described later in detail.

[Interlayer Insulating Film Forming Step 2] Next, an interlayer insulating film 51 is formed on the entire surface of the substrate including the wiring 50. The interlayer insulating film 51 is a silicon oxide film (deposited insulating film)
It has a three-layer structure in which a silicon oxide film (coated insulating film) 51B, a silicon oxide film (coated insulating film) 51B, and a silicon oxide film (deposited insulating film) 51C are sequentially stacked. The lower silicon oxide film 51A is deposited by a plasma CVD method,
It is formed with a thickness of about 0 to 700 [nm]. The middle silicon oxide film 51B is formed to flatten the surface of the interlayer insulating film 51. The silicon oxide film 51B is applied to a film thickness of about 100 to 150 [nm] on a wide flat pattern by the SOG method, and then subjected to a bake treatment (about 450 [° C]), and the surface is etched back. Is formed.
Due to the recession by the etching, the silicon oxide film 51B is formed only in the concave portion of the step shape on the surface of the lower silicon oxide film 51A. In addition, the lower silicon oxide film is also etched and retreats at the lower step-shaped protrusions of the lower layer due to the retreat by the etching, and the flatness after the silicon oxide film 51B is applied is maintained. Further, the middle layer of the interlayer insulating film 51 may be formed of an organic material film, for example, a polyimide resin film instead of the silicon oxide film 51B. The upper silicon oxide film 51C is deposited by, for example, a plasma CVD method and formed to a thickness of about 500 to 700 [nm] in order to increase the strength of the film as the entire interlayer insulating film 51.

[Connection Hole Forming Step 3] Next, as shown in FIG. 33, a connection hole 52 is formed in the interlayer insulating film 51. The connection hole 52 is an upper connection hole 52B formed by performing isotropic etching on the upper silicon oxide film 51C side of the interlayer insulating film 51, and a lower hole formed by performing anisotropic etching on the lower silicon oxide film 51A side. Each of the side connection holes 52A is formed. After forming the connection holes 52, a heat treatment of about 400 [° C.] is performed in order to recover damage due to etching.

[Wiring Forming Step 2] Next, as shown in FIG. 1, a wiring extending on the interlayer insulating film 51 so as to be connected to the wiring 50 through the connection hole 52.
Form 53. The wiring 53 is formed by a second-layer wiring forming step. As described above, the wiring 53 has a three-layer structure in which a transition metal film 53A, an aluminum film (or an alloy film thereof) 53B, and a transition metal film 53C are sequentially stacked. The lower transition metal film 53A is formed of, for example, a MoS ₂ film deposited by a sputtering method and has a thickness of about 50 to 100 [nm]. The middle aluminum film 53B is deposited by a sputtering method, and is 700 to 700 mm thicker than the aluminum film 50B of the wiring 50.
It is formed with a thickness of about 1000 [nm]. The upper transition metal film 53C is formed of, for example, a MoSi ₂ film deposited by a sputtering method and has a thickness of about 10 to 40 [nm]. The wiring 53 includes a transition metal film 53A, an aluminum film 53B,
After sequentially stacking the transition metal films 53C, processing is performed using a photolithography technique and an etching technique. The processing technique of the wiring 53 will be described later in detail. After the step of forming the wiring 53, heat treatment is performed to recover damage due to etching for processing the wiring 53.

[Passivation film forming process]

Next, as shown in FIG. 1 and FIG.
A passivation film 54 is formed on the entire surface of the substrate including on the surface 53. As described above, the passivation film 54 is formed of a composite film in which a silicon oxide film 54A, a silicon nitride film 54B, and a resin film 54C are sequentially stacked. The passivation film 54
The lower silicon oxide film 54A is formed with a thickness of about 150 to 600 [nm]. The intermediate silicon nitride film 54B is deposited by, for example, a plasma CVD method and is formed to a thickness of about 1.0 to 1.2 [μm]. The upper resin film 54C is formed of, for example, a polyimide-based resin film applied by a coating method and has a thickness of 3 to 12 μm.
m]. Next, in the formation region of the external terminal BP of the DRAM1,
A bonding opening 56 is formed in the resin film 54C above the passivation film 54. This bonding opening 56 is formed using a photolithography technique and an etching technique. Then, thereafter, in the region where the external terminal BP is formed, the middle silicon nitride film 54 of the passivation film 54 is formed.
B, each of the lower silane films 54A is sequentially removed to form a bonding opening 55. This bonding opening 55 is formed by, for example, anisotropic etching. Further, the same manufacturing process as that of forming the bonding opening 55 is used to perform the fifteenth process.
As shown in FIG.
The transition metal film 53C on the upper layer 53 can be removed. By performing these series of steps, the DRAM of this embodiment is
1 is completed. Next, in the above-described manufacturing process of the DRAM 1, the manufacturing process of each main part will be described in detail.

[Gate Wiring Forming Step 2] First, the lower electrode layer 33 of the information storage capacitor C having the stacked structure of the memory cell M shown in FIG. 27 is processed by a chopping etching method. In the chopping etching apparatus, a plurality of branched etching gas supply pipes 72A to 72C are connected to an etching chamber 70 via a control valve 71A, as shown in FIG. The etching chamber 70 is provided with an exhaust pipe 70A. The branched etching gas supply pipe 72A is connected to the control valve 7
1B, a branched etching gas supply pipe configured to supply the etching gas G1 to the etching chamber 70 through each of the mass flow controllers (MFC) 73A.
The etching gas G2 is supplied to the etching chamber 70 through the control valve 71C and the mass flow controller 73B.
Is configured to be supplied. Similarly, the branched etching gas supply pipe 72C is configured to supply the etching gas G3 to the etching chamber 70 through each of the control valve 71D and the mass flow controller 73C. Each of the mass flow controllers 73A to 73C is controlled by a chopping controller (CC) 74. The chopping controller 74 includes an etching gas supply pipe.
The configuration is such that the flow rate of the etching gas flowing in each of 72A to 72C can be alternately controlled. The etching gas G1 flowing through the etching gas supply pipe 72A is an anisotropic etching gas such as a halogen compound (C ₂
Use Cl ₂ F ₄ ). The flow rate of this etching gas G1 is the third
As shown in Fig. 5 (time chart of gas flow rate), it is periodically increased and decreased. The control of the gas flow rate is controlled by the chopping controller 74. As shown in FIG. 38 (a diagram showing the relationship between the etching rate and the taper angle), when the flow rate of the etching gas G1 is increased, the etching anisotropy can be increased. On the other hand, each of the etching gases G2 and G3 flowing through each of the etching gas supply pipes 72B and 72C uses an isotropic etching gas such as a halogen element (SF ₆ ). Etching gas G
The flow rate of 2 is periodically increased and decreased as shown in FIG. 36 (time chart of gas flow rate). The control of the gas flow rate is controlled by the chopping controller 74, and the etching gas G2 is decreased when the flow rate of the etching gas G1 is increased and increased when the flow rate of the etching gas G1 is decreased. As shown in FIG. 38, when the flow rate of the etching gas G2 is increased, the isotropy of the etching can be improved. The flow rate of the etching gas G3 is kept constant as shown in FIG. 37 (time chart of the gas flow rate). The control of the gas flow rate is controlled by the chopping controller 74, and the etching gas G3 flows less than when the flow rate of the etching gas G1 is increased and more than when the flow rate of the etching gas G1 is decreased. As shown in FIG. 38, the etching gas G3 can enhance the isotropy of the etching. In this chopping etching apparatus, the etching gas G1 and the etching gas
As shown in the figure, the polycrystalline silicon film of the lower electrode layer 33 of the information storage capacitor C having the stacked structure is processed by flowing into the etching chamber 70. That is, the polycrystalline silicon film is processed by alternately and repeatedly performing anisotropic etching and isotropic etching. This etching is repeated at a high speed of 1 second or less. When the etching is repeated at a high speed, an organic polymer adheres to the side wall of the polycrystalline silicon film while the polycrystalline silicon film is being etched by anisotropic etching, and the organic polymer is anisotropic again before the organic polymer is destroyed by isotropic etching. An organic polymer can be newly attached by performing etching. Since the organic polymer acts as a stopper layer for side etching based on isotropic etching, the anisotropy of etching can be increased even during isotropic etching. Usually, when the polycrystalline silicon film is etched by anisotropic etching, an etching residue occurs particularly at a step portion on the base surface, so that it is about 500
Although overetching of about [%] is performed, by using the chopping etching method, it is possible to secure the anisotropy of etching while removing the etching residue by isotropic etching. Specifically, about 10% of the total flow rate of the etching gas
An etching gas G1 of about [%] shows extreme anisotropy, and an etching gas G2 of about 30% shows extremely isotropic property. According to the experimental results of the inventor, about 100 to 1
An etching residue can be removed with an over-etching amount of about 50%. Further, the chopping etching method may be performed by combining the etching gas G3 (gas flow rate is constant) and the etching gas G1 (gas flow rate periodically increases and decreases). As described above, the DRAM for patterning the polycrystalline silicon film (lower electrode layer 33) formed on the surface of the base (interlayer insulating film 31) having the (43-24) step shape by anisotropic etching.
In the first forming method, the polycrystalline silicon film is patterned by alternately and repeatedly performing anisotropic etching and isotropic etching. With this configuration, it is possible to reduce the etching residue on the surface of the step-shaped portion of the base by isotropic etching while securing the anisotropy of the etching during the patterning of the polycrystalline silicon film. And damage or destruction of the underlying surface can be prevented. (45-25) The anisotropic etching is performed again before the organic polymer attached to the patterned side surface of the polycrystalline silicon film is destroyed by the isotropic etching. With this configuration, since the organic polymer generated by the anisotropic etching acts as a stopper layer for isotropic etching, the amount of side etching in isotropic etching can be reduced, and the anisotropy of etching can be increased. . (Claim 46) In the chopping etching apparatus, an etching chamber (etching chamber) 70 is provided, and the etching chamber 70 includes a mass flow controller 73A.
A gas supply system for supplying the anisotropic etching gas G1 with the interposition thereof, and a gas supply system for supplying the isotropic etching gas G2 or G3 with the mass flow controller 73B or 73C provided, respectively, the mass flow controller 73A, A chopping controller 74 for alternately and repeatedly controlling the gas supply amount flowing to each of the mass flow controllers 73B and 73C is provided. With this configuration, the chopping etching method can be realized. Further, in the chopping etching method, since each of the anisotropic etching gas G1, the isotropic etching gas G2 or G3 is continuously and repeatedly flown, there is no exhaust treatment, and the etching time is greatly reduced. Can be. Note that this chopping etching method is not limited to the polycrystalline silicon film of the lower electrode layer 33, and each of the gate electrode 26 of the MISFETQs for memory cell selection and the upper electrode layer 35 of the information storage capacitor C having a stacked structure. Can be applied to the polycrystalline silicon film. Further, the chopping etching method can be applied to the wirings 50 and 53 mainly composed of an aluminum film. In this case, the anisotropic etching gas G1 is C
Use F ₄ , CHF ₃ , CClF ₃ or the like. Isotropic Etching Gas G2
Used is Cl ₂ or G3 is BCl ₃ or the like.

[Gate Wiring Forming Steps 1, 2, 3] The memory cell selecting MI of the memory cell M shown in FIG.
The gate electrode 26 (including the word line 26) of the SFETQs, the lower electrode layer 33 of the information storage capacitor C having the stacked structure of the memory cell M shown in FIG. 27, and the information storage capacitor having the stacked structure shown in FIG. Each of the upper electrode layers 35 of the element C is processed by low-temperature anisotropic etching. First, DRAM1 (semiconductor wafer before dicing process)
Is directly adsorbed to the lower electrode in the etching chamber via an electrostatic attraction plate. This lower electrode is constantly cooled,
As a result, the semiconductor wafer is kept at a temperature lower than the normal temperature. In this state, the gate electrode 26, the lower electrode layer 33, or the upper electrode layer 35 can be formed by performing anisotropic etching and processing the polycrystalline silicon film into a predetermined shape. Since a large amount of anisotropic etching gas (halogen compound C ₂ Cl ₂ F ₄ ) is deposited on the surface of a semiconductor wafer having a lower temperature than the inner wall of the etching chamber, the use of low-temperature anisotropic etching is based on the anisotropic etching gas. Can be reduced, and contaminants adhering to the inner wall of the etching chamber can be reduced.

[Wiring Forming Steps 1 and 2] The wiring 50 shown in FIG. 32 and the wiring 53 shown in FIG.
Each is shown in Fig. 39 (schematic diagram of the device)
Processing-ashing processing-wet processing-drying processing
Use a continuous processing device that performs
You. The continuous processing device 80 shown in FIG.
Room 81, load room 82, etching room 83, ashing room 84,
Unloading room 85, rinsing room 86, bake drying room 87
Are provided in series. Load chamber 82, etching chamber
83, ashing room 84, unloading room 85
Buffer room (in the same vacuum system) 80A shielded from the atmosphere
Are located in Buffer chamber 80A is, for example, 10^-3~Ten^-6
A degree of vacuum of [atmospheric pressure] is maintained. Load in the loading / unloading chamber 81 of the continuous processing unit 80
The cassette 81A is configured to be detachably mounted.
I have. This load cassette 81A is an unprocessed semiconductor wafer.
It is configured so that a plurality of C 100 can be stored. Low
The semiconductor wafer 100 stored in the cassette 81A is for transport
A robot placed in the buffer chamber 80A with the arm 88A interposed
Transported to the load chamber 82. The semiconductor wafer 100 transferred to the load chamber 82 is
Transported to the etching chamber 83 with the intervening arm 88B.
It is. The etching chamber 83 is designed for photolithography
Etching mask (photoresist film)
Using an anisotropic etching method (or the chopping
The wiring 50 or 53 is formed by etching.
As the anisotropic etching gas, a halogen compound (BCl_Three
+ CF_Four) And halogen elements (Cl_Two) Use mixed gas
You. The etching chamber 83 has, for example, 10^-1~Ten^-3
The degree of vacuum is about [atmospheric pressure]. The semiconductor which has been subjected to the etching process in the etching chamber 83
The body wafer 100 can be swung without opening to the atmosphere.
Transported to the ashing chamber 84 via the arm 88C.
You. The ashing chamber 84 is provided with the etching mask (photo
Resist compound) to a halogen compound (CF_FourOr CHF_Three) And acid
Element (O_Two). Ashing room 84 is an example
For example, 2-10^-1In a state where the degree of vacuum is maintained at [atmospheric pressure]
Ashing process at a temperature of about 25 to 200 [° C]
Is performed. The semiconductor wafer subjected to the ashing process in the ashing chamber 84
The AHA 100 is unloaded with the swing arm 88C interposed.
Transport chamber 85. Semiconductor transported to unload chamber 85
The body wafer 100 is washed with a transfer arm 88D.
Transported to 86. This washing chamber 86 and the subsequent baking
The drying chamber 87 is located outside the buffer chamber 80A (the continuous processing device 80).
Inside) and maintained at atmospheric pressure. The rinsing chamber 86 is a chamber generated by the etching process.
Rogen element (Cl_Two). This haloge
The element in the atmosphere outside the continuous treatment device 80, especially H_TwoTouch O
Then, the aluminum film (or its alloy film) 50B of the wiring 50
Or the aluminum film (or its alloy film) 53B of the wiring 53
Corrodes exposed surfaces. After the washing process,
The semiconductor wafer 100 is transferred to the bake drying chamber 87 by the transfer arm 88E.
And dried in the bake drying chamber 87. Bake
When the drying process is completed, the semiconductor wafer 100 is unloaded.
Stored in the cassette 81B. The semiconductor wafer stored in the unload cassette 81B
The wafer 100 is cleaned by a device different from the continuous processing device 80.
Each of a treatment, a drying treatment, and an inert treatment is performed. Washing
The cleaning process is to remove foreign matter after etching and aluminum
The aluminum film 53B of the wiring film 50B or the wiring 53 is exposed.
Side film attached to the surface (for example, containing Al etc.
This is a process for removing the compound thin film. This cleaning process is
This is performed using a potash washing solution or an acid washing solution. The drying process is
Drying after washing. The inert treatment is performed by using the aluminum
For forming an oxide film on the exposed surface of the film 50B or 53B.
Reason. In this way, the (28-16) anisotropic etching
Pattern the minium film (or its alloy film) 50B or 53B
In the method of forming a DRAM 1 to be
A film 50B or 53B is deposited, and an etching mask is formed on this surface.
(Photoresist mask) forming process and halogen
Anisotropy using elements and halogen compounds as etching gas
Using etching, before in vacuum system (in buffer chamber 80A)
The aluminum film 50B or 53B has a predetermined patterning.
In the same vacuum system as in the anisotropic etching step
The etching mask with a halogen compound and oxygen gas.
Removing by ashing using
Shields chlorine generated during the etching process from the atmosphere outside the equipment
Washing in the set system and thereafter drying.
You. With this configuration, the ashing process is performed by an etching process.
The same anisotropic etching process is performed in the same vacuum system as
Rinse treatment performed in a system where the generated chlorine is shielded from the atmosphere
(86) so that the aluminum
Corrosion of the film 50B or 53B can be reduced. In addition, each of the wirings 50 and 53 is shown in FIG.
Etching process-low-temperature ashing process shown in configuration diagram)
-A continuous process that consistently and continuously processes each of the vacuum bake processes
Processing using a processing device. The continuous processing device 80I shown in FIG.
Chamber 81, load chamber 82, etching chamber 83, low-temperature ashing
Chamber 84A, nitrogen gas blow vacuum bake chamber 89, unload chamber 8
Each of the five is provided in series. Load room 82, edge
Ching room 83, low temperature ashing room 84A, nitrogen gas blow true
Empty bake room 89 and unload room 85 each have buffer room 80A
Are located in The semiconductor wafer 100 subjected to the etching process is
Low temperature ashing chamber 84A with swing arm 88C interposed
Conveyed. The low-temperature ashing chamber 84A is
Placed in the buffer chamber 80A in the same vacuum system as at room temperature
Perform ashing at low temperatures (approximately 20 ° C)
Is going. This ashing is performed in the same manner as described above.
Etching mask with mixed gas of oxygen compound and oxygen
This is the process of removing. Low-temperature ashing process
Aluminum film 50B of 50 or aluminum film 53B of wiring 53
In the side film attached to the side of the resist and the side of the resist
Al is oxidized and Al_TwoO_ThreeIn the low-temperature region where
This is a shing process. Semiconductor wafer 10 subjected to the low-temperature ashing process
0 is nitrogen gas blow vacuum with swing arm 88C interposed
It is transported to the bake chamber 89. This nitrogen gas blow vacuum
Chamber 89 is heated by a hot plate or heating lamp.
The surface of the wafer 100 is heated to about 200 to 400 [° C.]
To reduce halogen elements generated by etching
Is configured. Also, nitrogen gas blow vacuum bake chamber
89 is high purity nitrogen during heating of the semiconductor wafer 100.
Gas (N_Two: Dew point -60 [° C] or less) as carrier gas
It reduces the flow of air and oxygen. After the vacuum baking process, a washing process,
Each of the drying process and the inactive process is sequentially performed. In this way, (26-15) anisotropic etching
DRAM1 shape for patterning the minium film 50B or 53B
In the forming method, the aluminum film 50B or 53B is deposited.
And forming an etching mask on the surface;
Use halogen elements and halogen compounds as etching gas
The aluminum foil in a vacuum system using anisotropic etching
Performing a predetermined patterning on the film 50B or 53B;
In the same vacuum system as in the anisotropic etching step,
Chamber using a halogen compound and oxygen gas
Removing by low-temperature ashing below the temperature;
The predetermined patterning in the same vacuum system as the shing process
Baked aluminum film or its alloy film
Performing a process. With this configuration, the above
Singing process at low temperature and same vacuum system as etching process
Because it is performed inside, the side wall of the aluminum film 50B or 53B
And Al in the side film attached to the side of the resist
Al_TwoO_ThreeCan be reduced, and the side film can be removed
It becomes easy and vacuum from the anisotropic etching process.
In the same vacuum system without opening to the atmosphere until baking
And chlorine generated in the anisotropic etching process
Can be reduced by vacuum baking,
Corrosion of the Luminium film 50B or 53B can be reduced
You. Also, each of the wirings 50 and 53 is shown in FIG.
Etching process-low-temperature ashing process shown in configuration diagram)
-Vacuum bake treatment-Cleaning treatment-Inert treatment
Using a continuous processing device for continuous processing. The continuous processing device 80II shown in FIG.
Chamber 81, load chamber 82, etching chamber 83, low-temperature ashing
Chamber 84A, nitrogen gas blow vacuum bake chamber 89, unload chamber 8
5, each of the cleaning processing room 90 and the inert processing room 91 are provided in series.
I have. That is, the continuous processing device 80II
The device 80I and the process for performing the processes after the process performed by the device 80I
It is configured in combination with a control device. As mentioned earlier,
The cleaning chamber 90 is different between acid and alkali cleaning solutions or acid cleaning solutions.
It is configured to remove objects and side films.
The inert processing chamber 91 is provided on the surface of the aluminum film 50B or 53B.
This is a process for forming an oxide film on the substrate. Further, the ashing process or the low-temperature ashing process
Is a halogen compound (CF_Four) And oxygen
It is done with joint gas. Oxygen removes etching mask
Halogen compound is used in the etching mask.
Has the effect of increasing the speed of removal. Surface of the wiring 50
Thin transition metal film 50C, thin on the surface of wiring 53
Each of the transition metal films 53C having a thickness is provided.
In the ashing process using a combined gas, the transition metal
Remove each of the metal films 50C and 53C by overashing.
Would. Therefore, in this embodiment, the ashing
The processing or the low-temperature ashing processing is performed by using the transition metal film 50 of the wiring 50.
C or the above until the surface of the transition metal film 53C of the wiring 53 is exposed.
Ash with a mixed gas (just ashing)
After that, overashing is performed only with oxygen gas. (Embodiment II) This embodiment II is a modification of the DRAM 1 of the embodiment I.
According to the present invention, the area of the recell M is reduced and the degree of integration is improved.
This is a second embodiment. Example 2 of a DRAM memory cell array according to Embodiment II of the present invention.
The surface structure is shown in FIG. 42 (plan view of main part). The DRAM 1 of the present embodiment II has a memory
One n-type semiconductor of MISFETQs for memory cell selection of cell M
Connection hole 40 connecting region 28 and complementary data line (DL) 50
B is connected to the upper layer of the stacked information storage capacitor C.
It is formed in self-alignment with the pole layer 35. The connection hole 40
In B, each of the complementary data line 50 and the upper electrode layer 35
Is a separation insulating film (35 not shown in FIG. 42).
A) is electrically isolated. Next, a specific method of manufacturing the DRAM 1 will be described with reference to FIG.
To 45 (memory cell array shown for each predetermined manufacturing process)
A brief explanation using (a) a cross-sectional view of the main parts of CMOS of peripheral circuits
I will tell. First, similar to the step shown in FIG.
Of the information storage capacitor C having the stacked structure of the memory cell M
After depositing a polycrystalline silicon film for forming the upper electrode layer 35,
Etching mask 67A is formed on the polycrystalline silicon film.
The etching mask 67A is shown in FIG. 29 of the embodiment I.
Unlike the etching mask 67, the memory cell M and the complementary
Memory cell array 11B that matches the connection area with the data line (50)
Is formed so as to cover the entire area. Thereafter, using the etching mask 67A, the peripheral circuit
Region of the polycrystalline silicon film, the dielectric film 34, the interlayer insulating film 31
Are sequentially etched, as shown in FIG. 43.
Thus, upper electrode layer 35 is formed. This upper electrode layer 35
The information storage capacity of the stacked structure
The quantity element C is substantially completed. Next, as shown in FIG. 44, the surface of the upper electrode
An insulating film 36 is formed on the entire surface of the substrate including the upper surface.
The edge films 39 and 40 are sequentially laminated. Next, it is complementary to the memory cell M in the memory cell array 11B.
In the connection region with the conductive data line (50), the interlayer insulating film 4
0, 39, the insulating film 36, and the upper electrode layer 35 are sequentially etched.
Then, a part of the connection hole 40B is formed. This d
The etching is performed, for example, by anisotropic etching (or isotropic etching).
And the dielectric film 34 (or
Uses the interlayer insulating film 31) as an etching stopper layer.
You. Next, the dielectric film 34 exposed from a part of the connection hole 40B
(Especially silicon nitride film 34A) as an oxidation resistant mask.
The surface of the upper electrode layer 35 exposed on a part of the inner wall of the connection hole 40B.
The surface is oxidized to form the isolation insulating film (silicon oxide film) 35A.
You. This isolation insulating film 35A is, for example, at least 100 [nm].
It is formed with a film thickness of about. After this, one of the connection holes 40B
Each of the dielectric film 34 and the interlayer insulating film 31 exposed from the portion is sequentially
By etching, connect as shown in Figure 45
Hole 40B is completed. Further, the isolation insulating film 35A is made of a dielectric material.
Do not use body film 34 as an oxidation resistant mask (depending on conditions,
(Removed during etching)
It may be formed. Next, as in Example I, n⁺Replaces the type semiconductor region 41
To form complementary data lines 50 and other wiring 50
I do. Subsequent manufacturing steps are the same as in Example I.
Therefore, the description is omitted here. The memory cell M of the DRAM 1 according to the first embodiment stores the complementary data.
Connection hole 40B for connecting the data line 50 and a MISFE for selecting a memory cell.
TQs gate electrode 26, stacked information storage capacitor
In the manufacturing process between each of the upper electrode layers 35 of the device C
Alignment margin is secured. The upper electrode layer 35 is the lower layer
To ensure a margin between the lower electrode layer 33 and
The lower electrode layer 33 is formed between the lower electrode layer 33 and the lower gate electrode 26.
The extra margin dimensions are secured. However, the DR of Example II
In AM1, each of the connection hole 40B and the upper electrode layer 35 is self-aligned.
, So it is equivalent to the alignment margin between the two.
By reducing the area of the memory cell M and improving the degree of integration.
Can be. (Embodiment III) The present embodiment III is a modification of the DRAM 1 of the embodiment I.
Improves the amount of charge stored in the capacitor C for information storage with a locked structure
To reduce the memory cell area, and
A third embodiment of the present invention with increased step coverage
You. A memory cell array and a DRAM according to Embodiment III of the present invention.
FIGS. 46 to 50 (places)
Brief description using the main part cross-sectional views shown for each fixed manufacturing process)
I do. First, similar to the step shown in FIG.
The gate electrode (26) and the entire surface of the substrate including the gate insulating film 25
Polycrystalline silicon film used as word line (26), interlayer insulation
Each of the edge films 27C is sequentially laminated. The interlayer insulating film 27C is
Increases the amount of charge stored in the information storage capacitor C with a locked structure
For example, a film having a thickness as large as about 600 [nm] is formed.
You. As the interlayer insulating film 27C, inorganic silane
Deposited by CVD method using gas and nitrogen oxide gas as source gas
You. Next, the MISFE for selecting the memory cell of the memory cell array 11B
TQs, n-channel MISFETQn of peripheral circuit, p-channel MISFE
In each formation region of TQp, the interlayer insulating film 27C
Then, an interlayer insulating film 27 having a small film thickness is formed.
The interlayer insulating film 27 is etched to a thickness of, for example, about 300 [nm].
To run. Next, as shown in FIG. 46, the interlayer insulating films 27, 27
C, each of polycrystalline silicon film is sequentially anisotropically etched.
Etching to form gate electrode 26 and word line 26 respectively
I do. As shown in FIG. 46, the MISFET for selecting a memory cell
Qs, n-channel MISFETQn and p-channel MISFETQp
On the gate electrode 26, a thin interlayer insulating film 27 is formed. one
On the other hand, a thick interlayer insulating film 27C is formed on the word line 26.
You. Next, as shown in FIG. 47, the n-type semiconductor region 28, the p-type
Each of the semiconductor regions 30 is formed. Form n-type semiconductor region 28
MISFETQs for memory cell selection are almost completed
I do. Next, as shown in FIG. 48, the side wall of the gate electrode 26 is formed.
And sidewalls on the side walls of the interlayer insulating film 27 thereover.
Pacer 29, the side wall of the word line 26 and the interlayer insulating film 27C
Each of the side wall spacers 29A is formed on the side wall. Next, the entire surface of the substrate including each of the interlayer insulating films 27 and 27C
Then, an interlayer insulating film 31 is formed, and thereafter, as shown in FIG.
Then, connection holes 31A and 32 are formed in the same manner as in Example I.
You. Next, as shown in FIG.
In the above, interlayer insulating films 27, 27
Stacked structure information stretched on top of each of C
The lower electrode layer 33 of the storage capacitor C is formed. Fig. 50
As shown in the figure, the lower electrode layer 33 is formed above the word line 26.
And the area is increasing in the height direction.
Increasing the amount of charge stored in the information storage capacitor C
Can be. In addition, the lower electrode layer 33 is located above the gate electrode 26.
Reduced step shape (reduced aspect ratio)
Connection between the complementary data line 50 and the memory cell M
Step coverage of the complementary data line 50 in the region
Can be improved. Further, the lower electrode layer 33 is formed as described above.
The charge accumulation amount can be increased as
Thinner, simplifying introduction and processing of n-type impurities
can do. After the step of forming the lower electrode layer 33, the embodiment
Since it is the same as I, the description here is omitted. Thus, the (37-20) complementary data line 50 and word line 2
Memory cell M is arranged at the intersection with
MISFETQs for memory cell selection and information on the stacked structure
DRAM1 composed of a series circuit with the information storage capacitor C
Information storage in the stacked structure of the memory cell M.
The lower electrode layer 33 of the capacitive element C is
Gate electrode 26 and its gate width of MISFETQs for memory cell selection
Word line 26 for selecting another memory cell M adjacent in the direction
And the lower electrode layer 33
The interlayer insulating film 27C between the
Compared with the interlayer insulating film 27 between the pole layer 33 and the gate electrode 26.
And make it thicker. With this configuration, the lower electrode layer 33
Increase the thickness of the interlayer insulating film 27C between the word line 26 and the lower electrode
Since the step of the layer 33 is increased, the area of the lower electrode layer 33 is increased.
Information storage capacitor C having a stacked structure
And the charge storage amount of the lower layer can be increased.
The interlayer insulating film 27 between the electrode layer 33 and the gate electrode 26 is thinned
Between the MISFETQs for memory cell selection and the complementary data line 50
Since the step at the connection part has been lowered,
Reduces the ratio of the ratio and reduces the disconnection failure of the complementary data line 50.
Can be reduced. As a result, α-ray soft error
And increase the integration of DRAM1.
In addition, the electrical reliability of the DRAM 1 can be improved. Each of the interlayer insulating films 27 and 27C is formed in a separate process.
The insulating film may be formed. (Embodiment IV) The present embodiment IV is a modification of the DRAM of the above-described embodiment I.
Lower layer capacitor of information storage capacitor C having stacked cell structure
The thickness of the pole layer is increased to increase the amount of accumulated electric charge.
This is the fourth embodiment. Cross-sectional structure of DRAM memory cell according to Embodiment IV of the present invention
Are shown in FIGS. 51 to 54 (cross-sectional views of main parts). The memory cell M of the DRAM 1 shown in FIG.
The thickness of the lower electrode layer 33 of the information storage capacitor C is increased.
Make up. For example, the lower electrode layer 33
Part is securely embedded and its surface is substantially flattened.
It is formed with a film thickness of a certain degree or more. example
For example, the opening size L of the connection hole 32 (the gate electrode 26 and the word line 26
Is about 1.0 [μm], the lower electrode
The film thickness T of the layer 33 is about 500 [nm] or more.
(T ≧ 1/2 × L). The information storage capacity of the stacked structure thus configured
The element C increases the area of the end face of the lower electrode layer 33,
Since the amount of charge stored at the end face can be increased,
Reducing the area of the cell M and improving the integration of the DRAM1
Can be. The memory cell M of the DRAM 1 shown in FIG.
Connection hole for the lower electrode layer 33
32 is formed with the film thickness just before it is buried. The information storage capacity of the stacked structure thus configured
Since the thickness of the lower electrode layer 33 is large to some extent,
It is possible to increase the charge storage amount at the end face of the lower electrode layer 33.
Along the steps of the connection holes 32 and 31A.
The layer electrode layer 33 is formed, and the height direction corresponds to the step.
The area of the lower electrode layer 33 can be increased in
Load accumulation can be increased. In other words, the stack
Increase in the amount of charge stored in the information storage capacitive element C having a dark structure
Reduces the area of the memory cell M and improves the integration of the DRAM1.
Can be up. The memory cell M of the DRAM 1 shown in each of FIGS. 53 and 54
Is the lower electrode of the stacked information storage capacitor C
The layer 33 is composed of a plurality of layers. Stack shown in Figure 53
The lower electrode layer 33 of the information storage capacitor C having the
It has a two-layer structure in which each of the extreme layers 33E and 33F is laminated.
You. The lower electrode layer 33 is a polycrystalline layer forming the lower electrode layer 33E.
After depositing silicon film, thermal diffusion method or ion implantation of n-type impurity
And then forming the lower electrode layer 33F
After depositing a silicon film, an n-type impurity is similarly introduced, and thereafter,
Formed by processing each polycrystalline silicon film.
You. In other words, the lower electrode layer 33 becomes undesirably thicker.
Divided into multiple layers as it becomes difficult to control the distribution of the concentration of pure substances
Then, an n-type impurity is introduced into each of the divided layers,
The impurity concentration distribution is uniformed. Shown in Figure 54
Lower electrode layer of stacked information storage capacitor C
33 similarly laminates each of the lower electrode layers 33F, 33F and 33G.
It has a three-layer structure. The information storage capacity of the stacked structure thus configured
The element C makes the distribution of the impurity concentration of the lower electrode layer 33 uniform.
Can be (Embodiment V) This embodiment V is different from the DRAM of the embodiment I in that
MISFETQs for cell memory cell selection, n-channel MISFETQn
Example 5 of the present invention in which the narrow channel effect of
You. The DRAM 1 according to the embodiment V of the present invention is different from the DRAM according to the embodiment I in the second embodiment.
P-type impurity (channel stopper region 24A is formed) shown in FIG.
Impurity) is introduced by high-energy ion implantation.
You. The energy amount of the ion implantation method is about 100 to 150 [KeV]
Do it in degrees. Introduced by this ion implantation method using high energy
The introduced p-type impurity 24p is used for isolation between elements at the time of its introduction.
The maximum peak value of the impurity concentration is located deeper than the insulating film 23.
Have. When introducing the p-type impurity 24p,
(62) etching mask (photoresist
Film). The p-type impurity 24p is made of silicon oxide.
Penetrate through the base film 60A, n^-Introduced into the main surface of mold well region 21
When the p-type impurity 24p is introduced, n^-
An impurity introduction mask such as a flash is formed on the main surface of the mold well region 21.
A photoresist film is formed. Introduction of this p-type impurity 24p
Thereafter, similarly to the above-described Example I, the insulating film for element isolation 23 is removed.
The p-type impurity 24p is diffused together with the formation.
Of the p-type channel stopper region 24A and the p-type semiconductor region 24B.
Form each. Thus, in the method of manufacturing the DRAM 1, the p-type channel
P-type impurity 24p that forms the stopper region 24A with high energy
It is introduced by the ion implantation method of gi. With this configuration, p
Type impurity 24p^-Introduced into the deep region of the mold well region 22,
Reduction of lateral diffusion during formation of device isolation insulating film 23
So that p^-Well region 22 especially channel
Select memory cells by suppressing the increase in impurity concentration in the formation region
MISFETQs for n-channel and MISFETQn for n-channel
Can reduce the effect. Further, the p-type impurity
24p to p^-Introduced into the deep region of the mold well region 22,
During the formation of the separation insulating film 23, the p-type impurity 24p is eaten by it.
The p-type channel strike.
The impurity concentration of the gate region 24A is increased, and the threshold voltage of the parasitic MOS is increased.
Pressure to increase the separation between elements.
You. (Embodiment VI) The present embodiment VI is a modification of the DRAM 1 of the embodiment I.
In the present invention, the upper resin film of the passivation film is divided.
Six examples. A semiconductor wafer forming a DRAM according to the embodiment VI of the present invention.
The plan structure of C is shown in FIG. 55 (plan view of the main part). As shown in FIG. 55, the semiconductor wafer 100
A plurality of DRAMs 1 of Example I are arranged in a matrix. Id 55
The semiconductor wafer 100 shown in the figure is in a state before the dicing process
Is shown. Each DRAM1 has a scribe area (daisy
Area) is placed in the area defined by 100A
ing. On the surface of each DRAM 1 placed on the semiconductor wafer 100
Is the upper layer of the passivation film 54 described in the first embodiment.
Resin film (for example, polyimide resin film) 54C is applied
ing. This resin film 54C is used for the scrubbing of the semiconductor wafer 100.
Area corresponding to the external area BP of each DRAM1
Area is not applied and on the surface of each DRAM1
And is divided into a plurality. Resin film 54C is α ray soft
Since it is applied for the purpose of increasing the error withstand voltage, memory
Cell array 11A and sense amplifier circuit (SA) 13, column
Address decoder circuit (YDEC) 12 line α line soft error resistance
Is applied to a part of the direct peripheral circuit to secure the pressure.
You. In other words, the resin film 54C has the α-ray soft error withstand voltage.
Other parts of the direct peripheral circuit and indirect peripheral that do not need to secure
A region on the circuit is a divided region. The direct peripheral circuit
The other part is the row address decoder circuit (XDEC) 14,
There is a word driver circuit (WD) 15 and the like. With indirect peripheral circuits
For example, there are a clock circuit and a buffer circuit. This tree
By dividing the oil film 54C, the lower passivation
Film such as the silicon nitride film 54B of the
It can reduce the stress acting on c100 itself.
Wear. The method for forming the resin film 54C is as follows. First, a resin film is applied on the surface of the underlying silicon nitride film 54B.
Then, a first baking process is performed. This baking process
For example, after applying 80 to 90 [° C] and 800 to 1000 [seconds],
Degree, for example, 120-140 [℃], 800-1000 [seconds]
I have. Next, photolithography technology and etching technology
Used, scribe area 100A of resin film and external terminal BP
And the divided regions are removed. Then, the second baking treatment is performed again on the resin film.
Then, the above-described resin film 54C is formed. This baking process
Applied 150 to 200 [° C] and 800 to 1000 [seconds], for example.
Then, again, for example, 300 to 400 [° C] and 800 to 1000 [seconds]
I am giving. In the second baking process, the resin film
54C is the stress acting on the lower layer and the semiconductor wafer 100
Is the largest, but the resin film 54C is divided
Thus, the stress is reduced. The semiconductor wafer 100 was subjected to a dicing process.
However, when DRAM1 is made into individual semiconductor chips,
As shown in FIG. 55, the area where the resin film 54C is applied is also
There is no change in the area (divided area). Thus, (38-21) p^-Main surface of the semiconductor substrate 22 (also
Is the memory cell arranged on the main surface of the semiconductor wafer 100)
Information writing operation and information reading of array 11A and memory cell M
Between the direct peripheral circuit that directly controls the output operation and the rest
DRAM1 with resin film 54C coated on the surface of the contact peripheral circuit
Then, the resin film 54C is divided into a plurality. With this configuration
And the p^-Type semiconductor substrate 20 (or semiconductor wafer 10
0), stress based on the difference between the respective linear expansion coefficients of the resin film 54C
So that p^-Of semiconductor substrate 20
And cracks on the film on its main surface
be able to. The resin film 54C is in a half before the dicing step.
To be applied and baked when the conductor wafer is 100
Formed during the probe test.
Reduces poor needle contact and increases reliability of wafer inspection process
In addition, the yield can be improved. Also, (40-22) the DRAM 1 before the scribe step
Semiconductor wafer 10 in which a plurality of formation regions are arranged in a matrix
Process of applying a resin film 54C over the entire surface of the
Between the regions where the DRAMs 1 are formed on the oil film 54C (the scribe area 100
A) and the area of the external terminal BP is removed, and the DRA
Dividing the resin film 54C on the M1 formation region;
Scribing the scribe area 100A of the conductor wafer 100
Forming a plurality of DRAMs 1. This structure
The step of dividing the resin film 54C is performed by the semiconductor
The scribe area 100A of the wafer 100 and the external terminal BP
It can be performed in the step of removing the resin film 54C in the region.
This corresponds to a step of dividing the resin film 54C.
Accordingly, the number of steps for forming the DRAM 1 can be reduced. (Embodiment VII) The present embodiment VII differs from the DRAM of the embodiment I in that
The seventh embodiment of the present invention in which the number of address decoder circuits is reduced.
This is an example. Example VII of the DRAM memory cell array
Fig. 56 (plan view of main part) and Fig. 57 (predetermined product)
(Plan view of main part in manufacturing process). Column address decoder shown in DRAM1 of Embodiment I
When reducing the number of circuits (YDEC) 12 to be arranged, as shown in FIG. 56
Column select signal line (YSL) 50 is arranged
You. Column select signal line 50 is a column address decoder
Circuit 12 controls n-channel MISFETQy for column switch
It is configured to control. N-cha for column switch
Flannel MISFETQy has complementary data line 50, common data line I / O
Are connected to each other. Column selection
Signal line 50 is used for information write operation speed and information read operation.
Use low-resistance wiring material for the purpose of speeding up and
Same as complementary data line 50 to reduce the number of manufacturing steps
It is formed of a conductive layer (same manufacturing process). Arrangement of n-channel MISFETQy for column switch
Basically, one set of complementary data lines 50
On the other hand, one column select signal line 50 is arranged.
You. The DRAM 1 of this embodiment has two sets of complementary data lines (four data lines).
Data lines DL, ▲ ▼), one for each 50. Through
Usually, one set of complementary data lines of two sets of complementary data lines 50
Dummy between the data line 50 and another set of complementary data lines 50
A column select signal line is provided. Dummy column
The select signal line is the complementary data line 50 in this area.
Of the complementary data lines 50 is reduced.
They are arranged to make the spacing uniform. That is, the photo
An etching mask (for example,
When forming a dist film,
Due to the diffraction phenomenon at the time of exposure, the etching
Disk size is reduced, but dummy column select signals
Lines are located to reduce this phenomenon. this
Stacked structure as the target etching mask
Lower electrode layer 33 of information storage capacitor C, complementary data
A mask for processing the line 50 or the shunt word line 53
You. However, the DRAM 1 of this embodiment has such a phenomenon.
Since it can be ignored, delete the dummy column select signal line.
ing. The column select signal line 50 is a dummy column select.
Like the signal lines, increase the spacing between the complementary data lines 50.
You. In particular, a memory cell near the column select signal line 50
Of the information storage capacitor C having a stacked structure of
The pole layer 33 is a capacitor element for storing information of other stacked structure.
The size (large charge) is larger than that of the lower electrode layer 33 of the child C.
Accumulation amount). That is, the lower electrode layer 33
The case where the dummy column select signal line is arranged
Since the same phenomenon occurs, the amount equivalent to the size reduction,
It has a large size in advance. This lower electrode layer 33
Is drawn below the column select signal line 50 in the plane direction.
Size increased by stretched (crossed) protrusions 33H
It has a large configuration. That is, the protrusion 33H is
Can be formed within the area occupied by the rect signal line 50.
In this way, the degree of integration of DRAM1 is improved by sharing this occupied area.
can do. The lower electrode layer 33 having a small size is used for an information reading operation.
Is possible and the minimum that can secure the α-ray soft error withstand voltage
It is configured such that a limited amount of charge can be obtained. this
On the other hand, the lower electrode layer 33 having a large size
At least the minimum
It is configured so that the charge storage amount can be obtained. This lower layer
There is no particular problem for the electrode layer 33 having a large size. did
Therefore, the DRAM 1 of the present embodiment has different sizes of lower layers.
For storing information of two types of stacked structures with electrode layer 33
The capacitive element C is arranged. Thus, (35-19) complementary data line 50 and word line 2
At the intersection with 6, MISFETQs for memory cell selection and stacked
Memo consisting of a series circuit with an information storage capacitive element C
A recell M is arranged and a phase is set for each of the two sets of complementary data lines 50.
The same conductive layer as the complementary data line 50 and extends in the same direction
A DRAM 1 extending a column select signal line 50,
Complementary data line adjacent to the column select signal line 50
50 of the memory cells M connected to one of the data lines.
Lower electrode layer 33 of information storage capacitor C having a stacked structure
Is the information storage capacity of the stacked structure of the other memory cells M
The device C has a larger size than the lower electrode layer 33.
You. With this configuration, the column select signal line 50 is arranged.
Dimension spread between complementary data lines 50 corresponding to the placement
The etching mask for processing the lower electrode layer 33 is based on
Because the size is reduced by the diffraction phenomenon during exposure, before
One data line adjacent to the column select signal line 50
For storing information of stacked structure of connected memory cells M
Since the size of the lower electrode layer 33 of the capacitive element C has been increased,
This lower electrode layer 33 is reduced to a size equal to or smaller than the set value.
Of the information storage capacitive element C having a stacked structure.
The charge storage amount can be secured. As a result,
And the area of the memory cell M is reduced.
Can increase the integration of DRAM.
Wear. (Embodiment VIII) The present embodiment VIII is a modification of the DRAM of the above-described embodiment I.
The present invention has improved film quality of an interlayer insulating film between wirings and between wirings.
This is an eighth embodiment of the present invention. The schematic configuration of the CVD apparatus that is Embodiment VIII of the present invention
This is shown in the figure (a block diagram showing a gas supply system). The CVD apparatus shown in FIG. 58 mainly includes a reactor body 110 and a vacuum pump.
Pump 111, source gas supply pipes 112 and 113, carrier gas
Decorative tubes 114, mass flow controllers arranged in each supply path
It comprises a roller 115 and a control valve 116. This CV
D unit has high step coverage and small film shrinkage
It is configured to form a silicon oxide film. This CV
The D device is the same as the DRAM 1 of the embodiment I, but
Inter-layer insulating film 27, sidewall spacer 29, interlayer insulating film 31
To form each. The source gas supply pipe 112 is a source gas G4 such as an inorganic
Silane gas (SiH_Four, Si_TwoH₆Etc.) to the reactor body 110
It is configured as follows. Source gas supply pipe 113 is a source
Gas G5 such as nitric oxide gas (N_TwoO) to the reactor 110
It is configured to be. The carrier gas supply pipe 114
Carrier gas G6 such as nitrogen gas (N_TwoTo supply)
It is configured. The reactor 110 is shown in FIG. 59 (schematic diagram).
The inside of the reaction tube (outer tube) 110A
Are provided in a double structure. The reaction tube (outside
A heater 110C is arranged on the outer periphery of the tube 110A.
One end of the reactor body 110 shown in FIG. 59 is connected to a vacuum pump 111.
It is connected. In addition, the other end of the reactor
Insert multiple wafers 100 (perform batch processing)
An opening / closing door 110D is provided. Reactor body 110
Inside, deposition of silicon oxide film on semiconductor wafer 100
Semiconductor wafer so that the surface crosses the reactant gas supply direction.
Insert and hold AHA 100 leaning
Is configured. In the reaction tube 110B at the other end of the reactor body 110,
Nozzle 112A connected to the source gas supply pipe 112 and
A nozzle connected to the source gas supply pipe 113 at a close position
113A is disposed. In Fig. 60 (enlarged sectional view of the main part)
As shown, the nozzle 112A feeds the source gas G4 into the reaction tube 110B.
And the nozzle 113A mixes with the source gas G4.
To supply the source gas G5 into the reaction tube 110B
Have been. Although not limited to this configuration, the nozzle 112A,
The gas supply directions of the nozzles 113A should cross each other.
It is authorized to. Source gas G4 supplied from the nozzle 112A, for example, Si
H_FourHas a thermal decomposition temperature of about 400 [° C]. From nozzle 113A
Source gas G5 supplied e.g. N_TwoO has a thermal decomposition temperature of about 550
[° C.]. Therefore, simply source gas G4, G5
When each is supplied into the reaction tube 110B, the SiH_FourPyrolysis first
Silicon on the inner wall of the reaction tube 110B and the surface of the semiconductor wafer 100.
Foreign matter such as silicon and porous silicon oxide adheres,
The CVD apparatus of the present embodiment has a thermal decomposition temperature of the source gas G4.
Mix each of the source gases G4 and G5 before reaching
As the gas G4 is diluted, the adhesion of foreign matter as described above
Can be reduced. For example, a specific example of a production condition of a silicon oxide film is as follows.
It is as follows.

[Generation conditions]

Further, the source gases G4 and G5 may be mixed outside the reaction tube 110B, that is, in the gas supply path. As described above, the semiconductor wafer 100 is held in the (47-26) reaction furnace body 110, and the source gas G4 (inorganic silane gas) and the source gas G5 (nitrogen oxide gas) are introduced into the reaction furnace body 110 from one end thereof. In a CVD apparatus for supplying and producing a silicon oxide film on the surface of the semiconductor wafer 100, a source gas is generated by mixing each of the source gases G4 and G5 below the thermal decomposition temperature of the source gas G4. Is supplied to the semiconductor wafer 100 held in the reaction furnace body 110. With this configuration, the source gas can be mixed at a temperature lower than the thermal decomposition temperature of the source gas G4, and the concentration of the source gas G4 can be diluted. Foreign matter (silicon particles, etc.) scattered between the holding portion of the wafer 100 and foreign matter adhering to the inner wall of the reactor body 110 is reduced, and consequently mixed into the silicon oxide film formed on the surface of the semiconductor wafer 100 Therefore, the quality of the silicon oxide film can be improved. Further, in the CVD apparatus, foreign substances adhering to the inner wall of the reactor body 110 can be reduced. (Embodiment IX) The present embodiment IX is different from the DRAM of the embodiment I in that the wiring 50
This is a ninth embodiment of the present invention in which the quality of the interlayer insulating film 51 between the wiring 53 and the wiring 53 is improved. FIG. 61 (schematic block diagram) shows a continuous processing apparatus which is Embodiment IX of the present invention. The continuous processing apparatus shown in FIG.
, A silicon oxide film (coating type insulating film) 51B, a silicon oxide film (coating type insulating film) 51B, and a silicon oxide film (stacking type insulating film) ) This is an apparatus for continuously forming each of 51C. The continuous processing apparatus mainly includes a wafer loading section 120A, an SOG coating section 121, a load lock section 122, a wafer transport section 123, a lamp annealing section 124, an etching section 125, an insulating film deposition section 12
6. It is composed of each wafer unloading unit 120B. A plurality of semiconductor wafers 100 are housed in the wafer loading section 120A. The semiconductor wafer 100 is in a state where the silicon oxide film 51A is deposited on the surface of the semiconductor wafer 100 after the wiring 50 is formed in the DRAM 1 of the embodiment I. Next, the semiconductor wafer 100 is transported to the SOG coating section 121, and a silicon oxide film (coating type insulating film) 51B is coated on the silicon oxide film 51A by the SOG method. The semiconductor wafer 100 coated with the silicon oxide film 51B is transported to the lamp annealing unit 124 via the load lock unit 122 and the wafer transport unit 123. The lamp annealing section 124 performs a low-temperature baking process (mineralization process) and a hardening baking process on the silicon oxide film 51B. The semiconductor wafer 100 subjected to the baking process is transferred to the etching unit 125 via the wafer transfer unit 123. The etching unit 125 performs etching (etchback) on the surface of the silicon oxide film 51B to remove the excess silicon oxide film 51B. Specifically, the silicon oxide film applied on the portion of the wiring 50 where the connection hole 52 is opened is removed. The semiconductor wafer 100 in which the surface of the silicon oxide film 51B is etched is immediately transferred to the insulating film deposition unit 126 via the wafer transfer unit 123. This insulating film deposition part 126
A silicon oxide film (deposited insulating film) 51C is deposited on the surface of the silicon oxide film 51B. The semiconductor wafer 100 on which the silicon oxide film 51C has been deposited is placed on the wafer unloading section 1 via the wafer transfer section 123.
Conveyed to 20B. This continuous processing apparatus includes a silicon oxide film 5 on an interlayer insulating film 51A.
After depositing 1B, the silicon oxide film 51B is baked,
Thereafter, the silicon oxide film is subjected to an etching process, and thereafter, each process can be continuously performed so that the silicon oxide film 51C can be immediately deposited on the surface of the silicon oxide film 51B (without contacting the atmosphere outside the device). It is configured as follows. As described above, after baking the silicon oxide film (coating type insulating film) 51B applied on the base surface (silicon oxide film 51A), the surface of the silicon oxide film 51B is coated with silicon oxide. In the method of forming the DRAM 1 for depositing the film (deposited insulating film) 51C, a step of applying the silicon oxide film 51B in a system (in an apparatus) shielded from the atmosphere, and a step of performing a bake treatment on the silicon oxide film 51B Then, a step of etching back the silicon oxide film 51B and a step of depositing a silicon oxide film (deposited insulating film) 51C on the surface of the silicon oxide film 51B are sequentially performed. With this configuration, since the silicon oxide film 51B is coated with the silicon oxide film 51C without being in contact with the air after the application and the baking process, the moisture absorption of the silicon oxide film 51B is reduced, and the deterioration of the film quality of the silicon oxide film 51B is reduced. can do. As a result, it is possible to improve the adhesion between the silicon oxide film 51B and the silicon oxide film 51C thereover, and prevent a change in the etching rate of the silicon oxide film 51B. Further, as shown in FIG. 62 (schematic block diagram), the continuous processing apparatus includes a wafer transfer section 127, a wafer cooling section 12 between a SOG coating section (batch type) 121A and a wafer transfer section 123.
8. Each of the wafer cassette units 129 may be sequentially arranged. This continuous processing apparatus is optimal when the baking process cannot be performed immediately after applying the silicon oxide film 51B in a batch manner in the SOG coating unit 121A. In other words, the continuous processing apparatus is configured such that it does not come into contact with the atmosphere outside the apparatus on its path until the silicon oxide film 51B is applied to the lamp annealing section 124 after being applied to the lamp annealing section 124. As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the scope of the invention. Of course there is. For example, the present invention can be applied to a semiconductor integrated circuit device using a DRAM as one unit, such as a microcomputer (one-chip microcomputer). In addition, the present invention is not limited to the DRAM, but includes SRAMs and ROMs.
And the like can be applied to a semiconductor integrated circuit device having another storage function. [Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) The degree of integration can be improved in a semiconductor integrated circuit device having a memory function. (2) In the semiconductor integrated circuit device, the soft error withstand voltage can be improved. Can have a high breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a principal part of a DRAM according to a first embodiment of the present invention, FIG. 2 is a partial cross-sectional plan view of a resin-sealed semiconductor device for sealing the DRAM, and FIG. FIG. 4 is an enlarged layout diagram of a main part of the DRAM, FIG. 5 is an equivalent circuit diagram of a main part of the DRAM, FIG. 6 is a plan view of a main part of the DRAM, FIG. FIG. 8 is a plan view of a main part in a predetermined manufacturing process of the DRAM, FIG. 9 is a plan view of a connection portion between a word line and a shunt word line of the DRAM, and FIG. FIG. 11 is a cross-sectional view taken along the line II-II of FIG. 11, FIG. 11 is a cross-sectional view taken along the line III-III of FIG. 6, and FIG. 12 is a main part including a region of the output stage circuit of the DRAM. FIG. 13 is a main part equivalent circuit diagram of a word boost circuit of the DRAM, FIG. 14 is a main part plan view of an element used in the word boost circuit, and FIG. Is a cross-sectional view of a main part of a region of an external terminal of the DRAM, FIGS. 16 to 33 are cross-sectional views of a main part showing the DRAM in each manufacturing process, and FIG. 34 is a schematic diagram of a main part of a chopping etching apparatus. FIG. 35 to FIG. 37 are time chart diagrams of gas flow rates of the etching apparatus, FIG. 38 is a diagram showing a relationship between an etching rate and a taper angle, and FIG. 39 to FIG. 42 is a schematic cross-sectional view of a processing apparatus, FIG. 42 is a cross-sectional view of a main part of a DRAM which is Embodiment II of the present invention, FIGS. 43 to 45 are cross-sectional views of a main part showing the DRAM in each manufacturing process, 46 to 50 are cross-sectional views of a main part of a DRAM according to Embodiment III of the present invention for each manufacturing process, and FIGS. 51 to 54 are main parts of a DRAM according to Embodiment IV of the present invention. FIG. 55 is a plan view of a main part of a semiconductor wafer which is Embodiment V of the present invention. FIG. 56 is a plan view of a main part of DRAM which is Embodiment VI of the present invention. FIG. 57 is a plan view of a principal part in a predetermined manufacturing process of the DRAM, FIG. 58 is a block diagram showing a gas supply system of a CVD apparatus which is Embodiment VIII of the present invention, and FIG. 60 is an enlarged cross-sectional view of a main part of the CVD apparatus, and FIGS. 61 and 62 are schematic structural views of a continuous processing apparatus which is Embodiment IX of the present invention. . In the figure, 1... DRAM, M... Memory cell, C... Stacked information storage capacitor element, Qs.
MISFET, Qn, Qp... MISFET.

──────────────────────────────────────────────────の Continued on front page (72) Inventor Hiroko Kaneko 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (72) Inventor Toshihiro Sekiguchi 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the Development Center (72) Inventor Hiroyuki Uchiyama 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Takashi Nakamura 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. 72) Inventor Toshio Maeda 3681 Hayano, Mobara-shi, Chiba Prefecture, Hitachi Device Engineering Co., Ltd. 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the Device Development Center (72) Inventor Atsushi Ogishima 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (72) Maki Nagao 5-20, Josuihoncho, Kodaira-shi, Tokyo No. 1 Inside the Musashi Plant, Hitachi, Ltd. (72) Inventor Tomomasa Funabashi 5-20-1, Kamisui Honcho, Kodaira City, Tokyo Inside the Musashi Plant, Hitachi, Ltd. 5-20-1, Honcho, Musashi Plant, Hitachi, Ltd. (72) Inventor Masayuki Kojima 5-20-1, Josuihonmachi, Kodaira City, Tokyo In Musashi Plant, Hitachi, Ltd. (72) Atsushi Koike, Inventor, Tokyo Atsushi 5-20-1, Josuihonmachi, Kodaira-shi Musashi Factory, Hitachi, Ltd. (72) Inventor Hiroyuki Miyazawa 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Musashi Factory, Hitachi, Ltd. (72) Inventor Masato Sadaoka 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Inside the Kura Factory (72) Kazuya Kadota, Inventor 5-20-1, Josuihoncho, Kodaira City, Tokyo Inside Musashi Factory, Hitachi, Ltd. (72) Inventor Tadashi Chikawara 5-chome, Josuihoncho, Kodaira City, Tokyo No. 1 Inside the Musashi Factory of Hitachi, Ltd. (72) Kazuo Nojiri 5--20-1, Kamisumihonmachi, Kodaira-shi, Tokyo Inside the Musashi Factory of Hitachi, Ltd. Address Hitachi Research Laboratories, Hitachi, Ltd. (56) References IEICE Transactions '85 / 5Vol. J68-C No. 5 pp. 325− 332 (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8242 H01L 27/108 H01L 21/027

Claims (7)

(57) [Claims] A plurality of memory cells each including a MISFET and a capacitance element and arranged in a row direction and a column direction, each of the memory cells including a plurality of memory cells connected to a word line and a data line; The MISFET has a gate electrode, a source region, and a drain region, and the capacitor is formed on the first electrode connected to one of the source region and the drain region, and on the first electrode. Manufacturing of a semiconductor integrated circuit device having a second electrode and a dielectric film formed between the first electrode and the second electrode, wherein the data line is connected to the other of the source region and the drain region Forming a gate electrode of the MISFT on a main surface of a semiconductor substrate; and introducing a source region and a drain region of the MISFET by introducing impurities into a main surface of the semiconductor substrate on both sides of the gate electrode. Form Forming a first conductive film covering the MISFT on the main surface of the semiconductor substrate; and patterning the first conductive film by a photolithography process using a mask having a substantially square pattern. Forming a first electrode of the capacitive element on one of the source region and the drain region and the gate electrode; forming the dielectric film on the first electrode of the capacitive element; Forming a second electrode of the capacitor element thereon, wherein the first electrode has a substantially rectangular shape in plan view and includes a portion where a distance between a plurality of adjacent first electrodes is wide and a portion where the space is narrow. The method of manufacturing a semiconductor integrated circuit device, wherein the substantially rectangular pattern has a correction pattern in a portion where a space between the adjacent first electrodes is wide. 2. The semiconductor integrated circuit according to claim 1, further comprising a step of forming a sidewall spacer on a side surface of said gate electrode before said step of forming a first conductive film covering said MISFET. Device manufacturing method. 3. The semiconductor integrated circuit according to claim 2, further comprising a step of forming a first insulating film having the same pattern as the gate electrode on the gate electrode before the step of forming the sidewall spacer. A method for manufacturing a circuit device. 4. The method according to claim 1, wherein the step of forming the sidewall spacer comprises:
4. The method according to claim 3, further comprising: forming a second insulating film on the first insulating film so as to cover the gate electrode; and etching the second insulating film by anisotropic etching. Of manufacturing a semiconductor integrated circuit device. 5. A third insulating film covering the MISFET and the capacitor, after the step of forming a second electrode of the capacitor, exposing another part of the source region and the drain region. Forming a third insulating film having an opening; and forming a conductive layer on the third insulating film and in the opening, wherein the conductive layer is used as the data line and the source region 5. The method according to claim 4, wherein the semiconductor integrated circuit device is electrically connected to the other of the drain region and the drain region. 6. The correction pattern according to claim 1, wherein a part of a resist mask corresponding to the first electrode located on a side of a connection portion between the data line and the other of the source region and the drain region includes:
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed in order to prevent the semiconductor integrated circuit device from being formed smaller than a design value due to excessive exposure in the photolithography process. 7. A method of forming a first conductive film on a main surface of a semiconductor substrate, and patterning the first conductive film by a photolithography process using a mask having a substantially square pattern, thereby forming a plurality of first conductive films. Forming an electrode, wherein the first electrode is substantially square in plan view, and has a portion where a space between a plurality of adjacent first electrodes is wide and a portion which is narrow; The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a correction pattern is provided in a portion where the distance between the adjacent first electrodes is large.