JPH02246150A - Semiconductor integrated circuit device, its formation and apparatus for producing it - Google Patents

Abstract

PURPOSE:To increase a charge storage amount of a capacity element, for information storage use, of a stacked structure and to enhance an alpha-ray soft-error breakdown strength and an integration density of a DRAM by a method wherein a correction pattern which increases a surface area of a lower-layer electrode layer is formed on the lower-layer electrode structure of the capacity element, for information storage use, of the stacked structure of a memory cell of the DRAM. CONSTITUTION:A capacity element C, for information storage use, of a memory cell M is constituted in such a way that a lower-layer electrode layer 33, a dielectric film 34 and an upper-layer electrode layer 35 are laminated one after another. The capacity element C for information storage use is constituted in a so-called stacked structure. In the lower-layer electrode layer 33, a correction pattern 33A protruding in a plane direction from a region formed in a plane square shape is formed on the connection side of an n-type semiconductor region 28 and a complementary data line 50. A size of an etching mask used to process the lower-layer electrode layer 33 is reduced by reflected light; accordingly, a size of the lower-layer electrode layer 33 is made smaller than a preset value. Then, the correction pattern 33A is constituted in such a way that the size of the lower-layer electrode layer 33 is made large in anticipation of a reduced portion of the size.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to semiconductor technology, and in particular to DRAM (DRAM).
amic Random Access Memory
) applied to semiconductor integrated circuit devices and their formation technology.
It is related to effective technology. [Prior art] A memory cell that holds 1 [bit] of information in a DRAM.
MISFET for memory cell selection and capacitive element for information storage
It consists of a series circuit with a child. The memory cell selection
The gate electrode of the MISFET is a word extending in the row direction.
connected to the line. MISFET for memory cell selection
One semiconductor region is connected to a complementary data line. The other semiconductor region is connected to one voltage of the information storage capacitive element.
connected to the pole. The other electrode of the information storage capacitive element
A predetermined potential is applied to. This type of DRAM is integrated to increase capacity.
There is a trend towards reducing the size of resellers. When the size of memory cells is reduced, the capacity for information storage
The size of the element is also reduced, so the amount of charge storage that serves as information is reduced.
decreases. Decrease in charge storage amount is α-ray soft error tolerance
especially for large-capacity DRA of 1 [Mbit1 or more].
M is an important technical issue where improving alpha-ray soft error tolerance is an important technical issue.
It has become one. Based on these technical issues, DRAM memory cells
Stacked structure (STC structure) with information storage capacitive element
tend to be adopted. This stacked structure stores information.
A multilayer capacitive element consists of a lower electrode layer, a dielectric film, and an upper electrode layer.
They are constructed by sequentially laminating each of them. The lower electrode layer is
A part of the other semiconductor area of the recell selection MISFET
connected and the other area stretched over the gate electrode.
There is. The lower electrode layer is a polycrystalline silicon film deposited by CVD.
Trilithography technology and etching technology are applied to achieve a specified flatness.
It is patterned to have a planar shape. dielectric
A body membrane is provided along the top and side surfaces of the lower electrode layer.
ing. An upper electrode layer is provided on the surface of the dielectric film.
ing. The upper electrode layer is connected to the stack of other adjacent memory cells.
integrated with the upper electrode layer of the information storage capacitive element with a closed structure.
and is used as a common plate electrode. The upper electrode layer is made of polycrystalline silicon film like the lower electrode layer.
has been completed. Note that the memory cell is a stacked structure information storage capacitor.
For example, regarding the DRAM that constitutes the
No. 35906. [Problem to be solved by the invention] The present inventor has developed a DRAM having a large capacity of 4 [Mbitl].
During development, we discovered the following problems. The DRAM currently being developed by the inventor has a folded bit structure.
The trine method (two-intersection method) is adopted. this kind of
DRAM is alternately reversed in the direction in which complementary data lines extend.
Memory cells are arranged in a pattern. the memory cell
The lower electrode layer of the stacked structure information storage capacitor is
The planar shape is rectangular. Adjacent memory
Lower electrode layer of a stacked structure information storage capacitor element
The interval is between one semiconductor of the MISFET for memory cell selection.
Increase the connection area between the area and the complementary data line, otherwise
is set small. In other words, in the connection area
There is an upper electrode layer between the lower electrode layers. Allowances for alignment and insulation separation during the manufacturing process with connection holes, etc.
The spacing is large because the dimensions of the front are added.
Except for the connection area mentioned above, the minimum processing size between the lower electrode layers is
or close to it, so the spacing is small.
For this reason, photolithography technology is used in the manufacturing process.
An etching mask is used to process the lower electrode layer using
During the exposure process, the etching mask is formed by diffraction phenomenon.
In particular, the connection area side of the block is overexposed. moreover,
The connection region side is affected by the reflected light from the step of the gate electrode layer.
is overexposed. In other words, the etching mask
The lower electrode layer processed (etched) using
The size is much smaller than the original size, and the stack
The amount of charge storage in the information storage capacitive element of the double structure decreases.
. This decrease in charge storage decreases the α-ray soft error withstand voltage.
This not only causes DRAM malfunction, but also causes information storage.
Since it is necessary to increase the size of the product capacitor, D
Decrease the degree of integration of RAM. The objects of the present invention are as follows. (1) In a semiconductor integrated circuit device having a memory function,
Our aim is to provide technology that can improve the degree of integration.
Ru. (2) In the semiconductor integrated circuit device, a soft error
Our goal is to provide technology that can improve voltage resistance.
. (3) The semiconductor integrated circuit device has a high operating speed.
The aim is to provide technology that can speed up the process. (4) In the semiconductor integrated circuit device, electrical reliability
The goal is to provide technology that can improve the (5) In the semiconductor integrated circuit device, manufacturing processing
Our goal is to provide technology that can improve accuracy.
. (6) In the semiconductor integrated circuit device, manufacturing yield
The goal is to provide technology that can improve performance. (7) In the semiconductor integrated circuit device, the number of manufacturing steps is
The objective is to provide technology that can reduce the (8) In the semiconductor integrated circuit device,
We provide technology that can improve the film quality of insulating films.
There are many things. (9) Provide a device for improving the film quality of the insulating film as described in (8) above.
It's about doing. (10) In the semiconductor integrated circuit device, the external device
To provide technology that can improve driving performance
be. (11) In the semiconductor integrated circuit device, an element formation surface
To provide a technology capable of flattening the surface of
It is in. (12) In the semiconductor integrated circuit device, the manufacturing process
Our goal is to provide technology that can stabilize the
Ru. (13) Equipment for stabilizing the manufacturing process mentioned in (12) above.
The aim is to provide a (14) In the semiconductor integrated circuit device, installed in the semiconductor integrated circuit device.
We provide technology that can increase the withstand voltage of
There are many things. The above and other objects and novel features of the present invention are accomplished by the present invention.
It will become clear from the description of the specification and the attached drawings.
cormorant. [Means for solving the problem] Outline of one typical invention disclosed in this application.
A brief explanation of the main points is as follows. (1) MISFET for memory cell selection and stacked structure
A memory cell is constructed by a series circuit with a capacitive element for information storage.
In a semiconductor integrated circuit device having a DRAM that
For information storage in the stacked structure of DRAM memory cells.
Correction to increase the surface area of the lower electrode layer of the capacitive element
Configure a pattern. (2) Extending the wiring on the base surface with a stepped shape
In the semiconductor integrated circuit device, the wiring. Transition metal film deposited by CVD method, sputtering method
A composite film in which aluminum films or their alloy films are sequentially laminated.
Consists of synthetizer. (3) The wiring in (2) above is made of transition gold deposited by the CVD method.
metal film, aluminum film deposited by sputtering method, or a combination thereof.
A gold film and a transition metal film deposited by sputtering are sequentially deposited.
Layered 3J! It is composed of a composite membrane with f structure. (4) Through the opening formed in the passivation film,
The same conductive layer as the internal wiring, to which the ending wire is connected.
For semiconductor integrated circuit devices having external terminals formed by
and the internal wiring is made of an aluminum film or an alloy film thereof,
It is composed of a composite film in which each of the transition metal films is sequentially laminated, and the
The external terminals are made of an aluminum film or an aluminum film from which the transition metal film has been removed.
is composed of the alloy film. (5) The aluminum film of the external terminal in (4) above or its
The transition metal film on the alloy film is formed on the passivation film.
removed within the area defined by the designated Sekiguchi. (6) Forming an insulating film on the gate electrode of the MISFET,
A sacrificial layer is formed on the sidewall of the gate electrode and the sidewall of the insulating film above the gate electrode.
For semiconductor integrated circuit devices that form wall spacers
, the insulating film on the gate electrode, the side wall
Soak each of the pacers with inorganic silane gas and nitrogen oxide gas.
It consists of a silicon oxide film deposited using the CVD method as a base gas.
Ru. (7) Lower electrode layer formed on the base insulating film, the base
Dielectric film formed on the insulating film and on the surface of the lower electrode layer
and an upper electrode layer formed on this dielectric film.
Semiconductor with stacked structure information storage capacitive element
In the integrated circuit device, information storage of the stacked structure
The dielectric film of the capacitive element is made of a composite film containing a silicon nitride film.
The base insulating film is coated with inorganic silane gas and nitrogen oxide gas.
A silicon oxide film deposited by the CVD method using gas as a source gas.
Configure. (8) First MISFE constituting a memory cell for storage function
T, a second MISFE constituting a peripheral circuit of the memory function;
and an eighth MIS that constitutes the output stage circuit of the memory function.
In a semiconductor integrated circuit device having an FET, each chip
The channel type is the same and each gate length size is substantially the same.
are the same, the first MISFET, the second MISFET
The threshold voltages of SFET and 3rd MISFET are set in order.
Next lower. (9) Half the third MISFET of the output stage circuit in (8) above.
The first MIS of the memory cell is configured on the main surface of the conductor substrate.
FET and the second MISFET of the peripheral circuit are each connected to the semiconductor
A higher impurity concentration was formed on the main surface of the body substrate.
It is formed on the main surface of the well region. (10) MISFET for memory cell selection and stacked on its upper layer
Series with information storage capacitive element of stacked structure
A memory cell in which memory cells consisting of circuits are arranged in a matrix.
Configure a memory cell array and add peripherals to the peripheral area of this memory cell array.
Semiconductor integrated circuit device having DRAM with side circuits arranged
In this case, a front panel is provided between the memory cell array and the peripheral circuit.
The lower electrode layer of the stacked structure information storage capacitor element,
A step formed by the same conductive layer as the upper heavy pole layer or both layers
Provide a relaxing layer. (11) The memory cell array and peripheral circuit of (10) above
In between, from the former to the latter, the stacked structure
Same as the lower electrode layer and upper electrode layer of the information storage capacitive element.
a first step relaxation layer formed of one conductive layer; the lower electrode layer;
Or the second step relief formed by the same conductive layer as the upper electrode layer
Place each of the layers in sequence. (12) The memory cell array and peripheral circuit of (10) above
A guard ring region is arranged between the steps, and the step relaxation layer is
placed in the guard ring area. (13) Multiple memories at the intersection of data lines and word lines
Cells are arranged to form a memory cell array. an area other than the memory cell array in a layer above the word line;
Place the shunt word line connected to the word line at
In a semiconductor integrated circuit device having a memory function,
around the connection between the word line and the shunt word line.
A step relief layer is provided. (14) MISFET for memory cell selection and information storage capacity
Arranging memory cells formed in series circuits with quantum elements
, has a folded bit line type DRAM.
In a semiconductor integrated circuit device, one of the complementary data lines
a first intersection of the first data line and the first word line;
the other second data line of the gender data line and the first word line.
The husband of the second intersection with another second word line adjacent in the column direction
the first word line, the second word line, and the second word line.
Each of the word lines has substantially the same width dimension and a predetermined separation dimension.
While being held, extend in parallel in the row direction, and
Directions opposite to each other for each of the first data line and the second data line
The first word line and the second word line are connected so that they protrude from the
The first word line at the first intersection is extended in a zigzag manner.
Make the second word line side protrude along the shape of the memory cell
and the first word line side of the second word line at the second intersection.
Protrude along the shape of the memory cell. (15) Aluminum film or its like by anisotropic etching
alloy film, or transition with the aluminum film or its alloy film.
Semiconductor integrated circuit for patterning composite films with transfer metal films
In the method for forming a circuit device, the aluminum film,
Deposit an alloy film or composite film and photoresist on this surface.
The process of forming a mask, and the process of forming a halogen element and halogen
Using anisotropic etching using a compound as the etching gas
. The aluminum film, its alloy film or composite film in a vacuum system
a step of applying a predetermined patterning to the anisotropic etching process;
The photoresist mask is applied in the same vacuum system as the printing process.
Uses halogen compounds and oxygen gas. Low below room temperature
The removal process by hot ashing and the low temperature ashing process
The predetermined patterning is performed in the same vacuum system as the process.
Baking treatment for aluminum film or its alloy film
Prepare for the process. (16) Aluminum film or its like by anisotropic etching
transition with the alloy film or the aluminum film or its alloy film
Semiconductor integrated circuit patterning composite film with metal film
In the method for forming a device, the aluminum film,
Deposit a gold film or composite film and apply photoresist on this surface.
Process of forming a mask, halogen element and halogenation
Using anisotropic etching using a compound as the etching gas,
The aluminum film, its alloy film or composite film in a vacuum system
a step of applying a predetermined patterning to the anisotropic etching process;
The photoresist mask is applied in the same vacuum system as the printing process.
Removed by ashing using halogen compounds and oxygen gas.
and the anisotropic etching process.
The chlorine is washed away in a system shielded from the atmosphere and then dried.
and a step of (17) MIS surrounded by channel stopper region
In a semiconductor integrated circuit device having an FET, the MI
SFET is connected to the periphery of one semiconductor region to which a high voltage is applied.
, a low voltage is applied between the surroundings and the channel forming region.
the channel forming region;
A gate electrode is placed on top with a gate insulating film interposed.
and the channel stopper region is connected to the other semiconductor.
Surrounds and structures the body area. (18) MISFET of (17) above + 7) One half
The outer peripheral end of the upper layer wiring connected to the conductor region is connected to the gate.
placed on the electrode or extended onto the other semiconductor region.
and place it. (19) Memory at the intersection of complementary data line and word line
MISFET for cell selection and stacked structure information storage
A memory cell consisting of a series circuit with a capacitive element is arranged, and
The same conductivity as the complementary data lines for each of the two sets of complementary data lines.
Extend column select signal lines that extend in the same direction in the same layer.
A semiconductor integrated circuit device having a DRAM, which is
complementary data adjacent to the column select signal line.
memory cells connected to one of the data lines.
The lower electrode layer of the information storage capacitive element with the tucked structure is
of the information storage capacitive element in the stacked structure of the memory cell.
It is configured with a larger size than the lower electrode layer. (20) Memory at the intersection of complementary data line and word line
A cell is placed, and this memory cell is M for memory cell selection.
ISFET and stacked structure information storage capacitive element
Semiconductor integrated circuit with DRAM composed of series circuits
In the memory cell device, information on the stacked structure of the memory cell is provided.
The lower electrode layer of the capacitive element for information storage is
Gate electrode of MISFET for Mori cell selection and its gate
A word line that selects other memory cells adjacent to each other in the width direction.
The lower electrode layer and the front electrode layer are configured to polymerize respectively during
An interlayer insulating film between the lower electrode layer and the word line is formed between the lower electrode layer and the word line.
It is configured to be thicker than the interlayer insulating film between the gate electrode and the gate electrode. (21) Memory cells arranged on the main surface of the same semiconductor substrate
Information write operation and information read operation of array and memory cells
Direct peripheral circuits that directly control operations and other indirect peripheral circuits
For semiconductor integrated circuit devices with a resin film coated on the surface of the circuit.
Then, the resin film is divided into a plurality of parts and applied. (22) In (21) above, before the scribing process
A plurality of formation regions of the semiconductor integrated circuit device are arranged in a matrix.
A resin film is applied to the entire surface of the semiconductor wafer.
process and the formation area of each semiconductor integrated circuit device of this resin film.
Remove areas between areas and external terminals of each semiconductor integrated circuit device
At the same time, on the formation region of each semiconductor integrated circuit device,
The process of dividing the resin film and each semiconductor of the semiconductor wafer
By scribing between the formation areas of the integrated circuit device, multiple
and a step of forming a semiconductor integrated circuit device. (23) Bake the coated insulating film applied on the underlying surface.
After the treatment, the coated insulating film is etched.
After coating, a deposited insulating film is deposited on the surface of this coated insulating film.
In the method of forming semiconductor integrated circuit devices,
a step of applying the coating type insulating film in a system shielded from the
a step of performing a baking treatment on the coating type insulating film;
A process of etching an insulating film, the above-mentioned coating type insulating film
Each step of depositing a deposited insulating film on the surface of the
. (24) A film formed on a base surface with a stepped shape.
Semiconductor integrated circuit patterned by anisotropic etching
In the method for forming the device, the film is anisotropically etched;
By repeating each isotropic etching process alternately,
Patterning. (25) The anisotropic etching described in (24) above is based on this anisotropic etching.
It adheres to the patterned side of the membrane by chemical etching.
before the organic polymer is destroyed by isotropic etching.
Do it again. (26) Hold the semiconductor wafer in the reaction chamber, and
A source gas consisting of nitrogen gas and nitrogen oxide gas is introduced into the reaction chamber.
The surface of the semiconductor wafer is supplied from one end side to the inside of the semiconductor wafer.
A semiconductor assembly that uses the CVD method to generate a silicon oxide film on the surface.
In the method for forming an integrated circuit device, the inorganic silane gas is
Both inorganic silane gas and nitrogen oxide gas are released below the thermal decomposition temperature.
are mixed to produce a source gas, and this source gas is
It is supplied to the semiconductor wafer side held in the reaction chamber. [Function] According to the above-mentioned means (1), the gap between the adjacent lower electrode layers
In areas with large gaps (data line side), photolithography
Diffraction phenomenon during exposure of roughy technology and reflection from base level difference
an etching mask for processing the lower electrode layer with light;
This reduces the possibility that the size of the
), the surface of the lower electrode layer is
Capacitive element for information storage with stacked structure that secures surface area
The amount of charge accumulated can be increased. As a result, alpha rays
Improves soft error withstand voltage and reduces memory cell area.
Therefore, the degree of integration of DRAM can be improved. According to the above-mentioned means (2), the aluminum film or
The alloy film has low resistance and increases signal transmission speed
Therefore, it is possible to increase the operating speed of the circuit.
At the same time, the transition metal film is
High step coverage reduces wiring breakage defects
can improve electrical reliability.
Ru. In addition, the transition metal film below the wiring is connected to silicon.
The precipitation phenomenon of silicon can be prevented in some parts. According to the above-mentioned means (3), the transition metal layer in the upper layer of the wiring
The metal film can prevent the occurrence of aluminum hillocks.
can. In addition, the transition metal film on the upper layer of the wiring is aluminum.
Reduces the reflectance of the surface of the film or its alloy film, making it easier to process wiring.
Diffraction phenomenon during exposure when forming etching masks
This improves wiring processing accuracy.
can be done. In addition, the transition metal film on the upper layer of the wiring
The melting point is lower than that of the underlying aluminum film or its alloy film.
Aluminum films and
The alloy film will not be melted. According to the above-mentioned means (4), in the bonding process,
to improve the reflectance of the surface of the external terminal and
Bonding of external terminals due to the difference in reflectance with the scivation film
bonding position can be reliably recognized.
Reduce manufacturing defects and improve yield of semiconductor integrated circuit devices.
can be raised. In addition, the external terminal and bonding
bondability with aluminum wire (aluminum wire).
This reduces bonding defects.
, it is possible to improve the yield of semiconductor integrated circuit devices.
. According to the above-mentioned means (5), the surface transition of the external terminal is
A mask for removing the transfer metal film is applied to the passivation film.
It can also be used as a mask to form openings.
The number of manufacturing steps is reduced by the amount equivalent to the process of forming the
can be done. According to the above-mentioned means (6), the insulation on the gate electrode
The silicon oxide film, which is the membrane and sidewall spacer, is
Oxide deposited by CVD method using organic silane as source gas
Because film shrinkage can be reduced compared to silicon film,
Reduces peeling between the insulating film and sidewall spacer.
and reduce the leakage between the gate electrode and other conductive layers.
It is possible to prevent problems and improve electrical reliability.
Insulating film on the gate electrode, side wall space
High step coverage of silicon oxide film
Therefore, it is necessary to improve the uniformity of the silicon oxide film thickness and improve the dielectric strength.
can be raised. Also, step coverage is high
This reduces the amount of deposited film required to obtain the same sidewall thickness.
The thickness can be reduced, and the lower electrode layer can be easily processed. According to the above-mentioned means (7), the information of the stacked structure is
The thickness of the underlying insulating film relative to the dielectric film of the capacitive element for information storage
Reduces shrinkage that occurs between the dielectric film and the underlying insulating film
dielectric film.
Prevents destruction and leakage between the lower electrode layer and the upper electrode layer
Prevents electric current. In addition to improving electrical reliability,
Since the step coverage of the insulating film is high, the silicon oxide film is
The uniformity of the film thickness is improved, and the lower electrode layer on the underlying insulating film and its
The dielectric strength between the layer and the conductive layer below can be increased. According to the above-mentioned means (8), the noise generated in the power supply
Based on this, the first MISFET of the memory cell in the unselected state is
It is possible to prevent erroneous conduction, so please do not write information.
Electrical reliability is ensured in each reading operation and information readout operation.
The third MISFE of the output stage circuit can be improved.
Since the substrate effect constant of T can be reduced, the output signal can be reduced.
to increase the signal level and improve the driving ability of external devices.
Furthermore, the first MISFET of the memory cell
In comparison, the threshold voltage of the second MISFET in the peripheral circuit is lowered.
This improves the transfer conductance and increases the operating speed.
It is possible to increase the speed. According to the above-mentioned means (9), the third M of the output stage circuit
ISFET has a low impurity concentration in the semiconductor substrate, so
Control of the impurity concentration on the main surface of the conductive substrate or a slight impurity concentration
The threshold voltage can be easily set using the
, the first MISFET of the memory cell, and the second MISFET of the peripheral circuit.
Each of the MISFETs has a gap between the semiconductor substrate and the well region.
Forming a potential barrier due to the difference in purity concentration
As a result, the α-ray soft error resistance can be improved.
can. The improvement of α-ray soft error resistance is due to the memory cell surface.
Since the product can be reduced, the degree of integration can be improved.
I can do it. According to the above-mentioned means (10), the memory cell array
and the peripheral circuit is relaxed by the step relief layer,
Wiring extending over each area (e.g. aluminum wiring)
) to stabilize the photolithography technology used to process
As a result, disconnection defects at the stepped portion of the wiring can be avoided.
The production yield can be improved. According to the above-mentioned means (11), the memory cell array
The step portion between the
Improve manufacturing yields by reducing
can do. According to the above-mentioned means (12), the occupation of the step relaxation layer
All or part of the area can be used as the area occupied by the guard ring area.
This reduces the area occupied by the step relief layer.
It is possible to improve the degree of integration. According to the above-mentioned means (13), the word line and the shunt
around the connection part with the word line for
This reduces the step between the
Wiring such as word line for client (e.g. aluminum wiring)
Photolithography to process connection holes for connecting wires and wires.
The wiring technology can be stabilized.
Reduces disconnection and continuity defects at the stepped portion, and improves manufacturing efficiency.
Yield can be improved. According to the above-mentioned means (14), the first word line and
The protruding portion is connected to the MI for memory cell selection at the first intersection.
The second word line and its protrusion are used as the gate electrode of SFET.
The output part is a MISFE for memory cell selection at the second intersection.
The protruding portion is used as the gate electrode of each T.
, ensure the gate length of MISFET for memory cell selection
This reduces the short channel effect and improves DRAM performance.
can improve the degree of integration of the first intersection.
The interval between memory cells arranged at each of the first and second intersections is reduced.
Because it can be made smaller, the degree of integration of DRAM can be further improved.
can do. According to the above-mentioned means (15), the ashing process
Since it is performed at low temperature and in the same vacuum system, aluminum
Aluminum in the side film formed on the side wall of the aluminum membrane
reducing the formation of compounds between umum and oxygen;
This makes it easier to remove the side film, and the front
The process from anisotropic etching to baking is exposed to the atmosphere.
It is carried out in the same vacuum system without release, and the anisotropic
Baking can reduce chlorine generated during the tucking process.
This reduces corrosion of the aluminum film.
be able to. According to the above-mentioned means (16), the ashing process
Since it is carried out in the same vacuum system as the etching process mentioned above,
Size generated on the side wall of aluminum film or its alloy film
Reduces the possibility that the film will be converted into alumina (Ag2O,).
The anisotropic etching process reduces the
The chlorine produced can be removed by washing with water, so
Reducing corrosion of aluminum film or its alloy film
I can do it. According to the above-mentioned means (17), one of the MISFETs
The other semiconductor region does not contact the channel stopper region.
The pn junction breakdown voltage of one semiconductor region is improved, and the M
The ISFET can be made to have a high breakdown voltage. According to the above-mentioned means (18), the one semiconductor region
A gate electrode is formed on the surface of the interlayer insulating film between the
It is formed in a concave shape with a step shape, and due to this concave shape, the upper layer
The etching mask used to process the lines cuts the upper layer wiring during exposure.
The size is reduced by light reflecting off the surface of the cambial layer.
It is possible to reduce the processing accuracy of upper layer wiring.
can be improved. According to the above-mentioned means (19), the column select signal
The dimension between the complementary data lines corresponding to the line placement
Etching mass for processing the lower electrode layer based on the spread
Due to the size reduction due to diffraction phenomenon during exposure,
Therefore, one data line adjacent to the column select signal line
For information storage in a stacked structure of memory cells connected to
Since the size of the lower electrode layer of the capacitive element was increased, this
The lower electrode layer may be reduced to a size smaller than the set value.
charge storage in a stacked structure information storage capacitor element.
quantity can be secured. As a result, α-ray soft error
-Improved voltage resistance and reduced memory cell area
Therefore, the degree of integration of DRAM can be improved. According to the above-mentioned means (20), the lower electrode layer and the workpiece are connected to each other.
By increasing the thickness of the interlayer insulating film between the electrode wire and the lower electrode layer,
Since the height is increased, the area of the lower electrode layer is increased in the height direction,
Increasing the amount of charge storage in stacked structure information storage capacitors
In addition, the lower electrode layer and the gate voltage
By thinning the interlayer insulating film between the pole and the MI for memory cell selection.
Lower the level difference between the SFET and the complementary data line.
Therefore, we reduced the aspect ratio at the connection part and
It is possible to reduce disconnection defects in the complementary data line. this
As a result, the alpha-ray soft error resistance has been improved and DRAM integration has been improved.
In addition to improving the electrical reliability of DRAM,
reliability can be improved. According to the above-mentioned means (21), the semiconductor substrate, the resin
It is possible to alleviate the stress caused by the difference in linear expansion coefficient of each membrane.
This prevents warping of semiconductor substrates and
It is possible to prevent cracks from occurring in the film on the main surface.
can. The resin film is applied to the semiconductor wafer before the scribing process.
Formed by applying and baking when in a state of
Since the probe needle is not fused during the probe test,
Improve reliability of wafer inspection process and increase yield
can be improved. According to the above-mentioned means (22), the resin film is divided.
The process is performed to form each semiconductor integrated circuit device on the semiconductor wafer.
In the process of removing the resin film between the external terminal areas and between the external terminal areas.
Therefore, it is compatible with the step of dividing the resin film.
This will reduce the number of steps required to form semiconductor integrated circuit devices.
be able to. According to the above-mentioned means (23), the coating of the coating type insulating film is
Deposits are completely eliminated without contacting the atmosphere after baking and baking.
Since it is covered with a thin film, it reduces moisture absorption of the coated insulation film.
Deterioration of the film quality of the coated insulating film can be reduced. child
As a result, the adhesion between the coated insulating film and the deposited insulating film is improved.
and prevent changes in the etching rate of coated insulating films.
be able to. According to the above-mentioned means (24), the patterning of the film is
isotropic etching while ensuring etching anisotropy.
Remove etching residue on the surface of the step-shaped part of the base by etching.
The amount of overetching can be reduced.
and prevent damage and destruction of the underlying surface.
. According to the above-mentioned means (25), the anisotropic etching
The organic polymer produced in
The side edge of isotropic etching is
To reduce the amount of etching and increase the anisotropy of etching
I can do it. According to the above-mentioned means (26), the source gas is inorganic.
Mixed at below the thermal decomposition temperature of silane gas, the inorganic silane
Since the concentration can be diluted, the solution in the reaction chamber can be
Splashing between the source gas supply and the semiconductor wafer holder
Reduces the amount of foreign matter (silicon particles) attached to the walls of the reaction chamber.
oxidation resulting in the formation of oxidation on the surface of the semiconductor wafer.
Reduces the amount of foreign matter mixed into the silicon film or attached to its surface.
This improves the quality of the silicon oxide film.
be able to. In addition, in the CvD device, the reaction
Foreign matter adhering to indoor walls can be reduced. Hereinafter, regarding the configuration of the present invention, MIS for memory cell selection will be explained.
Series of FET and stacked information storage capacitive element
The present invention is applied to a DRAM that constitutes a memory cell with a circuit.
This will be explained along with another embodiment. Note that the same functions are used throughout the explanation of the examples.
Those with the same symbol are given the same symbol, and the repeated explanation is as follows.
Omitted. (Example of the invention) (Example I) Resin-sealed type for sealing a DRAM which is an example of the invention!
The semiconductor device is shown in FIG. 2 (partial cross-sectional plan view). As shown in Figure 2, DRAM (semiconductor pellet)
is S OJ (Small -9-ut-1ina J
-bend) type resin-sealed semiconductor device 2.
There is. DRAMI is the tab 3A of the resin-sealed semiconductor device 2.
It is mounted on the surface with an adhesive interposed. The DRAM1 has a large capacity of 4CMbits.
. This DRAMI is a 350[:mil] resin-sealed half
It is sealed in the conductor device 2. On the main surface of DRAMI
1 [Memory cell (memory element) that stores bitl information
) are arranged in rows and columns in a memory cell array.
It is. Other than memory cell arrays, DRAM
Direct peripheral circuits and indirect peripheral circuits are arranged on the main surface of
There is. Direct peripheral circuits perform information writing operations of memory cells and
This is a circuit that directly controls the information read operation, and the row address
column address decoder circuit, column address decoder circuit, sense
A single indirect peripheral circuit including an amplifier circuit, etc.
This is a circuit that indirectly controls the operation of the side circuits, and the clock
Includes signal generation circuits, buffer circuits, etc. At the most peripheral part of the DRAMI,
There are external terminals (pond terminals) in the center of each side and long side.
BP) are arranged. This external terminal BP is connected via a bonding wire 4.
Connected to inner lead 3B. bondingwa
Ear 4 uses aluminum (80) wire. Also
, as the bonding wire 4, a gold (Au) wire,
The surface of copper (Cu) wire and metal wire is coated with insulating resin.
Bonding wires may be used such as covered wires.
Ear 4 is a bonding method that combines thermocompression bonding with ultrasonic vibration.
It is bonded by. The inner lead 3B is integrated with the outer lead 3C.
It is configured. This inner lead 3B, outer lead
Each of the tabs 3A of the lead 3C1 is cut from the lead frame.
Cut and molded. The lead frame is made of, for example, Cu, Fe-N1 (for example, Ni
It is made of an alloy with a content of 42%. The tab 3A has tab suspensions on each of the short side and long side.
The lead 3D is connected. The outer lead 3C is based on the S semi-standard. The signals applied to each are specified and numbered.
In Figure 2, the upper left corner is terminal 1, and the lower left corner is terminal 10.
The lower right end is the 11th terminal, and the upper right end is the 20th terminal. Regarding the signal applied to this outer lead 3C,
This will be discussed later as there is a trade-off with the external terminal BP mentioned above. The DRAMI, tab 3A, bonding wire 4,
The inner lead 3B and tab suspension lead 3D are resin-sealed parts.
It is sealed with 5. The resin sealing part 5 aims to reduce stress.
For this purpose, phenolic curing agents, silicone rubber and fibres.
It uses an epoxy resin with nine additives. Siri
Cone rubber works to reduce the coefficient of thermal expansion of epoxy resin.
It's useful. The filler is made of spherical silicon oxide particles.
Similarly, it has the effect of lowering the coefficient of thermal expansion. Next, the DRA sealed in the resin-sealed semiconductor device 1
The schematic configuration of Ml is shown in Figure 3 (chip layout diagram).
. As shown in Figure 3, there is a
Six memory cell arrays (MA) 11 are arranged.
The DRAMI of the embodiment includes, but is not limited to, memory.
The cell array 11 has four main memory cell arrays IIA.
It is divided into , and a matte structure is adopted. In other words, the same
In Figure 3, there are two memory cell arrays above and to the side of DRAMI.
A memory cell array I11A is arranged, and two memory cell arrays I1A are arranged below.
These four divided memory cells where the IA is located
Each of the memory cell arrays 11A further includes four memory cell arrays.
It is subdivided into IIB. In other words, DRAMI is 16
Memory cell arrays IIB are arranged. 16 pieces
One memory cell array IIB subdivided into 256
[It is configured with a capacity of Kbitl.] Two of the 16 subdivided memory cell arrays
A column address decoder circuit (Y
DEC) 12 and sense amplifier circuit (SA) 13
Some of them are located. Sense amplifier circuit 13c complementary
It consists of type MISFET (CMO8). A part of the sense amplifier circuit 13 is an n-channel MISFET.
It consists of This is the other part of the sense amplifier circuit 13.
The p-channel MISFET is located opposite the above part.
The memory cell array IIB is arranged at the end of the memory cell array IIB. A complementary data line (
two data lines) extend over the memory cell array 11B.
The DRAM1 of this embodiment is a folded bit.
A line method (two-intersection method) is adopted. The husband of the memory cell array 11B subdivided into 16 pieces
A row address decoder circuit (X
DEC) 14 and word driver circuit (WD) 15
is located. A circuit 1 arranged around these memory cell arrays 11
2 to 16 are configured as direct peripheral circuits of DRAMI.
There is. The upper peripheral circuit 16 is on the upper side of the DRAM, and the upper peripheral circuit 16 is on the lower side of the DRAMI.
A lower peripheral circuit 17 is arranged. Upper side of DRAMl
Two memory cell arrays 11A arranged at the top and two memory cell arrays 11A arranged at the bottom
There is a middle path between the two memory cell arrays 11A placed in the
A peripheral circuit 18 is arranged. In addition, the two memory cells placed above the DRAMI
Two memory cell arrays located on the lower side between array IIA
A central peripheral circuit 19 is arranged between each of the rays IIA.
There is. These peripheral circuits 16 to 19 are connected to DRAMI.
It is configured as a peripheral circuit. Next, we will discuss the specific features of the DRAMI external terminal BP mentioned above.
Regarding the specific circuit layout of the function and the indirect peripheral circuit,
A simple explanation using Figure 4 (enlarged layout diagram of main parts)
Ru. First, the external terminal BP located around the DRAMI is
Here, A0 to A are external terminals BP for address signals.
. Ilo, - 104 are external terminals BP for input/output signals.
be. RAS is the external terminal for the row address strobe signal.
Child BP and CAS are used for column address strobe signals.
This is the terminal BP. WE is external terminal BP for write enable signal, OE is
This is an external terminal BP for the output enable signal*
Vss is a reference potential, for example, for the circuit ground potential 0 [V].
External terminals BP and Vcc are power supply potentials, for example, circuit operating potentials.
5 External terminal BP for [V]. Although not shown, especially near the external terminal BP for input signals.
is equipped with an input protection circuit (electrostatic damage prevention circuit).
Ru. Each circuit of the upper peripheral circuit 16 of the indirect peripheral circuit is
Basically, it is placed near the external terminal BP to which each signal is applied.
has been done. 1601 is a write circuit, 1602 is R
AS system stiffness control circuit. 1603 is the substrate potential
v11 generation circuit, for example -2,5 to -3,5 [V
] This is a circuit that generates a potential of . 1604 is data output
Cover sofa circuit, 1605 is input/output data circuit, 160
6 is a data output control circuit. 1607 is the CAS system stiffness control circuit 608.
light control circuit, 1609 is test mode
control circuit, 1610 is main amplifier control
This is a circuit. 1611 is the IO select circuit, 16
12 is a mat selection and common source drive circuit. 1
614 is the bonding master control circuit, 161B is AT
D circuit, 1617 is X address buffer circuit, 1619
is a Y address buffer circuit. 1620 is the main a
1621 is a nibble counter circuit, 1622 is a nibble counter circuit, and 1622 is a nibble counter circuit.
It is a test logic circuit. In the Nakamichi peripheral circuit 18, 1801 is the Y address buffer.
1802 is the ATD circuit, 1803 is the mat selection
It is a selection circuit. 1804 is an X-system predecoder circuit, 1
805 is an X system redundant circuit, 1806 is a refresh counter
1807 is a column equalization circuit. 1
808 is a decoder monitor circuit, 1809 is an X address bar.
buffer circuit, 1810 is common I10 equalization control circuit
1812 is an X address latch circuit, 1813 is an
This is a refresh control circuit. In the lower peripheral circuit 17, 1701 is a mat selection circuit.
circuit and common source drive circuit, 1702 is Y predeco
It is a reader circuit. 1703 is the X address buffer circuit
, 1704 is a Y address balance circuit. 170
5 is ATD circuit, 170B is Y system redundant circuit, 1707
is an X predecoder circuit. Next, the subdivided memory cell array of the DRAMI
Figure 5 shows the main part of 11B and the main part of its peripheral circuit.
This will be explained using (principal equivalent circuit diagram). As shown in Figure 5, the folded bit line method
DRAM1 that adopts memory cell array (MA) II
In B, complementary data lines DL, DL are extended in the column direction.
It's set. A plurality of sets of complementary data lines DL are arranged in the row direction.
It is placed. Complementary data line DL is sense amplifier circuit
(SA)13. In the memory cell array IIB, the word line WL is
It extends in the row direction intersecting the complementary data line DL.
. A plurality of word lines WL are arranged in the column direction.
However, each word line WL has a row address buffer.
Connected to the poor circuit (XDEC) 14 and selected
It is configured as follows. At the intersection of each of the complementary data lines DL and the word line WL
is 1 [Memory cell that stores bitl information (memory cell)
Element) M is arranged. Memory cell M is a memory cell
Selection n-channel MISFET QJI and information storage capacity
It is composed of a series circuit with element C. MISFETQs for memory cell selection of memory cell M is one
The other semiconductor region is connected to complementary data line DL. The other semiconductor region is one electrode of the information storage capacitive element C.
It is connected to the. The gate electrode is connected to the word line WL.
It is. The other electrode of the information storage capacitive element C is connected to the power supply voltage.
It is connected to the voltage 1/2Vcc. Power supply voltage 1/2Vc
c is an intermediate potential between the reference voltage Vss and the power supply voltage Vcc
For example, it is about 2°5 [V]. Power supply voltage 1/2Vcc is
, the electric field strength applied between the electrodes of the information storage capacitive element C is reduced.
It is possible to reduce the deterioration of the dielectric breakdown voltage of the dielectric film.
Ru. The sense amplifier circuit 13 is connected to the complementary data line DL.
configured to amplify the information of the memory cell M to be transmitted.
It is. The information amplified by the sense amplifier circuit 13 is
Co., Ltd. through n-channel MISFETQy for RAM switch.
The signal is output to the mon data line I10 and the line 10, respectively. Kara
MISFETQy for the system switch is a column address decoder.
It is controlled by a data circuit (YDEC) 12. The common data line I10 is connected to the main amplifier circuit (MA
P ) 1620. main amplifier circuit
1620 is MISFET for switch (no code
), output signal line DOL, DOL, data output buffer 7 times
For output signals through each of the D o B 1604
The terminal (Dout) is connected to BP. wife
The memo signal is further amplified by the main amplifier circuit 1620.
Information on recell M is output signal line DOL, data output buffer
DRAM through the external terminal BP and the external terminal BP.
Output to the outside of I. Next, the memory cell M of the DRAM 1 and the peripheral circuit (separate circuit)
elements that make up amplifier circuits, decoder circuits, etc.)
Explain the physical structure. Memory cell array IIB
The planar structure of the memory cell is shown in Figure 6 (main part plan view).
Cross-sectional structure of array IIB and peripheral circuit elements
is shown in Figure 1 (cross-sectional view of main parts), and on the left side of Figure 1.
The cross-sectional structure of the memory cell M shown is along the I-1 cutting line in FIG.
It shows the cross-sectional structure of the cut part. Also, the right side of Figure 1
The side shows the cross-sectional structure of 0MO8 that constitutes the peripheral circuit.
Ru. As shown in Figures 1 and 6, DRAM1 is made of single crystal silicon.
The p-type semiconductor substrate 20 is made of p-type semiconductor. half
The conductor substrate 20 has a (100) crystal plane as an element formation surface.
For example, it is formed with a resistance value of about 10 [Ω-1].
ing. A part of the main surface of the semiconductor substrate 20 is subjected to ion implantation.
The introduction of impurities of approximately 10° [atoms/d1 or more]
Not done, some areas and at least memory cells
This is an area of array IIB. The introduction of the impurity causes crystal defects.
This causes a large number of defects and leaks the electrical charges that serve as information.
−The area of introduction of impurities is partially restricted due to
There is. Therefore, in order to reduce contamination by heavy metals such as Na,
In addition, the DRAMI of this embodiment is located in a deep region of the semiconductor substrate 20.
Those having a gettering layer are used. Geez!
The taring layer is approximately 10 [μm] from the main surface of the semiconductor substrate 20.
deeper regions (deeper than each of the well regions 21 and 22)
area). Memory cell M (memory cell array) of the semiconductor substrate 20
11) , each formation region of n-channel MISFETQn
A p-type well region 22 is provided on the main surface of the region.
. Formation of p-channel MISFETQp on semiconductor substrate 20
A type well region 21 is provided on the main surface of the region.
. In other words, the DRAM1 of this embodiment has a twin well structure.
It is configured. Between the respective semiconductor element formation regions of the well regions 21 and 22
On the main surface is an insulating film for element isolation (field insulating film) 2
3 is provided. On the main surface of the p'-type well region 22
In this case, a p-type channel layer is formed under the insulating film 23 for isolation between elements.
A topper region 24A is provided. Parasitic MO using the inter-element isolation insulating film 23 as a gate insulating film
8 is easily n-type inverted, so channel stopper region 24A
is provided at least on the main surface of the p-type well region 22.
ing. In the formation region of memory cell M of memory cell array 11
There is a p-type semiconductor region on the main surface of the p-type well region 22.
24B is provided. The p-type semiconductor region 24B is substantially
Generally, it is provided over the entire surface of the memory cell array 11. p
type semiconductor region 24B is the p-type channel stopper region.
It is formed using the same manufacturing process and the same manufacturing mask as 24A, and p
The p-type impurity (
B) 6 peripheral circuits formed by lateral diffusion of
Compared to the constituent n-channel MISFETQn, the memory
Gate width of MISFETQs for memory cell selection of cell M
The dimensions are small. In other words, the p-type impurity
is spread over substantially the entire surface of the memory cell M due to the lateral diffusion of
The p-type semiconductor region 24B is formed.
Ru. This p-type semiconductor region 24B is connected to the p-type semiconductor substrate 20
than the P-type well region 22, which has a higher impurity concentration than the P-type well region 22.
It is formed with even higher impurity concentration. p-type semiconductor region
Area 24B is the threshold of MISFETQs for memory cell selection.
Capacitive element C for information storage can increase low value voltage.
The amount of charge accumulated can be increased. Also, p-type semiconductor
Region 24B is a potential barrier for minority carriers.
It also acts as an area. The memory cell selection MISFETQs of the memory cell M is
Figures 1, 6 and 7 (main parts in a given manufacturing process)
As shown in the top view), the p-type well region 22 (actually
It is formed on the main surface of the p-type semiconductor region 24B). Mail
M I S FETQs for Mori cell selection is for isolation between elements
Defined by insulating film 23 and p-type channel stopper region 24A
configured within the specified area. MI for memory cell selection
SFETQs mainly consists of p-type well region 22, gate insulation
Film 25, gate electrode 26, source region or drain region
It is composed of a pair of n-type semiconductor regions 28. The p-type well region 22 is used as a channel forming region.
It is used. The gate insulating film 25 is the f-type well region 22
It is made of a silicon oxide film formed by oxidizing the main surface of
. The gate electrode 26 is provided on the top of the gate insulating film 6.
Ru. The gate electrode 26 is made of, for example, a polyurethane material deposited by the CVD method.
Formed with crystalline silicon film, approximately 200 to 300 [nm] thick
It is made of thick material. This polycrystalline silicon film reduces resistance
An n-type impurity (P component is AS) is introduced. Also,
The gate electrode 26 is made of high melting point metal (Mo, Ti, Ta
, W) films and refractory metal silicides (MoSi, , TiS)
i2. It may be composed of a single layer of TaSi, WSi2) film.
Furthermore, the gate electrode 26 is formed on the polycrystalline silicon film.
Composite film laminated with melting point metal film and high melting point metal silicide film
It may be composed of The gate electrode 26 is arranged in rows as shown in FIGS. 6 and 7.
It is configured integrally with the word line (WL) 2B extending in the direction.
ing. In other words, each of the gate electrode 26 and the word line 26
are formed of the same conductive layer. Word line 26 is in the row direction
M for memory cell selection of a plurality of memory cells M arranged in
To connect each gate electrode 26 of ISFETQs
It is composed of As shown in FIG. 7, MISFETQ for memory cell selection
The gate length dimension of the gate electrode 26 of s is the width of the word line 26
It is thicker than its dimensions. For example, gate electrode
The gate length of 26 is 1.0 [μm] and the word line
The width dimension is 0.6 [μm]. In addition, the book
In the DRAM1 of the embodiment, the distance between the word lines 26 is
Except for 0.6 [μm], the minimum processing size is 0.8 [μm]
A so-called 0.8 μm manufacturing process is adopted.
. As shown in FIGS. 6 and 7, memory cells M are complementary
One data line DL of data lines (50) and word line z6
the first intersection with the other data of said complementary data line.
line DL and another word line adjacent to the word line 26 in the column direction.
and the second intersection with the lead wire 26. Before
Each word line 26 has substantially the same width dimension and is spaced apart by a predetermined distance.
They are extended in parallel in the row direction while maintaining their dimensions. These two word lines 26 correspond to respective data lines of complementary data lines.
Each data line DL and data line DL protrude in opposite directions.
It extends in the row direction in a zigzag pattern. Said No.
1, the word line 26 is connected to the adjacent
A protrusion is formed along the shape of the memory cell M on the word line 26 side.
26A is provided. Similarly, at the second intersection
Then, a memory cell is installed on the word line 2B side of the other word line 26.
A protrusion 26A is provided along the shape of the ring M. child
The protrusion 26A is substantially a MISF for memory cell selection.
Used as gate electrode 26 of ETQs and word line 2
Make the gate length longer than the wiring width in 6.
It has become. Moreover, the protrusion 26A defines the periphery of the memory cell M.
The insulating film 23 for element isolation and at least the manufacturing process
Just overlap them to the extent that there is a margin for mating.
along the shape of memory cell M (memory cell selection)
protrusion (at the same level as the gate width dimension of MISFETQs)
It's set. In other words. As shown in FIG. 7, MISFETQ for memory cell selection
Simply calculate the wiring width of the word line 26 using the gate length of s.
Compared to the distance A between the word lines 26 in the specified case,
Ensure sufficient separation dimension on the insulating film 23 for isolation between elements.
Therefore, the memory in the extending direction of the word line 26
The cell M interval can be reduced. In this way, (Claim 24-Means 14) memory cell selection
Series circuit between MISFETQs and information storage capacitive element C
A memory cell M formed by a channel is arranged. Folded
In bit line type DRAM1, complementary data
One of the first data lines DL and the first word line of the data line (50)
1st intersection with 26. The other second data line DL of the complementary data lines and the second data line DL
Another second word line 2 adjacent to the first word line 26 in the column direction
disposing the memory cell M at each of the second intersections with 6;
Each of the first word line 26 and the second word line 26 is substantially
parallel to each other with the same width dimension and maintaining the specified separation dimension.
The first data line DL and the first data line DL extend in the row direction.
Each of the two data lines DL protrudes in opposite directions.
jig each of the first word line 26 and second word line 26.
The first word line 26 at the first intersection is extended in a zag pattern.
The second word line 26 side protrudes along the shape of the memory cell M.
(protrusion 26A is provided) and the second intersection.
The first word line 26 side of the second word line 26 is connected to the memory cell M
Make it protrude along the shape of. With this configuration. The first word line 26 and its protrusion 26A form a first intersection.
M I S F E T for memory cell selection in the section
As the gate electrode 2B of Qs, the second word line 26 and
The protrusion 26A selects the memory cell at the second intersection.
used as the gate electrode 26 of MISFETQg.
By the protruding portion, the MISFET for memory cell selection
Since the Qss gate length can be secured, short channels can be
In addition to being able to reduce the channel effect, the first intersection
The interval between the memory cells M arranged at each of the second intersection and the second intersection is
Can be reduced. As a result, the occupancy of memory cell M
Reduce area. In addition, the area occupied by the isolation region between the memory cells M can be reduced.
This makes it possible to improve the degree of DRAMI integration.
can. The n-type semiconductor region 28 is an MIS constituting a peripheral circuit.
Compared to the Go-type semiconductor region (37) of FETQn,
Both sides are connected to the information storage capacitive element C with low impurity concentration.
It is formed by Specifically, the n-type semiconductor region 28 is I
X 10"[atoms/as"] low impurity concentration
It is constructed using the ion implantation method. In other words, n-type semiconductor
In the body region 28, crystal defects occur due to the introduction of impurities.
crystallization by heat treatment after introduction of impurities.
It is formed in such a way that defects can be fully recovered. However,
Therefore, the n-type semiconductor region 28 and the p-type well region 22
Since the amount of leakage current is small at the pn junction of
Stabilizes the charge that serves as information stored in the storage capacitive element C
can be retained. The n-type semiconductor region 28 is self-contained with respect to the gate electrode 26.
Formed by self-alignment, with low impurity concentration on the channel formation region side
Since it is composed of L D D (Lightly
M for selecting memory cells with D oped rain) structure
Configure ISFETQs. Also, one of the memory cell selection MISFETQs (
The n-type semiconductor region 28 (on the connection side of the complementary data line) is of the n-type
It is configured integrally with the semiconductor region 41. The other n-type semiconductor region (the connection side of the information storage capacitive element C)
The region 28 is formed integrally with the n-type semiconductor region 33A.
. The n° type semiconductor region 41 is a complementary data line (50).
and one n-type semiconductor region 28 .
It is formed within the area defined by A. n° type
Semiconductor region 41 has complementary data, I (50) and p-type
It is configured to prevent short circuit with the well region 22.
Ru. The n° type semiconductor region 33A is a stack described later.
The lower electrode layer (33) of the information storage capacitive element C with a double-layer structure
A connection hole 32 for connection with another n-type semiconductor region 28 is provided.
It is formed within a defined area. n-type semiconductor region
Region 33A is the n-type impurity introduced into the lower electrode layer 33.
It is formed by diffusing things. MISFET Qs for memory cell selection
An insulating film 27 is provided on the upper layer of the gate electrode 26.
A side wall is provided on each side wall of the root electrode 26 and the insulating film 27.
A spacer 29 is provided. The insulating film 27 is mainly
Gate electrode 26, information storage capacitor formed thereon
To electrically isolate each electrode (particularly 33) of child C.
It is composed of Side wall spacer 29 is the main
MISFETQs for memory cell selection with LDD structure is constructed in
It is designed to be completed. The insulating film 27, sidewall
The manufacturing method for each of the spacers 29 will be described later.
However, inorganic silane gas and nitrogen oxide gas are
It is formed from a silicon oxide film deposited by a CVD method that uses
There is. This silicon oxide film uses organic silane gas as a source gas.
Compared to the silicon oxide film deposited by CVD method, the lower layer
High step coverage on stepped surfaces and small film shrinkage
Sai. In this way, (10-6) MISFE for memory cell selection
An insulating film 27 is formed on the gate electrode 26 of the TQs, and the
Sidewalls of the gate electrode 26 and the sidewalls of the insulating film 27 above it
sidewall spacer 29 is formed on the DRAMI.
Then, the insulating film 26 on the gate electrode 26. Saidou
Each of the all spacers 29 is heated with inorganic silane gas and oxidized.
Silicon oxide deposited by CVD method using nitrogen gas as a source gas
Consists of a bare film. With this configuration, the gate electrode 26
Each of the upper insulating film 27 and side wall spacer 29
Some silicon oxide films are produced by CVD using organic silane as a source gas.
This reduces the shrinkage of the film compared to silicon oxide films deposited using conventional methods.
Therefore, the insulating film 27 and side wall space can be
The separation between the gate electrode 26 and the gate electrode 26 is reduced.
The link between the other conductive layers (for example, the lower electrode layer 33)
It is possible to prevent electrical leaks and improve electrical reliability.
In both cases, the insulating film 27 on the gate electrode 26 and the side wall
The step cover of the silicon oxide film which is each of the wall spacers 29 is
The high barrier improves the uniformity of the silicon oxide film thickness.
, dielectric strength can be improved. Also, step cards
Because of the high barrier, the required
It is possible to reduce the thickness of the deposited film, reduce the level difference, and reduce the thickness of the lower electrode.
Processing of the layer 33 becomes easier. The information storage capacitive element C of the memory cell M is. Figures 1, 6 and 8 (main points in a given manufacturing process)
As shown in (partial plan view), the lower electrode layer 33 and the dielectric
The body 114134 and the upper electrode layer 35 are laminated in sequence.
It is configured. The information storage capacitive element C is a so-called stack.
It is composed of a double layered structure (layered type: 5TC). The lower electrode of this stacked structure information storage capacitive element C
A part (center part) of the layer 33 is MISF for memory cell selection.
Connected to the other n-type semiconductor region 28 of the ETQs
. This connection is made through a connection hole 31A formed in the interlayer insulating film 31.
and the connection hole 3 defined by the sidewall spacer 29
It is carried out through 2. Opening support in the column direction of the connection holes 32
is the gate electrode of MISFET QS for memory cell selection.
2B, and the respective separation dimensions of the adjacent word lines 26.
stipulated. The opening size of the connecting hole 31A and the opening size of the connecting hole 32
The difference is at least due to the mask alignment allowance dimension in the manufacturing process.
It is larger than the corresponding amount. of the lower electrode layer 33
The other part (peripheral part) is the husband of the gate electrode 26 and the word line 26.
It is stretched to the top of each. The interlayer insulating film 31 is connected to the underlying insulating film 27 and the side window.
All spacers 29 are made of the same insulating film as each other.
There is. In other words, inorganic silane gas and nitrogen oxide gas are
It is formed from a silicon oxide film deposited by the CVD method using a gas.
ing. The lower electrode layer 33 is made of polycrystalline material deposited by CVD, for example.
It is formed from a silicon film, and this polycrystalline silicon film has a
n-type impurity (As or P) is introduced at a high concentration.
. The lower electrode layer 33 utilizes the stepped shape of the base and
Stacked information storage capacitive element C using walls
In order to increase the amount of charge accumulation, for example, 200 to 400 [
It is formed with a relatively thick film thickness of about 100 nm. The planar shape of the lower electrode layer 33 is shown in FIGS. 6 and 8.
As shown, the complementary data lines (50) extend in the column direction.
It consists of a long rectangular shape. As shown in Figure 8,
Each lower layer electrode arranged in the row direction in which the word line 26 extends
Layer 33 is at or near the minimum additional dimension in the manufacturing process.
It is formed according to the processing dimensions. Similarly, the complementary data line (
Each lower electrode layer 33 is arranged in the column direction in which 50) extends.
Of these, it is not for the connection side of the complementary data line, but for isolation between elements.
The minimum stress is applied between the lower electrode layers 33 with the insulating film 23 interposed therebetween.
It is formed with the same size or a processing size close to it. this
On the connection side of the complementary data line, the lower electrode
Between the layers 33 is an n-type MISFET QS for memory cell selection.
Connection region between semiconductor region 28 and complementary data line (50)
, the dielectric strength between the upper electrode layer 3S and the complementary data line (50)
pressure, the overlap between the lower electrode layer 33 and the upper electrode layer 35, and
Dielectric strength voltage between lower electrode layer 33 and complementary data line (5o)
spaced apart by a distance equal to the distance that ensures the Below this
The layer electrode layer 33 includes a complementary device with the n-type semiconductor region 28.
A region formed in a planar rectangular shape on the connection side with the data wire (50).
A correction pattern 33A protruding from the area in the plane direction is provided.
It is. Etching mask for processing the lower electrode layer 33
(photoresist film) in the connection area.
Diffraction phenomenon and words occurring in a region where the distance between the pole layers 33 is wide
The size is reduced due to the reflected light from the step of line 26.
Well, for this reason, the size of the lower electrode layer 33 is set to a predetermined value.
Because it is smaller than the value, it is suitable for storing information in a stacked structure.
The amount of charge stored in the capacitive element C decreases. Therefore, the correction pattern
The lower layer electrode 33A is designed in advance to account for the reduction in size.
The structure is such that the size of the pole layer 33 is increased. The correction pattern 33 is arranged between the lower electrode layers 33 in terms of layout.
It is placed on the connection side where there is plenty of room, but it is limited to this.
may be placed on the opposite side of the above position;
, the actual planar shape of the lower electrode layer 33 has rectangular corner portions.
It falls off quite a bit, so it is shaped to have a round shape overall.
be done. In this way, (1-1) MISFET for memory cell selection
Series of Qs and stacked structure information storage capacitive element C
In a DRAM1 that constitutes a memory cell with a circuit, the above-mentioned
Lower electrode layer 3 of stacked structure information storage capacitive element C
3, a correction pattern 33A is constructed to increase the surface area.
to be accomplished. This reduces the distance between adjacent lower electrode layers 33.
In the large area (complementary data line side), photolithography
Diffraction phenomenon during exposure of graphics technology and from word line 26
An etching process for processing the lower electrode layer 33 by the reflected light of
This can reduce the reduction in the size of the tinging mask (
(The size has been corrected in advance for the size reduction), so the lower layer
The surface area of the electrode layer 33 is secured, and the information of the stacked structure is
The amount of charge stored in the storage capacitive element C can be increased.
. As a result, alpha-ray soft error resistance has been improved, and memory cell
The area of memory M can be reduced, increasing the degree of integration of DRAM1.
can do. The dielectric film 34 is basically a lower electrode layer (a polycrystalline silicon film).
) Silicon nitride deposited on the upper layer (on the surface) of 33 by CVD method
The silicon nitride film 34A is oxidized with acid at high pressure.
It has a two-layer structure in which silicon oxide films 34B are laminated. In reality, the dielectric film 34 is
A natural silicon oxide film (less than 3 [nm1)
(not shown because the film thickness is always thin) is formed automatically.
Natural silicon oxide film, silicon nitride film 34A, silicon oxide film 34B
It has a three-layer structure in which each layer is sequentially laminated. Said invitation
The silicon nitride film 34A of the electric film 34 is deposited by the CVD method.
Therefore, the crystals of the underlying polycrystalline silicon film (lower electrode layer 33)
A professional that is independent of the substrate, unaffected by the condition or shape of the step.
It can be formed under cess conditions. In other words, silicon nitride film
34A is an oxide formed by oxidizing the surface of a polycrystalline silicon film.
Compared to silicon film, it has higher dielectric strength and fewer defects per unit area.
Since the number is small, leakage current is very low, and
The silicon nitride film 34A has a higher dielectric constant than a silicon oxide film.
There are signs. The silicon oxide film 34B is made of a very high quality film.
Therefore, the characteristics of the silicon nitride film 34A can be
performance can be further improved. Also, detailed later
Ruga. The silicon oxide film 34B is subjected to high pressure oxidation (1.5 to 10 [atmospheres]
), the oxidation time is shorter than that in normal pressure oxidation.
It can be formed in a shorter heat treatment time. Silicon oxide film 3
4B is thin (for example, 2 [nml or less)] and at normal pressure (1 [atm.
]) oxidation, the heat treatment time is within the allowable range.
It can also be formed by normal pressure oxidation. The dielectric film 34 extends along the top surface and sidewalls of the lower electrode layer 33.
It is provided using the side wall portion of the lower electrode layer 33.
This increases the area in the height direction. The area of the dielectric film 34
The increase is due to charge storage in the stacked structure information storage capacitive element C.
It is possible to improve the stacking capacity. The planar shape of this dielectric film 34 is the planar shape of the upper electrode layer 35.
It is defined by the shape and has substantially the same shape as the upper electrode layer 35.
has been completed. The upper electrode layer 35 is connected to the lower electrode layer with a dielectric film 34 interposed therebetween.
It is provided above the pole layer 33 so as to cover it. upper layer
The electrode layer 35 has a stacked structure of other adjacent memory cells M.
The structure is integrated with the upper electrode layer 35 of the information storage capacitive element C of the structure.
has been completed. The upper electrode layer 35 is supplied with a power supply voltage of 1/2 Vc.
c is applied. The upper electrode layer 35 is formed by, for example, the CVD method.
It is formed from a polycrystalline silicon film deposited in
An n-type impurity is introduced to reduce the resistance value. Up
The layer electrode layer 35 is, for example, equivalent to or equivalent to the lower electrode layer 33.
It is formed with the following film thickness. In this way, (11-7) interlayer insulating film (base insulating film) 3
1, the lower electrode layer 33 formed on the interlayer insulating film 31
A dielectric [3] formed on the surfaces of the upper and lower electrode layers 33
4 and an upper electrode layer 35 formed on this dielectric film 34
A stacked structure information storage capacitive element C consisting of
In the DRAMI that has the stacked structure information
The dielectric film 34 of the storage capacitor C is made of a silicon nitride film 34A.
The interlayer insulating film 31 is made of an inorganic silica.
by CVD method using nitrogen gas and nitrogen oxide gas as source gas.
Consists of a deposited silicon oxide film. With this configuration, the above
Dielectric film 34 of stacked structure information storage capacitive element C
The film shrinkage of the interlayer insulating film 31 is reduced, and the dielectric
The stress generated between the body film 34 and the interlayer insulating film 31 is
This prevents damage to the dielectric film 34.
However, leakage current between the lower electrode layer 33 and the upper electrode layer 35
This can prevent electrical current and improve electrical reliability.
Secondly, the step coverage of the interlayer insulating film 31 is high.
In this way, the uniformity of the film thickness of the interlayer insulating film 31 is improved, and the interlayer insulating film 31 is
The lower electrode layer 33 on top of 31 and the conductive layer below it (for example, a gate)
26) and the word line 26).
be able to. The memory cells M are shown in FIGS. 1, 6, 7, and 8.
Another memory cell M adjacent in the column direction as shown in
There are nine connected. In other words, two menus adjacent in the column direction
Morisel M is MISFETQ for selecting each memory cell.
One of the n-type semiconductor regions 28 of s is integrally constructed, and that part
It consists of a reversal pattern centered around minutes. These two
Memory cells M are arranged in the row direction, and these two memory cells
A cell M and two other memory cells M adjacent in the row direction are connected to each other in a column.
They are arranged with a 1/2 pitch shift in the direction. One of the memory cell selection MISFETQs of memory cell M
In the other n-type semiconductor region 28, as shown in FIGS. 1 and 6,
A complementary data line (DL) 50 is connected to the line. phase
The complementary data line 50 is connected to each of the interlayer insulating films 36, 39, and 40.
n-type semiconductor region 28 through connection hole 40A formed in
It is connected to the. Complementary data line 50 and n-type semiconductor region
The connection with the region 28 is made by interposing the strip-shaped semiconductor region 41.
It is being said. Each of the interlayer insulating films 36 and 39 is deposited by, for example, a CVD method.
It is formed of a stacked silicon oxide film. The interlayer insulating film 40 is
Acids containing phosphorus and boron that can be flattened by flow
It is composed of a silicon oxide film (BPSG). the layer
The interlayer insulating film 39 is used to ensure dielectric strength and to provide insulation between the upper layers.
B and P introduced into the insulating film 40 leak into the element.
It is established for the purpose of preventing. The complementary data line 50 is a transition metal film (barrier metal).
film) 50A, aluminum film or aluminum alloy film 5
0B and transition metal film (protective film) 50c are sequentially laminated.
It has a three-layer structure. Lower transition metal film 50 of the complementary data lines 50
A shows the aluminum film 50B and the n-type semiconductor region 28 (actual).
In fact, single-crystal silicon is formed at the connection part with the strip-shaped semiconductor region 41).
To prevent precipitation and increase in the resistance value of the connection part.
It is composed of In other words, the lower transition metal film 50A is
It is used as a so-called barrier metal film. This lower layer
The transition metal film 50A is an aluminum film 50B as an upper layer.
Aluminum can be formed before forming.
CV at a temperature close to or higher than the melting temperature of the film 50B
Method D can be used. Specifically, the underlying transition gold
As the main film 50A, a WSi2 film deposited by CVD method is used.
. Further, the lower transition metal film 50A is, for example, a TaSi3 film.
or a TiN film (that is, the transition of this example).
Metal films include transition metal films, transition metal silicide films, and transition metal nitride films.
lower transition metal film deposited by CVD method
50A is suitable for areas with large step shapes on the base, especially complementary
Significantly increased step coverage at the connection part of data line 5o
can be improved. Note that the lower transition metal film 50
A has a low resistance value when deposited by low-temperature sputtering.
High temperature of about 900 ['C] for the purpose of reducing and stabilizing
The lower transition metal film 5 must be subjected to a heat treatment of
0A is p in the n-type semiconductor region 28 and peripheral circuit region.
It is connected to the °-type semiconductor region (38) and further includes an interlayer insulating film.
40, so the high temperature heat treatment is unnecessary.
This causes interdiffusion of pure substances and increases the resistance value at each connection.
Despite this point, the lower transition metal film 50
A is 650 ['C] or higher, which does not require heat treatment to lower resistance.
It is desirable to form by CVD method at 900 ['C] or less.
Yes. Middle layer aluminum film 50B of the complementary data line 50
is basically used as the main part of wiring, and has low resistance.
It is made of good material. As aluminum film 50B
When using that alloy film, Cu or C is added to the aluminum film.
Add u and Si. CU is a migration phenomenon
For example, about 0.5 [wt%]
It has been added to a certain degree. Si reduces alloy spike phenomenon
For example, about 1 to 1.5 [wt%]
has been added. The aluminum film 50B is formed by sputtering, for example.
It is deposited using the ta method. The upper transition metal film 5oc of the complementary data line 50 is mainly composed of
Aluminum hillock deposited on the surface of aluminum film SOH
It is formed for the purpose of reducing the phenomenon. Further, the upper layer transition metal film 50c has a complementary data line 50.
In the case of the surface reflectance of the aluminum film 50B,
etching to process the complementary data line 5o.
Is there a diffraction phenomenon or a step difference between the adjacent substrates when the mask is exposed?
The size of the etching mask is reduced by the reflected light from the etching mask.
The structure is designed to reduce the occurrence of upper layer
The transition metal film 5oc is different from the underlying transition metal film 50A.
, since it is deposited after forming the aluminum film 50B.
, low temperature sputtering that does not melt the aluminum film 50B
There are nine deposited by law. The upper transition metal film 50C is complementary
There is no need to substantially lower the resistance value of the data line 50.
Therefore, high-temperature heat treatment is performed after deposition by sputtering.
This upper layer transition metal film 50C, which is not necessary, is M o S
i, formed of a membrane. In addition, the upper transition metal film
50C is a transition metal film other than the above, such as WSi, 'r
It may be formed using a 5i21T'i S L film or the like. In this way, (3-2) the base surface having a stepped shape (4
0) DR on which the complementary data line (wiring) 50 is extended
AMl, the complementary data line 50. Transition metal film 50A deposited by CVD method, deposited by sputtering method.
Each of the laminated aluminum films (or its alloy films) 50B
It consists of a composite membrane that is sequentially laminated. This configuration allows
The aluminum film 50B has a small resistance value and a complementary data
Since the signal transmission speed of the tangent wire 50 can be increased,
Aiming to increase the speed of information writing and reading operations.
In addition, the transition metal film SOA can be
High step coverage in stepped areas and complementary data
Since disconnection defects of the wire 50 can be reduced, electrical
Reliability can be improved. In addition, the complementarity data
The transition metal film 50A below the tangent wire 50 is the n-type semiconductor region 2.
To prevent the precipitation phenomenon of Si at the connection part with Si such as 8.
can be done. (4-3) The complementary data line 50 is formed using a CVD method.
The transition metal film 50A deposited by
Luminium film 50B, transition metal film deposited by sputtering method
It is composed of a composite membrane with a three-eye structure in which 50G is sequentially laminated.
Ru. With this configuration, the upper layer of the complementary data line 50
Transfer metal film 50G prevents aluminum hillock from occurring.
can be stopped. Further, the transition metal film 50C in the upper layer of the complementary data line 50 is
Reduce the reflectance of the surface of aluminum film 50B or its alloy film
etching mask for processing complementary data lines 50;
Diffraction phenomenon during exposure and difference in surface level when forming a
Excessive exposure due to reflected light can be reduced,
The processing accuracy of the complementary data line 50 can be improved.
. Further, the transition metal film 50C in the upper layer of the complementary data line 50
is compared to the melting point of the underlying aluminum film 50B.
Aluminum films because they can be deposited at lower temperatures
50B will not be melted. The complementary data line 50 is the first layer in the manufacturing process.
It is formed by a wiring forming process. This complementarity data
The line 50 is used to alleviate the step shape peculiar to the multilayer wiring structure.
Then, the second layer wiring formation process in the manufacturing process of the upper layer.
It is formed with a thinner film thickness than the wiring (53) formed in the process.
It is. Note that the DRAMI in this example has a two-layer wiring structure.
(2-layer aluminum wiring structure). Also
, DRAM1 has a three-layer gate wiring structure (three-layer polycrystalline silicon film).
structure). As shown in FIGS. 1 and 6, the complementary data line 5
A shunt wire is formed on the upper layer of 0 with an interlayer insulating film 51 interposed therebetween.
The code line (WL) 53 is configured to extend in the row direction.
ing. Although the shunt word line 53 is not shown, the number of shunt word lines 53 is
In a predetermined area corresponding to every ten to several hundred memory cells M.
and is connected to the word line (W L ) 26 as described later.
It is. Word line 26 is connected to memory cell array IIB.
The shunt is divided into multiple parts in the extending direction, and the shunt
The word line 53 is connected to each of the plurality of divided word lines 2.
6. The shunt word line 53 is
By reducing the resistance value of the lead wire 26, information writing operation and information reading are possible.
In each operation, the selection speed of the memory cell M can be increased.
It is configured so that it can be The interlayer insulating film 51 is made of silicon oxide, as shown in FIG.
Film (deposited type insulating film) 51A, silicon oxide film (coated type insulating film)
) SIB, silicon oxide film (deposited insulating film) 51c, respectively.
It consists of composite membranes laminated in sequence. Silicon oxide film 51A in the lower layer of the interlayer insulating film 51, oxidation in the upper layer
Each of the silicon films 51C is made of acid deposited by plasma CVD method.
Formed with silicon oxide film. The middle layer silicon oxide film 51B is 5OG.
(Spin On Glass)
It is formed from a treated silicon oxide film. This middle layer of silicon oxide
The base film 51B is for the purpose of flattening the surface of the interlayer insulating film 51.
It is formed. The middle layer silicon oxide film 51B is
After post-bake treatment, the entire surface is etched.
It is formed so that it is embedded only in the recess of the stepped part.
. In particular, the middle layer silicon oxide film 51B is the first layer wiring (5
0) and the second layer wiring (53) (connection hole 5
In 2), it is removed by etching treatment so that it does not remain.
has been left behind. In other words, the silicon oxide film 50B in the middle layer contains water.
The aluminum film of the wiring (each of 50 and 53)
The structure is designed to reduce corrosion. The shunt word line 53 is connected to the complementary data line 5.
It is formed with a cross-sectional structure similar to that of 0, and is made of transition gold.
Metal film 53A, aluminum film (aluminum alloy film) 5
Three-layer structure in which 3B and 53G transition metal films are sequentially laminated.
It is composed of a composite membrane. Shunt word line 53
The husband of the lower transition metal film 53A and the upper transition metal film 53C
The complementary data lines 50, which are the lower layer wiring, are connected to aluminum
Since the film 50B is formed, it can be deposited at low temperature.
It is deposited using the putter method. Lower layer transition metal film 53A,
Each of the upper transition metal films 53C is, for example, a MoSi film.
It is formed. The lower layer transition metal film 53A mainly contains the lower layer transition metal film 53A.
Shaped to reduce the resistance value of the connection part with the wiring (50)
has been completed. The upper transition metal film 53C is mainly made of aluminum.
To reduce chromatic rock and reduce reflectance to reduce diffraction phenomena.
Designed to reduce Shunt word line 53
As mentioned above, the lower layer wiring, for example, the complementary data line 53
It is formed with a thicker film than the film thickness, and is designed to reduce the resistance value.
It is composed of Each of the aforementioned word line 26 and shunt word line 53
The connections are shown in Figure 9 (top view of the connection area) and Figure 10 (Figure 9).
The intermediate conductor is shown in the cross-sectional view taken along the
This is done with an electric layer 500 interposed. That is, the shunt word line 53 passes through the connection hole 52.
and is once drawn down to the intermediate conductive layer 50D. The connection hole 5
2 is a substantially vertical step formed by anisotropic etching
With the lower connecting hole 52A having a shape and isotropic etching
The upper connection hole 52B has a gently stepped shape.
has been completed. In other words, the connection hole 52 is
Improves the step coverage of the lead wire 53 and reduces disconnection defects.
It is constructed in such a way that it can be reduced. and the intermediate conductive
The layer 50D is drawn in the extending direction of the shunt word line 53.
A contact that is stretched out and located at a different position from the connection hole 52.
It is connected to the word line 26 through the connecting hole 40A. During ~
The interlayer conductive layer 500 is the same conductive layer as the complementary data line 50 or
This is formed in the first layer wiring formation process. this middle
The conductive layer 50D connects the shunt word line 53 and the word line 2.
By reducing the step shape when connecting with 6, the shunt workpiece is
It is configured to prevent disconnection of the lead wire 53. Connection portions of the intermediate conductive layer 50D and the word line 26
There is a stacked structure around the connection hole 40A.
The upper electrode layer 35 of the information storage capacitive element C is a memory cell
It has been stretched from Ray IIB. Connection hole 4 connecting intermediate conductive layer 50D and word line 26
0A was formed on the stretched upper electrode layer 35.
Located within the area provided with opening $5A
. The memory cell array IIB has an MI for memory cell selection.
SFETQs, stacked structure information storage capacitive element C
Each area is stacked to make the step shape larger than other areas.
Therefore, as mentioned above, the shunt word line 5
3. An upper electrode layer 35 is provided in each connection region of the word line 26.
It's stretched. In other words, this upper electrode layer 35
B. Between each of the connection areas, the first wiring (
For example, the intermediate conductive layer 50D) 50, the second layer wiring
The surface of each underlying layer (for example, the shunt word line 53)
It is constructed so that the surface can be flattened. In this way, (22-13) complementary data line 5° and word
A plurality of memory cells M are arranged at the intersection with the lead line 26.
The upper layer of the word line 26 constitutes the Mori cell array 11.
area other than the memory cell array 11 (actually memory cell array 11).
The word line 26
A DRA in which a shunt word line 53 connected to
In Ml, the word line 26 and the shunt word line
A step-relaxing layer (drawn out upper layer) is placed around the connecting part with
A layer electrode layer 35) is provided. With this configuration, the word
Around the connection part between the line 26 and the shunt word line 53
The memory cell array 11 (actually memory cells M are arranged)
area) and reduce the level difference between each area.
Wiring such as the shunt word line 53 that extends
Photolithography for processing connection holes (40A and 52) to connect
The above-mentioned method can stabilize the lithography technology.
Reduces disconnection and continuity defects at the stepped portion of the wiring, and improves manufacturing efficiency.
The manufacturing yield can be improved. Further, the step relief layer (35) is a stack of the memory cell M.
Same as the upper electrode layer 35 of the information storage capacitive element C with the double structure.
Formed with one conductive layer. With this configuration. The step relief layer can be formed of the upper electrode layer 35.
Therefore, the DR is
The number of AMI manufacturing steps can be reduced. As shown in FIGS. 9 and 10, the upper layer electrode
The layer 35 includes the memory cell array IIB and the shunt wire.
between each of the connection areas between the word line 53 and the word line 26.
power supply wiring 50 to which power supply voltage 1/2 Vcc is applied.
Connected to E. Figures 6 and 11 (cut along the ■-■ cutting line in Figure 6)
(This figure omits the layers above the wiring 50.)
As shown, at the peripheral edge of memory cell array IIB,
A guard ring area OL is provided. guard ring
Region GL surrounds memory cell array IIB.
, Mainly substrate potential generation circuit (V, generator circuit) 1
It is configured to capture minority carriers released from 603.
has been completed. The guard ring region GL is located between the memory cell array IIB and the periphery.
placed between the circuit. Guard ring area GL is
, element isolation insulating film 23 and P-type channel stopper region
In the region defined by region 24A, an f-type well region
n-type semiconductor region 28 (and go
type semiconductor region 33A). In other words, Gar
The doling region GL is formed using the shape of the memory cell M.
Make a note so as not to disturb the repeating pattern of Morisel M.
Gate width dimensions of MISFETQs for recell selection and actual
are constructed with the same dimensions. To guard ring area GL
Although not shown, the power supply is connected via the power supply wiring (50).
A potential of 1/2 Vcc is applied. Memory cell array IIB, the guard ring region OL
A step relaxation layer (380, 35D) is arranged between each.
In this example, the zero step difference relaxation layer is arranged in two steps.
ing. In other words, the one-step difference relaxation layer is the memory cell array II.
From the B side toward the guard ring area GL side, the first step
Japanese layer (33D and 35D), second step relaxation layer (35D
) are arranged in sequence. The first step relaxation layer (33D and 35D) has a two-step structure.
has been done. Below the first step relaxation layer (33D and 35D)
The step-reducing layer 33D has a stacked structure for storing information.
It is composed of the same conductive layer as the lower electrode layer 33 of the quantum element C, and the upper
The layer step relaxation layer 35D is the same conductive layer as the upper electrode layer 3s.
It is configured. 2nd step relief layer (35D or 33D)
) is the information storage capacitive element C of the stacked structure.
The upper electrode layer 35 is made of the same conductive layer. wife
The one-step difference relaxation layer (330, 35D) is a memory cell array.
Step shape from IIB to guard ring area GL
It is configured to make it smaller. In this way, (18-10) MISF for memory cell selection
Information on ETQs and the stacked structure layered on top of them
A memory cell M consisting of a series circuit with a storage capacitive element C is
A memory cell array IIB arranged in rows and columns is constructed.
Peripheral circuits are arranged in the peripheral area of the memory cell array IIB.
In the installed DRAM, the memory cell array II
For information storage of the stacked structure between B and the peripheral circuit.
Lower electrode layer 33 of capacitive element C. Upper electrode layer 35 or the former
A step relaxation layer (33D, 3
5D). With this configuration, the memory cell array
The step portion between A 11B and the peripheral circuit is covered with the step relieving layer (
33D, 350) and extend over the respective regions.
lines (complementary data line 50 and shunt word line 53)
It is possible to stabilize the photolithography technology used for processing.
This reduces disconnection defects at the stepped portion of the wiring.
Therefore, manufacturing yield can be improved. (19-11) The memory cell array IIB and peripheral
The stacks are connected to the side circuits from the former to the latter.
The lower electrode layer 33 of the information storage capacitive element C with the double structure
The first level difference relaxation layer is formed of the same conductive layer as the upper electrode layer 35.
layers (33D and 35D), the lower electrode layer 33 or the upper layer
A second step relaxation layer (
33D or 35D) are arranged in sequence. This configuration
and a stage between the memory cell array 11B and the peripheral circuit.
The difference portion is formed by forming the first step-difference relaxation layer (33D and 35D), the second
Relaxation is performed step by step with each step relaxation layer (33D or 35D).
This can further improve manufacturing yields.
I can do that. (20-12) Memory cell array IIB and peripheral circuits
A guard ring area OL is arranged between the road and the step.
The relaxation layer (33D, 350) is the guard ring region OL.
Place it in With this configuration, the step relief layer (33D
, 35D) as guard ring territory.
Since the area occupied by area GL can be used for both purposes, it is possible to reduce the level difference.
Reduce the area occupied by the Japanese layer (33D, 35D) and increase the degree of integration.
can be improved. of the DRAM1 including the upper layer of the shunt word line 53.
Substantially the entire surface is covered with a passive base as shown in Fig. 1 above.
8154 is provided. First, it is illustrated in the detailed review.
However, passivation 1154 will be explained later.
Sea urchin (see Figure 15) Silicon oxide deposited by CVD method! I
I (54A), silicon nitride deposited by plasma CVD method
base IC54B), coated resin film (e.g. polyimide),
It consists of a composite film in which each of the mid-based resin films 54C) is laminated in sequence.
has been completed. Resin film on the upper layer of the passivation film 54
(54G) is mainly memory cell array 11B, direct peripheral
Formed for the purpose of reducing the incidence of alpha rays into each part of the circuit
has been done. In other words, the resin film 54C has an α-ray soft error.
It is configured to improve pressure resistance. Note that the resin film 5
4C is connected to the external terminal BP located around the DRAMI.
The area where the bonding wire 4 is connected is not removed.
It is. A detailed explanation of this area will be given later. The CMOS constituting the peripheral circuit of the DRAMI is
It is configured as shown on the right side of Figure 1. 0MO8 n-channel MISFETQn is isolated between elements.
with insulation 1123 and p-type channel stopper region 24A.
Within the surrounding area, the F-type well region 22
It is configured on the main surface. n-channel MISFETQn
mainly includes the f-type well region 22, the gate insulation 1125 .
Gate electrode 26. One area is the source region and the drain region.
A pair of n-type semiconductor regions 28 and a pair of go-type semiconductor regions 37
It consists of p-type well region 22. Gate insulating film 25, gate electrode
26 and n-type semiconductor region 28, each of the memory cell
Constructed in the same manufacturing process as the selection MISFETQs,
They have qualitatively similar functions. That is, n channel M
ISFETQn has an LDD structure. The Go-type semiconductor region 37 with high impurity concentration is a source region and a drain region.
configured to reduce the respective resistivity values of the in-area.
There is. The n″ type semiconductor region 37 is located on the sidewall of the gate electrode 26.
to the side wall spacer 29 formed by self-alignment.
defined and self-aligned to gate electrode 28
is formed. In contact with the Go-type semiconductor region 37 used as a source region.
Reference voltage V! through the connecting hole 40A! Wiring with 18 applied
50 are connected. used as drain area
The output signal is connected to the green semiconductor region 37 through the connection hole 40A.
sr1″ type semiconductor region 3 to which wiring 50 for
7 and the wiring 50 are formed within the area defined by the connection hole 40A.
electrically connected through the Go-type semiconductor region 41
has been done. The wiring 50 is the same as the complementary data line 50.
It is made of a conductive layer. 0MO8 p-channel MISFETQP has isolation between elements.
In the area surrounded by the insulating film 23,
It is formed on the main surface of the well region 21. p channel M
ISFETQP mainly consists of an n-type well region 21, a gate
The gate insulating film 25, the gate electrode 26, the source region and the drain
A pair of p-type semiconductor regions 30 which are in regions and a pair of P
It is composed of a °-type semiconductor region 38. n-type well region 21, gate insulating film 25 and gate voltage
Each of the poles 26 is connected to the memory cell selection MISFETQ.
s, n channel M I S F E T Q n, respectively.
It has substantially the same function as . The p-type semiconductor region 30 with a low impurity concentration is a p-type semiconductor region with an LDD structure.
Configure channel MISFETQp. as a source area
There is no contact with the P° type semiconductor region 38 with high impurity concentration used.
Wiring 5 to which power supply voltage Vcc is applied through through hole 40A
0 is connected. p used as drain region
The output terminal is connected to the °-type semiconductor region 38 through the connection hole 40A.
Output signal wiring configured integrally with signal wiring 50
50 are connected. This output signal wiring 50 is passed through the connection hole 52.
Upper layer wiring 53 is connected. The wiring 53 is connected to the
It is formed of the same conductive layer as the word line 53 for the client. FIG. 12 shows a cross-sectional structure including the output stage circuit of the DRAM1.
(Cross-sectional view of main parts).
1, memory cell M of memory cell array IIB is
It is shown. As mentioned above, the memory cell M is basically p
- type well region 22 . Me-shaped well area
22 is a do type formed with a lower impurity concentration than that ◆
Forming a potential barrier region between the semiconductor substrate 20
Therefore, the α-ray soft error resistance can be improved. Mail
MISFETQs for memory cell selection of Morisel M is
Formed by the lateral diffusion of the p-type channel stopper region 24A.
formed on the main surface of the p-type semiconductor region 24B.
Therefore, the impurity concentration is higher than that of the V-type well region 22.
formed in the area. This p-type semiconductor region 24A is
As mentioned above, the lateral direction of the p-type channel stopper region 24A
Although the impurity concentration is increased to some extent due to the diffusion of
selectively newly added only to memory cell array IIB in response to
Introducing p-type impurities (threshold voltage adjustment impurities)
The purity concentration can be made even higher; the introduction of impurities is an example.
For example, the p-type semiconductor region 24B is formed by ion implantation.
M I S F E T Q s threshold for resell selection
The DRAMI memory of this embodiment has a high value voltage.
The gate length of MISFET Qa for Mori cell selection is 1.0 [μ
m] (the effective channel length is 0.7 to 0.8 [μml
), the threshold voltage is set to a high value of approximately 0.8 [V] or more.
has been done. MI for memory cell selection of the memory cell M
SFETQs are connected to power supply wiring (Via or Vcc) and unselected.
selected word line 26 or shunt word line 53 (V
Noise generated in the power supply wiring at the intersection with
based on the word line 26 or the shunt word
The potential of line 53 will float, causing malfunction (erroneous conduction).
, the threshold voltage is set high. Such non-selection
The phenomenon of malfunction of memory cell M in the selected state has become more common with higher integration.
It occurs noticeably. In FIG. 12, the right side shows peripheral circuits as in FIG. 1.
0MO8 is shown. This CMOS n-channel M
Each of ISFETQn and p-channel MISFETQp is
, column address decoder circuit 12, sense amplifier circuit
Direct peripheral circuits such as 13 and indirect peripheral circuits such as clock circuits
used on the road. The n-channel MISFETQn is
In order to reduce the short channel effect associated with high integration, p-
The p-type semiconductor substrate 20 has a higher impurity concentration than the p-type semiconductor substrate 20.
is provided in the control area 22. In addition, n-channel MIS
FETQn, especially a part of the direct peripheral circuit (α-ray soft error)
n-channel MIS F E (circuit where you want to ensure voltage resistance)
Similar to the memory cell M, TQn is an r-type well region 22.
It is set in. The n-channel MISFETQn is D
Configured as a standard MISFET in RAMI
and introduced into the p-type well region 22 and its main surface.
The threshold value can be uniquely determined by the concentration of impurity for threshold voltage adjustment.
Voltage is set. The n-channel MISFETQn depends on the circuit used.
Although the gate length is different, it is converted using a gate length of 1.0 [μm].
(effective channel length is 0.7 to 0.8 [μml)]
, the threshold voltage is set in the range of approximately 0.3 to 0.8[V].
has been established. In other words, the n-channel MISFETQn is
, especially since high-speed operation performance is required, the transfer conductor
The threshold voltage is set to increase the
. In the center of FIG. 12, there is an n-channel that constitutes the output stage circuit.
channel MISFETQo. This n channel M
ISFETQo is basically the n-channel of the peripheral circuit.
It consists of an LDD structure similar to MISFETQn.
Ru. In other words, the n-channel MISFETQo is p-type
Semiconductor substrate 20. gate insulating film 25, gate electrode 26,
A pair of n-type semiconductor regions that are a source region and a drain region
region 28 and a pair of Go-type semiconductor regions 37.
. The p-type semiconductor substrate 20 is smaller than the p-type well region 22.
All are formed with low impurity concentration, and the n-channel MISFE
It is used as a channel forming region of TQO. this
For example, the n-channel MISFETQo is a push-pull type
It constitutes the output stage circuit. n-channel MISFETQ
o varies depending on the circuit used and the required specification form.
The gate length is different, but the gate length is 1.0 [μm].
(effective channel length is 0.7 to 0.8 [, um]), L
The threshold voltage is set to a low value of approximately 0.3 [V] or less.
It is. In other words. n-channel MISFET QO reduces the substrate effect constant
, configured to increase the output signal level. Ma
In addition, the use of the closed type semiconductor substrate 20 prevents impurities on its surface.
Since the concentration of the n-channel M is low, especially in the manufacturing process,
The feature that makes it easy to set the threshold voltage of ISFETQo low is
Originally, when using the twin well method, the manufacturing process
To suppress the increase in process, n-channel MISFET
A p-type well region 2 is provided in all of the formation regions of Qn and Qo.
2, but the DRAM of this embodiment is for the reason mentioned above.
Based on this, a part of the main surface of the r-type semiconductor substrate 20 is used.
. In this way, (13-8) Memory cell selection of memory cell M
MISFETQs for selection, n-channel forming peripheral circuit
Configuring M I S F E T Q n and output stage circuit
DRAM1 with n-channel MISFETQo
In this case, each channel type is the same n-type and each gate is
The channel length (effective channel length) size was virtually the same.
In this case, the memory cell selection MISFETQs, n-channel
channel MISFETQn, n-channel MISFETQo
The threshold voltages of the respective threshold voltages are successively lowered. With this configuration
, based on the noise generated in the power supply, the memory is in an unselected state.
MISFET Qs for memory cell selection of cell M is erroneously conductive.
information writing operation,
Improve electrical reliability in each information read operation
n-channel MISFET of the output stage circuit
Since the substrate effect constant of Qo can be reduced, the output
Increases the signal level and improves the driving ability of external devices.
and furthermore, the memory cell selection of the memory cell M can be performed.
n-channel MI of the peripheral circuit compared to MISFETQs for
Since the threshold voltage of SFETQn is lowered, the transfer fan
It is possible to improve the ductance and increase the operating speed.
Wear. (15-9) n-channel MIS of the output stage circuit
The FET QO is formed on the main surface of the semiconductor substrate 20 and the above-mentioned
MISFETQs for memory cell selection of memory cell M,
Each of the n-channel MISFETQn of the side circuit is
The main surface of the type semiconductor substrate 20 has an impurity concentration higher than that of the main surface of the type semiconductor substrate 20.
The p-type well region 22 is formed on the main surface thereof. child
The configuration of the n-channel MISFET of the output stage circuit
Since the impurity concentration of the p-type semiconductor substrate 20 is low, Qo is
, the impurity concentration on the main surface of the f-type semiconductor 1 plate 20 or some impurity
The threshold voltage can be easily set low by controlling the purity concentration.
and memory cell selection of the memory cell M.
M I S F E T Q s, peripheral circuit n channel
Each of the channels M I S F E T Q n is p-type.
Impurity concentration between semiconductor substrate 20 and p-type well region 22
It is possible to form a potential barrier region due to the difference in
As a result, alpha-ray soft error resistance can be improved.
Ru. Improvement of α-ray soft error resistance is a memo of DRAM1.
Since the area occupied by Recell M can be reduced, it is possible to
You can improve your degree. The word driver circuit (WL) 15 (WL) of the DRAMI
Figure 13 shows the generator circuit for the input signal (see Figure 3).
In Fig. 13, WC is a word clear circuit diagram.
A signal and WD are food decode signals. XI is word boost potential, XP is self boost node
This is a do precharge signal. XIJL is word boost
This is a potential discharge signal. XIJO, XIJO, XNK, BXIl, BX2 engineering husband
are the decoded signals of the generator circuit. genere
The motor circuit has a high-voltage cut M in the area surrounded by the broken line.
ISFETQcl and Qc2 are arranged respectively. high
Each of MI 5FETQcl and Qc2 for pressure cut is n
Consists of channels. The generator circuit is a self-boost node pre-chip.
Precharged by charge signal XP (=Low)
and node N is at power supply potential Vcc-L/threshold voltage vth
The primary is precharged up to the word boost potential X
When I rises above power supply potential Vcc, n-channel MI
Due to the coupling of the gate capacitance of SFETQd, the above
Node N has a high potential (approximately 10 [V
] or higher). The above-mentioned MIS for high pressure cutting
F E T Q c 1, Qc2 respective drain regions
The area is connected to the node N which has been raised to the high potential. MISFETQ for high voltage cut of the generator circuit
Each of cl and Qc2 is as shown in Fig. 14 (plan view of main part).
It is composed of MISFETQc for high voltage cut
l and Q c 2 are respectively the inter-element isolation insulating film 23 and
Region surrounded by p-type channel stopper region 24A
In the main surface of the p-type well region 22,
There is. In other words, MISFETQcl, Q for high voltage cut
c2 are the me-type well region 22 and the gate insulating film 25, respectively.
, the gate electrode 26, the source region and the drain region.
A pair of n-type semiconductor regions 28 and a pair of d-type semiconductor regions 3
It consists of 7. The gate electrode 26 is connected to the element isolation insulating film 23 and
and within the region surrounded by the p-type channel stopper region 24A.
The planar shape is a ring shape. Gate
The electrode 26 has a T-shaped branch in a part thereof.
The branched portion (26) is on the insulating film 23 for isolation between elements.
It is connected to the signal wiring 50 at. drain area
One of the go-type semiconductor regions 37 used as
within the area defined by the gate electrode 26 in the shape of a
They are set up. the other used as the source area
The Go-type semiconductor region 37 is connected to the element isolation insulating film 23.
and surrounded by a p-type channel stopper region 24A.
In the area, outside the ring-shaped gate electrode 2B
located around the perimeter. In other words, MISF for high pressure cutting
ETQc1. Each of Qc2 is one of the d-type semiconductor regions 3
7 with a channel forming region interposed therebetween to form the other go-shaped half.
A conductor region 37 is provided. said one d type
A high potential is applied to the semiconductor region 37.
However, one d-type semiconductor region 37 is a type p-channel stock.
The layout is such that it does not come into contact with the pad area 24A. The high voltage cut MISFETQc1. Each of Qa2
The signal wiring is connected to the Go-shaped semiconductor region 37 through the connection hole 40A.
A line 50 is connected. One Go-type semiconductor region 37 (
The outer peripheral end of the signal wiring 50 connected to the high voltage side) is a gate.
It is stretched over the electrode 26 (or on the source region side).
Ru. The ring-shaped gate electrode 26 has a stepped shape.
Therefore, in the center part of the ring shape, the signal wiring 50
A recess is formed in the surface of the underlying interlayer insulating film 40. this
The recess is an etching mask (film) for processing the signal wiring 50.
Reflection on the surface of the signal wiring 50 during exposure of the photoresist film)
Due to the diffraction phenomenon based on
Therefore, the signal wiring 50 (
The etching mask used to process it causes the above-mentioned diffraction phenomenon.
I try to process in areas where there is no difference. In this way, (32-17) P-type channel stopper region
MISFETQ for high voltage cut surrounded by 24A
In the DRAMI having c, the high voltage cut M
ISFETQc is a Go-type semiconductor to which high voltage is applied.
A channel forming region (f-type well region) is formed around the body region 37.
22) The other Go-type semiconductor to which a low voltage is applied through the
a gate region 37, and a gate is formed on the channel forming region.
A gate electrode 26 is arranged with a gate insulating film 25 interposed therebetween.
The p-type channel stopper region 24A is
The periphery of the Go-type semiconductor region 37 is surrounded and configured. child
Due to the configuration of the above-mentioned high voltage cut MISFETQC,
One of the Go-type semiconductor regions 37 is a p-type channel stopper region.
24A, one of the go-type semiconductor regions 37
MISFE for high voltage cutting with improved pn junction breakdown voltage
TQc can be made to have a high withstand voltage. In addition, (34-18) the high voltage cut MISFET
The upper layer transistor connected to one of the go-type semiconductor regions 37 of Qc
The outer peripheral end of the signal line 50 is placed on the gate electrode 26.
or the other Go-type semiconductor region 37.
place With this configuration, the one Go-type semiconductor region 3
7 and the upper layer signal wiring 50, an interlayer insulating film 40, etc.
A concave shape is formed on the surface of the gate electrode 26 in the shape of a step,
Due to this concave shape, it is difficult to process the upper layer signal wiring 50.
When the mask is exposed, the surface of the upper wiring formation layer (50) is
Reduce size reduction caused by light reflecting off surfaces.
As a result, the processing accuracy of the upper layer signal wiring 50 can be improved.
can be improved. Previous ii! The external terminal located at the periphery of DRAM1 (
Figure 15 shows the cross-sectional structure of BP (ponding pad).
As shown in FIG. 15, the outer end
The child BP is formed by the second layer wiring 53 in the manufacturing process.
It is. The wiring 53 used inside the DRAMI is
As explained above with respect to the shunt word line 53, the transition
Metal film 53A, aluminum film 53B, transition metal film 53
It has a three-layer structure in which C is laminated. to this
On the other hand, the external terminal BP excludes the upper layer transition metal film 53C.
I left. Lower layer transition metal film 53A, middle layer aluminum
It is composed of a two-layer structure in which the films 53B are laminated in sequence.
Ru. The bonding device connects the surface of the external terminal BP, the
Due to the difference in the reflectance of each surface of the film 54, the above-mentioned
Bond the bonding wire 4 to the surface of the terminal BP.
Positioning is performed when searching. Upper layer history of wiring 53
The transfer metal film 53C has a low reflectance, and the passivation film 5
Since the difference in reflectance between 4 and 4 is small, the external terminal BP
The surface has a higher reflectance than the upper transition metal film 53G.
The aluminum film 53B is exposed. Exposing the surface of the aluminum film 53B of the external terminal BP
The step of removing silicon oxide from the upper passivation film 54
Bonding formed on the film 54A and the silicon nitride film 54B
This is done in the same process as the process of forming the plug opening 55 (same mask).
), on the passivation film 54
The resin film 54C of the layer has a layer on the bonding opening 55.
The bonding opening 56 has a larger size than that of the bonding opening 56.
is provided. In this way, (7-4) is formed on the padge page 1 film 54.
through the bonding openings 55 (and 56)
Same as internal wiring 1iA53 to which wiring wire 4 is connected.
DRAM1 having an external terminal BP formed of one conductive layer
In this case, the internal wiring 53 is covered with an aluminum film (or
alloy film) 53B and transition metal 1t@53C, respectively.
It is composed of a laminated composite film, and the external terminal BP is connected to the transition terminal.
It is composed of an aluminum film 53B with the metal film 53C removed.
Ru. With this configuration, external
Improves the reflectance of the surface of the terminal BP, making it easier to connect the external terminal BP and pad.
external terminal BP due to the difference in reflectance with the scivation film 54.
Since the bonding position can be reliably recognized,
, reducing bonding defects and improving DRAM assembly process.
Yield can be improved. Also, bonding
When the ear 4 is formed of aluminum wire, the external
The surface of the terminal BP exposes the aluminum film 53.B.
Therefore, the bond between external terminal BP and bonding wire 4 is
improve bondability and reduce bonding defects.
I can do that. As a result, the yield of DRAM1 assembly process is
can be further improved. (8-5) Aluminum film 5 of the external terminal BP
The transition metal film 53C on 3B is the passivation layer 11.
defined by a bonding opening 55 formed in 154
Remove within the area. With this configuration, the outer end
Etching to remove transition metal film 53C on the surface of child BP
A mask opens bonding to the passivation film 54.
It can also be used as an etching mask to form the mouth S5.
4 minutes, which corresponds to the process of forming a mask, DRA
The number of MI manufacturing steps can be reduced. Next, regarding the specific manufacturing method of the above-mentioned DRAMI,
Figures 16 to 33 (cutaways of main parts shown for each predetermined manufacturing process)
This will be briefly explained using a side view). I-well formation process] First, a p-type semiconductor substrate 20 made of single crystal silicon is prepared.
do. Next, a silicon oxide film 6 is formed on the main surface of the final type semiconductor substrate 20.
0 and silicon nitride films 61 are sequentially stacked. silicon oxide film
60 is a high temperature bath of about 900 to 1000 ['C]
Formed by team oxidation method, for example, 30 to 50 [nml]
Form the film with a thickness of approximately This silicon oxide film 60 is a buffer
used as a layer. The silicon nitride film 61 is doped with impurities.
Used for masks and oxidation-resistant masks. Silicon nitride film 6
1 is deposited by 9, for example, the CVD method, and has a thickness of 30 to 60 [nm].
Form the film with a thickness of approximately Next, silicon nitride @6 in the π-type well region (21) formation region
1 is removed to form a mask. The formation of this mask is
Photolithography technology (photoresist mask formation technology)
This is done using etching techniques. Next, as shown in FIG. 16, the mask (61) is used.
The main surface of the r-type semiconductor substrate 20 is exposed through the silicon oxide film 60.
An n-type impurity 21n is introduced into the portion. The n-type impurity 21n is
, for example, about 10"[atoms/cs"]
Using P with a pure concentration, a voltage of about 120 to 150 [KeV]
Introduced using energy ion implantation method. Next, using the mask (61), as shown in FIG.
Next, grow the silicon oxide film 60 exposed through the mask, and
A silicon oxide film 60A that is thicker than that is formed. silicon oxide
The film 60A is formed only in the type 1 well region (21) formation region.
a mask and an impurity to remove said mask (61).
Used as a substance introduction mask. The silicon oxide film 60A has a high temperature of about 900 to 1000 [''C].
Formed by a steam oxidation method at a temperature of, for example, 1
It is formed to have a film thickness of about 10 to 150 [nm].
Ru. The heat treatment process for forming this silicon oxide film 60A
Then, the introduced n-type impurity 21n is slightly diffused,
2-type semiconductor region (ultimately becomes 2-type well region 21)
) 21A is formed. Next, the mask (61) is selectively removed. mask
(61) is removed, for example, with hot phosphoric acid. After this. Although not shown, n-channel M of the DRAMI output stage circuit
In the formation region of ISFETQo (see FIG. 12),
Forming an impurity introduction mask (e.g. photoresist film)
Ru. Next, as shown in FIG. 18, the silicon oxide film 60A,
Using each of the impurity introduction masks (not shown),
P is applied to the main surface of the r-type semiconductor substrate 20 through the silicon oxide film 60.
A type impurity 22p is introduced. The p-type impurity 22p is, for example,
Impurities of about 1013 to 10"[atomg/m"]
Using BF (or B) at a concentration of 50 to 70 [KeV]
It is introduced by ion implantation method with a certain amount of energy. This p-type non-
The pure substance 22p is formed by making the silicon oxide film 60A thicker.
Therefore, it is not introduced into the well region (21) forming region.
Not possible. Next, each of the n-type impurity 21n and the P-type impurity 22p
As shown in Figure 19, the
A well region 21 and a p-type well region 22 are formed. child
"The type well region 21 and the f-type well region 22 are 110
Heat treatment in a high temperature atmosphere of about 0 to 1300[''C]
Formed by applying. As a result, p-type well
The region 22 is formed in self-alignment with the π-type well region 21.
be done. After this, a defect is formed in the area of the output stage circuit.
Remove the pure substance introduction mask.

[Separation region formation process]

Next, a silicon nitride film 62 is formed over the entire surface of the substrate including the silicon oxide films 60 and 60A. This silicon nitride film 6
2 is used as an impurity introduction mask and an oxidation-resistant mask. The silicon nitride film 62 is deposited by, for example, a CVD method.
It is formed with a film thickness of about 00 to 150 [nm1]. Next, the silicon nitride film 62 is removed between the MISFET formation regions (insulating film formation region for element isolation), and a mask is formed using the remaining silicon nitride film 62. This mask (62) is formed using photolithography technology and etching technology.
62), a p-type impurity 24p is introduced into the main surface of the me-type well region 22 through the silicon oxide film 60, as shown in FIG. The p-type impurity 24p is formed on the main surface of the type 1 well region 21 because the silicon oxide film 60A is thicker than the silicon oxide film 60 formed on the main surface of the type 1 well region 22. The p-type impurity 24p is not introduced, that is, the p-type impurity 24p is selectively introduced into the main surface portion of the p-type well region 22. The p-type impurity 24p is, for example, 10"ra
Using BF with an impurity concentration of approximately 50 to 70 [KaV], the p-type impurity 24p is introduced by ion implantation with an energy of approximately 50 to 70 [KaV]. When introducing the p-type impurity 24p, the mask (62) is processed. An etching mask (photoresist film) may be used in combination.Next, using the mask (62), each of the exposed silicon oxide films 60 and 60A is grown to form an insulating film for element isolation (field insulating film). The inter-element isolation insulating film 23 is formed in a nitrogen gas atmosphere at a high temperature of, for example, 1000 ['C].
It can be formed by performing heat treatment for 0 [minutes] and then oxidizing for about 140 to 170 [minutes] using a steam oxidation method. Alternatively, the inter-element isolation insulating film 23 may be formed only in a steam oxidation atmosphere, and the inter-element isolation insulating film 123 is formed to have a thickness of, for example, about 600 to 800 nm. The p-type impurity 24p introduced into the main surface of the me-type well region 22 is stretched and diffused by substantially the same manufacturing process as the process of forming the inter-element isolation insulating film 23.
A P-type channel stopper region 24A is formed. This p
When forming the type channel stopper region 24A, a relatively long heat treatment is performed as described above, so that the p-type impurity 24p has a large amount of diffusion in the lateral direction. A p-type impurity 24p is diffused over substantially the entire region, forming a p-type semiconductor region 24B. On the other hand, in the formation regions of the n-channel MI 5FETs Qn and Qo that constitute the CMO 9 of the peripheral circuit, the gate width and other dimensions are larger than that of the memory cell M, so the amount of lateral diffusion of the p-type impurity 24p is The p-type impurity 24p is relatively small and is diffused only in the vicinity of the element isolation insulating film 23, that is, n
P-type semiconductor region 24B is not substantially formed in the formation regions of channel MISFETs Qn and Qo. Therefore, this p-type semiconductor region 24B is not formed in the formation region of each of the n-channel MISFETs Qn and Qo of the peripheral circuit, but is selectively formed in the formation region of the memory cell array IIB. Moreover. The p-type semiconductor region 24B is the P-type channel stopper region 24
It can be formed in the same manufacturing process as A. After the heat treatment, each of the p-type channel stopper region 24A and the p-type semiconductor region 24B has a temperature of l O'' to I Q'' [at. After that, as shown in FIG. 21, the mask (62) is removed. Next, the silicon oxide on the main surface of the me-type well region 22 is membrane 6
Silicon oxide film 60 on the main surfaces of 0 and n-type well regions 21
A is removed and the me-shaped well region 22. n-type well region 2
1. Expose each main surface of 1.

[Gate insulating film formation process]

Next, a silicon oxide film 63 is formed on each of the exposed main surfaces of the me-type well region 22 and the 1-type well region 21. The silicon oxide film 63 is mainly made of a so-called white ribbon of silicon nitride, which is formed at the end of the insulating film 23 for element isolation using a silicon nitride film (mask) 62 when forming the insulating film 23 for element isolation. It is done to oxidize. The silicon oxide film 63 is formed, for example, by a steam oxidation method at a high temperature of about 900 to 1000 ["C] in diameter, and
It is formed with a film thickness of about nml. Next, in the element formation region defined by the element isolation insulating film 23, the main surface portion of the p-type well region 22 (memory cell array (p-type semiconductor region 24B in IB)), the main surface portion of the di-type well region 21, , a p-type impurity 64p for adjusting the threshold voltage is introduced into the main surface of the p-type semiconductor substrate 20, that is, the entire surface of the substrate. Using B with an impurity concentration of about 2
It is introduced by ion implantation with an energy of about 0 to 40 [K e V]. This p-type impurity 64p is introduced mainly to adjust the threshold voltages of each of the n-channel MISFETs Qs, Qn, and Qo. Next, in the element formation region defined by the element isolation insulating film 23, a p-type impurity 65p for adjusting the threshold voltage is introduced into the main surface of the n-type well region 21. This p
The type impurity asp is, for example, 10"l"atoms/
cm”] using B with an impurity concentration of 20 to 4
It is introduced by ion implantation with an energy of about 0 [KeV]. The p-type impurity 65p is mainly used in the p-channel MISFETQp.
has been introduced to adjust the threshold voltage. Next, as shown in FIG. 22, an insulating film 23 for isolation between elements
In the formation region of memory cell array IIB defined by , a p-type impurity 66P for adjusting the threshold voltage is introduced into the main surface of the p-type well region 22. The P-type impurity 66p is, for example, 1011 [atoms/
Using B with an impurity concentration of about 20 to 40 [K
It is introduced by an ion implantation method with an energy of about [eV]. P-type impurity 66p is mainly used for memory cell selection of memory cell M.
It is introduced to adjust the threshold voltage of ISFETQs. Note that the introduction of the p-type impurity 66p can be done by changing the impurity concentration of the p-type semiconductor region 24B described above or by changing the impurity concentration of the p-type semiconductor region 24B described above.
It can be omitted if the amount to be introduced is close to that of the type impurity 65p. In addition, the p-type impurities 64p, 65p, 66p
The order of introducing each of the p-type impurities 64p, 65p, and sep may be changed, and the p-type impurities 64p, 65p, and sep are introduced into the p-type semiconductor substrate 20, the p-type well region 22, and the n-type well region 21. Either one can be omitted depending on how the respective impurity concentrations are set. Next, the silicon oxide film 63 is selectively removed, and the p-type well region 22 and the p-type well region 21 (not shown) are removed.
(including the type semiconductor substrate 20) are exposed. Next, a gate insulating film 25 is formed on each main surface of the exposed p" type well region 22 and n- type well region 21. The gate insulating film 25 has a high It is formed by a steam oxidation method at a temperature of 15 to 25 nm.
It is formed with a film thickness of approximately .

[Gate wiring formation process 1] Next, on the gate insulating film 25 and the inter-element isolation insulating film 23
A polycrystalline silicon film is formed over the entire surface of the substrate including the top. The polycrystalline silicon film is deposited by CVD method and has a thickness of 150 to 300
[Form with a film thickness of about nm1.] An n-type impurity such as P, which reduces the resistance value, is introduced into the polycrystalline silicon film by thermal diffusion. Next, an interlayer insulating film 27 is formed over the entire surface of the polycrystalline silicon film. The interlayer insulating film 27 is composed of a silicon oxide film 27A formed on the surface of the polycrystalline silicon film and a silicon oxide film 27B laminated on top of the silicon oxide film 27A. The lower silicon oxide film 27A is formed with a thickness of about 20 to 50 nm in an oxygen gas atmosphere of about 800 to 1000 [C]. The upper silicon oxide film 27B is formed using inorganic silane gas (SiH, or SiH). , CQ□) and nitrogen oxide gas (N, O) as source gases.The silicon oxide film 27B, which is the upper layer of the interlayer insulating film 27, is formed to have a thickness of, for example, about 250 to 400 [nm]. Next, as shown in FIG. 23, using an etching mask (not shown), the interlayer insulating film 27 and polycrystalline silicon film are sequentially etched to form the gate electrode 26 and the word line (W).
L) 26 is formed. Further, an interlayer insulating film 27 is left above each of the gate electrode 26 and the word line 26. The etching is performed by anisotropic etching, and by using the chopping etching method described below, the anisotropy of the etching can be increased and the amount of overetching can be reduced. (Low concentration semiconductor region formation process) Next, in order to reduce contamination caused by impurity introduction, a silicon oxide film (not numbered) is formed on the entire surface of the substrate.This silicon oxide film is not exposed by the etching. The silicon oxide film is formed on each main surface of the p-type well region 22 and n-type well region 21 and on the sidewalls of each of the gate electrode 26 and word line 26. The silicon oxide film has a temperature of about 850 to 950['C], for example. It is formed in an oxygen gas atmosphere at a high temperature of 10 to 80[
It is formed with a film thickness of about nml. Next, using the element isolation insulating film 23 and the interlayer insulating film 27 (and gate electrode 26) as an impurity introduction mask, the memory cell array IIB, the n-channel MISFETQn,
In each formation region of Qo, p-type well region 22
．． An n-type impurity is introduced into each main surface portion of the p-type semiconductor substrate 20 . By introducing the n-type impurity, it is possible to form a low impurity concentration n-type semiconductor region 28 that is self-aligned with the gate electrode 26 or the word line 26. The n-type impurity is, for example, 10"[atoms/3"
Using P (or As) with an impurity concentration of about 80 to 1
It is introduced by ion implantation with an energy of about 20 [KeV]. As described above, the n-type semiconductor region 28 of the memory cell selection MISFET Qs of the memory cell M at least on the side connected to the information storage capacitive element C of the stacked structure has a low impurity concentration of less than 10 ``[atoms/Ql''1]. It is formed using the ion implantation method. n-type semiconductor region 28
are formed with a low impurity concentration, so the memory cell selection MISFETQs, n-channel MISFETQn,
When forming the n-type semiconductor region 28, each of which can have an LDD structure, a p-channel MISFE is used.
The TQp formation region is covered with an impurity introduction mask (photoresist film). By this step of forming the n-type semiconductor region 28, the memory cell selection MISFET QS of the memory cell M is almost completed. Next, using the interelement isolation insulating film 23 and the interlayer insulating film 27 (and gate electrode 26) as an impurity introduction mask, p
In the formation region of the channel MISFETQp, n-type impurities are introduced into the main surface of the type 1 well region 21. This P
By introducing type impurities, it is possible to form a low impurity concentration P type semiconductor region 30 that is self-aligned with the gate electrode 26, as shown in FIG. The n-type impurity is, for example, lO""[atoms/tx"
Using BF (or B) with an impurity concentration of about 60~
It is introduced by an ion implantation method with an energy of about 100 [KaV]. When introducing n-type impurities, memory cell array 1
The formation regions of 1B, n-channel MISFETQn, and Qo are each covered with an impurity introduction mask (photoresist film). Next, although not shown, in the formation region of the electrostatic breakdown prevention circuit added to the input stage circuit (or output stage circuit) of the DRAM1, the n-type Introducing impurities at high impurity concentrations. By introducing an additional n-type impurity into this n-channel MISFETQn, it is possible to easily drain an excessive voltage that is input to the drain region and causes electrostatic breakdown to the r-type well region 22 side. In other words, this n-channel MISFETQn can increase the electrostatic breakdown voltage. [Spacer formation process and connection hole formation process 1] Next, the second
As shown in FIG. 5, sidewall spacers 29 are formed on the respective sidewalls of the gate electrode 26, the word line 26, and the interlayer insulating film 27 above them. The sidewall spacer 29 is formed by depositing a silicon oxide film,
It can be formed by performing anisotropic etching such as RIE to a thickness corresponding to the thickness of the deposited silicon oxide film. The silicon oxide film of the sidewall spacer 29 has the same film quality as the silicon oxide film 27B of the upper layer of the interlayer insulating film 27. It is formed by a CVD method using inorganic silane gas and nitrogen oxide gas as source gases. This silicon oxide film is, for example, 2
It is formed with a film thickness of about 00 to 400 [nml]. Gate length direction of sidewall spacer 29 (channel length direction)
The length is about 200 to 400 [nml]. Note that the sidewall spacer 29 may be formed in a limited area as necessary. Next, an interlayer insulating film 31 is formed over the entire surface of the substrate including the interlayer insulating film 27, the sidewall spacer 29, and the like. This interlayer insulating film 31 is used as an etching stopper layer when processing each electrode layer of the information storage capacitive element C having a stacked structure. Further, the interlayer insulating film 31 is connected to the lower electrode layer (33) of the information storage capacitor C of the stacked structure and the memory cell selection MI.
SFETQ! It is formed to electrically isolate the gate electrode 26 and the word line 26 of I. The interlayer insulating film 31 is formed with a thickness that takes into account the amount of abrasion due to overetching during processing of the upper conductive layer, the amount of abrasion during the cleaning process, etc. The interlayer insulating film 31 uses inorganic silane gas and nitrogen oxide gas as a source gas. It is formed of a silicon oxide film deposited by a CVD method. In other words, this interlayer insulation 11i13
1 can reduce the stress generated due to the difference in linear expansion coefficient between the dielectric film (34) of the information storage capacitive element C of the stacked structure and the underlying interlayer insulating film 27. The interlayer insulating film 31 is formed to have a thickness of, for example, about 100 to 200 [nml]. Next, as shown in FIG. 26, on the other n-type semiconductor region (the side to which the lower electrode layer 33 of the information storage capacitive element C is connected) 28 of the memory cell selection MISFET Qs in the memory cell M formation region. The interlayer insulating film 31 is removed, and connection holes 31A and 32 are formed, respectively.

[Gate Wiring Formation Step 2] Next, as shown in FIG. 27, the lower electrode layer 33 of the information storage capacitive element C of the stacked structure of the memory cell M is formed. A portion of the lower electrode layer 33 is connected to the n-type semiconductor region 28 through each of the connection holes 31A and 32, and the other portion extends over the interlayer insulating film 27 and 31. The lower electrode layer 33 has connection holes 31 formed in the interlayer insulating film 31.
Compared to the opening size of A, it is formed larger by at least an amount corresponding to the mask alignment margin size in the manufacturing process. The lower electrode layer 33 is formed of a polycrystalline silicon film deposited by the CVD method, and is formed to have a thick film thickness of about 200 to 400 [nm]. This polycrystalline silicon film is formed in the second layer gate wiring formation step in the manufacturing process. After depositing the polycrystalline silicon film, the lower electrode layer 33 is made of n
It is formed by introducing a type impurity, such as P, into the polycrystalline silicon film by thermal diffusion, and then processing the polycrystalline silicon film using photolithography and etching techniques. The photolithography technique includes a process of forming an etching mask (photoresist film) and a process of removing the etching mask. The etching mask removal process uses Freon gas (CHF) and oxygen gas (0□).
This is done by downstream plasma processing using a mixed gas with This process has the effect of reducing damage to each element of the DRAMI. However, the present inventor has confirmed that the removal of the etching mask by this plasma treatment causes a phenomenon in which P (n-type impurity) deposited on the surface of the polycrystalline silicon film is selectively etched by the Freon gas. Selective etching of the deposited P is undesirable because it forms minute holes on the surface of the lower electrode layer 33 and deteriorates the dielectric strength voltage of the dielectric film (34). Therefore, the DRAM1 of this embodiment is After depositing a polycrystalline silicon film and introducing n-type impurities, the surface of the polycrystalline silicon film is oxidized before removing the etching mask, and the P precipitated layer is removed by removing the silicon oxide film. are doing. Oxidation on the surface of the polycrystalline silicon film causes several [
The addition of this oxidation step, which only requires oxidation to form a silicon oxide film with a thickness of about nm1, is not limited to the second layer gate wiring formation step (33), but also the first layer gate wiring formation step (33). 26) and the third layer gate wiring forming step (35). Further, the etching process of the polycrystalline silicon film uses anisotropic etching. In addition, the etching process can be performed by using the chopping etching method described below.
Etching residue can be reliably removed by increasing etching anisotropy and reducing the amount of overetching. In this way, a DRAMI manufacturing method includes depositing a polycrystalline silicon film, introducing an n-type impurity into the polycrystalline silicon film by thermal diffusion, and then processing the polycrystalline silicon film using photolithography technology and etching technology. After the n-type impurity is introduced into the polycrystalline silicon film and before the etching mask removal process of the photolithography technique, a step of removing the n-type impurity precipitated on the surface of the polycrystalline silicon film is provided. This configuration prevents the formation of minute holes on the surface of the polycrystalline silicon film when the etching mask is removed. It is possible to improve pressure resistance. Within the region defined by the connection hole 32, the other n-type semiconductor region 28 of the memory cell selection MISFETQs
The n-type impurity introduced into the lower electrode layer 33 is diffused into the main surface of the semiconductor layer 33 to form an n°-type semiconductor region 33A. Each of the n° type semiconductor region 33A and the n type semiconductor region 28 is formed integrally. The go-type semiconductor region 33A is designed to improve the ohmic characteristics between the other n-type semiconductor region 28 of the memory cell selection MISFET Qs and the lower electrode layer 33 (reduction in contact resistance value). (Dielectric film forming step) Next, as shown in FIG. 28, a dielectric film 34 is formed on the entire surface of the substrate including on the lower electrode layer 33 of the stacked information storage capacitor C of the memory cell M. .Dielectric material [3
4 is basically formed of a two-layer structure in which the silicon nitride film 34A and the silicon oxide film 34B are sequentially laminated, as described above. The lower silicon nitride film 34A is deposited by, for example, a CVD method to have a thickness of about 5 to 10 nm. When forming this silicon nitride film 34A, inclusion of oxygen is suppressed as much as possible. Lower electrode layer 3 at normal production level
If the silicon nitride film 84A is formed on the polycrystalline silicon film 33 (polycrystalline silicon film), a very small amount of oxygen will be involved, so a natural silicon oxide film (
) is formed. The silicon oxide film 34B, which is the upper layer of the dielectric film 34, is formed by applying a high-pressure oxidation method to the lower silicon nitride film 34A. It is formed with a film thickness of about 1 to 6 [nm]. Silicon oxide film 34
When B is formed, the thickness of the lower silicon nitride film 34A is slightly reduced, so that the silicon nitride film 84A ultimately has a thickness of 4 to 8 [nm].
] is formed with a film thickness of approximately . The silicon oxide film 34B is basically formed under a high pressure of 1.5 to 10 [atmospheres] and 800 to 100 [atmospheres].
In this embodiment, the film is formed in an oxygen gas atmosphere at a high temperature of about 0['C]. The silicon oxide film 34B has a high pressure of 3 to 4 [atmospheres] and an oxygen flow rate (source gas) during oxidation of 4 to 6 [41/win].
], hydrogen flow rate (source gas) from 3 to 10 [Q/1r
It is formed as an inl. The silicon oxide film 34B formed by high-pressure oxidation can be formed to a desired thickness in a shorter time than a silicon oxide film formed at normal pressure (1 atmosphere). In other words, the high-pressure oxidation method can shorten the high-temperature heat treatment time, so the MISFE for memory cell selection
The pn junction depth of the source region and drain region of TQ8 etc. can be made shallow. Therefore, the dielectric film 34 has a three-layer structure in which a natural silicon oxide film, a silicon nitride film 34A, and a silicon oxide film 34B are sequentially laminated. A native silicon oxide film can be made thinner by reducing oxygen inclusion. Furthermore, although the number of manufacturing steps increases, the natural silicon oxide film may be nitrided and the dielectric film 34 may have a two-layer structure.

[Gate Wiring Formation Step 3] Next, a polycrystalline silicon film is deposited over the entire surface of the substrate including the top of the dielectric film 34. The polycrystalline silicon film is deposited by CVD method,
It is formed with a film thickness of about 150 to 250 [nm1]. This polycrystalline silicon film is formed in the third layer gate wiring formation step in the manufacturing process. Thereafter, an n-type impurity such as P, which reduces the resistance value, is introduced into the polycrystalline silicon film by thermal diffusion. Next, an etching mask 67 is formed on the polycrystalline silicon film over the entire surface of the memory cell array IIB except for the connection area between one n-type semiconductor region 28 of the memory cell selection MISFET Qs and the complementary data line (50). . The etching mask 67 is formed of, for example, a photoresist film using photolithography technology. Thereafter, by sequentially etching each of the polycrystalline silicon film and dielectric film 34 using the etching mask 67, the polycrystalline silicon film forms the upper electrode layer 3, as shown in FIG.
5 can be formed. The polycrystalline silicon film is etched, for example, by a plasma step etching method. By forming this upper electrode layer 35, the stacked structure information storage capacitive element C is almost completed. As a result, the DRAMI memory cell M is completed. After completing this memory cell M, the etching mask 67 is
is removed.

[High concentration semiconductor region forming step 1 Next, an insulating film 3B is formed on the entire surface of the substrate including on the upper electrode layer 35 of the information storage capacitor C of the stacked structure, on the n-channel MISFETQn, and on the p-channel MISFETQP. do. The insulating film 36 is mainly used as a contamination prevention film when introducing impurities. The insulating film 36 is formed of a silicon oxide film deposited by, for example, a CVD method using organic silane gas (Si (ocaHi), ) as a source gas, or a CVD method using an inorganic silane gas and nitrogen oxide gas as a source gas. The film thickness is approximately 100 nm. Next, n-type impurities are introduced into the main surface of the p-type well region 22 in the formation region of the n-channel MISFETQn (including Qo) constituting 0MO8 of the peripheral circuit of the DRAM1. The n-type impurity is mainly introduced into the gate electrode 26 and the interlayer insulating film 27 above it. Side wall spacer 2
9 is used as an impurity introduction mask. When introducing n-type impurities, the formation region of the memory cell M and the formation region of the p-channel MISFET Qp are covered with an impurity introduction mask (
covered with a photoresist film). The n-type impurity is introduced using As having an impurity concentration of about 10" to 101"[atoms/cse"], for example, by an ion implantation method with an energy of about 70 to 90 [K e Vl. Next, the CMO8 is p-channel MISFET that constitutes
In the Qp formation region, a p-type impurity is introduced into the main surface of the type 1 well region 21. The p-type impurity is mainly introduced into the gate electrode 26 and the upper layer of the open fiber film 27. Each sidewall spacer 29 is used as an impurity introduction mask. When introducing the P-type impurity, the formation region of the memory cell M and the formation region of the n-channel MISFETQn are covered with an impurity introduction mask. The n-type impurity is introduced by ion implantation using, for example, BF with an impurity concentration of about 10''[atoms/am''] and an energy of about 60 to 90 [KeV]. Thereafter, the n-type impurity and the n-type impurity are stretched and diffused, and as shown in FIG. P° type semiconductor regions 38 are formed respectively. The stretching diffusion is performed by heat treatment at a high temperature of about 900 to 1000[° C.] for about 10 cm. This step of forming the go-type semiconductor region 37 produces an n-channel MISFET.
Qn is almost completed. Through the step of forming the p° type semiconductor region 38, the p channel MI 5FETQP is almost completed. [Interlayer Insulating Film Forming Step 1] Next, interlayer insulating films 39 and 40 are sequentially laminated over the entire surface of the substrate including on each of the DRAMI elements. The lower interlayer insulating film 39 is made of C, for example, using organic silane gas as a source gas.
It is formed from a silicon oxide film deposited and stacked by the VD method. The living room insulating film 39 is formed to have a thickness of, for example, about 150 to 250 [nm1] in order to prevent leakage of impurities (P and B, respectively) from the upper interlayer insulating film 40 (BPSG). The upper interlayer insulating film 40 is formed of, for example, a silicon oxide film (BPSG film) deposited by a CVD method. This interlayer insulating film 40 is formed to have a thickness of, for example, about 400 to 700 [nm]. The interlayer insulation 11140 is subjected to blowing at a temperature of about 900 to 1000 ['C] in a nitrogen gas atmosphere. Its surface is flattened.

[Connection hole forming step 2] Next, the connection holes 40A are formed in each of the interlayer insulating films 40 and 39.
form. The connection hole 40A is connected to the n-type semiconductor region 28. of each element of the DRAMI. They are formed above each of the green semiconductor region 37 and the final semiconductor region 38, and above the word line 26 (not shown). The connection hole 40A is formed by, for example, isotropic etching the upper interlayer insulating film 40 side and anisotropic etching the lower interlayer insulating film 36 side. In other words, the connection hole 40A is configured to increase the step coverage of the upper layer wiring (for example, the complementary data line 50, etc.) and prevent disconnection defects. Further, the connection hole 40A may be formed only by anisotropic etching. Next, the n-type semiconductor region 2 exposed from the connection hole 40A
8. A silicon oxide film (
form (unsigned). In the silicon oxide film, B or P added to the interlayer insulating film 40 is added to the interlayer insulating film 40 in the subsequent heat treatment (stretching diffusion of impurities forming the Cr1'' type semiconductor region 41) through the connection hole 40A to the n-type semiconductor region 28, It is possible to prevent B from being introduced into the main surfaces of the Go-type semiconductor region 37 and the p'-type semiconductor region 38. B can be prevented from being introduced into the main surfaces of the N-type semiconductor region 28 and the Go-type semiconductor region 37, When P is introduced into the main surface of the closed-type semiconductor region 38, the effective impurity concentration decreases, and the contact resistance value between each semiconductor region and the wiring (50) connected thereto increases. The film 30 is formed of a thin film of about 12 to 50 [nm].Next, in the formation regions of the memory cell selection MISFETQs, n-channel MISFETQn, and Qo, the n-type semiconductor region 28. An n-type impurity is introduced into each main surface portion of the n-type semiconductor region 37.
The type impurity is introduced into each main surface portion through the thin silicon oxide film. Then, by stretching and diffusing this n-type impurity, a Go-type semiconductor region 41 with a high impurity concentration is formed as shown in FIG. Go-type semiconductor region 4
1, when the connection hole 40A is misaligned with each of the n-type semiconductor region 28 and the go-type semiconductor region 37 due to mask misalignment in the manufacturing process, the wiring (50) passing through the connection hole 40A and the p
- type well region 22 is formed to prevent short circuit. n forming this Go-type semiconductor region 41
The type impurity is, for example, 10'' [atoms/CIl
”] using As with a high impurity concentration of 110 to 130
It is introduced by an ion implantation method with an energy of about [K e V]. The Go-type semiconductor region 41 is in the memory cell M. It is formed integrally with one n-type semiconductor region 28 of the memory cell selection MISFETQs, and forms a part of the source region or the drain region. Since the n'' type semiconductor region 41 is formed with a high impurity concentration, it is possible to reduce the contact resistance value with the upper wiring, for example, the complementary data line (50).

[Wiring Formation Step 1] Next, as shown in FIG. 32, a wiring 50 is connected to the Go-type semiconductor region 41, the p°-type semiconductor region 38, etc. through the connection hole 40A, and extends on the interlayer insulating film 40. form. The wiring 50 is formed in the first layer wiring formation step in the manufacturing process. The wiring 50 is used as a complementary data line (DL) 60 between the memory cell array IIB and the column address decoder circuit 12. Wiring 50
is a layer 3 in which a transition metal film 50A, an aluminum film (or its alloy film) 50B, and a transition metal film 50C are sequentially laminated.
It is composed of a layered structure. The transition metal film 50A under the wiring 50 is formed of, for example, a WSi film deposited by CVD, and has a thickness of 50 to 200[n].
The thickness of the film is approximately 100 m. The reaction formation formula for WSi and film is as follows. The middle layer aluminum film 50B is deposited, for example, by a sputtering method, and has a thickness of about 300 to 600 [nm]. The upper transition metal film 50C is formed of, for example, a Mo5iz film deposited by sputtering, and has a thickness of about 10 to 40 [nm]. This wiring 50 includes a transition metal film 50A, an aluminum film 50A, and an aluminum film 50A.
After the 0B and transition metal films 50C are sequentially laminated, they are processed using photolithography and etching techniques. The processing technology for this wiring 50 and the wiring 53 above it will be described in detail later.

[Interlayer insulating film forming step 2] Next, an interlayer insulating film 51 is formed on the entire surface of the substrate including on the wiring 50.
form. The interlayer insulating film 51 is a silicon oxide film (deposited type insulating film) 51A, a silicon oxide film (coated type insulating film) 51B, and a silicon oxide film (deposited type insulating film) 51C, which are laminated in sequence.
It is composed of a layered structure. The lower silicon oxide film 51A is deposited by plasma CVD to have a thickness of about 400 to 700 [nm1]. The middle layer silicon oxide film 51B is formed to flatten the surface of the interlayer insulating film 51. The silicon oxide film 51B is made of S
100 to 150 [nm] on a wide flat pattern using the OG method.
] and then baked to a thickness of about 450 [
"C]), and the surface of the silicon oxide film 51B is formed by recessing the surface by etching. Due to the recessing by etching, the silicon oxide film 51B is formed only in the recessed portions of the step shape on the surface of the lower silicon oxide film 51A. Furthermore, due to the etching caused by the etching, the lower silicon oxide film is also etched and retreated in the step-shaped convex portion of the lower layer, and the silicon oxide film 5
The flatness after coating 1B is maintained. Also, one interlayer insulating film 5
The middle layer 1 may be formed of an organic film such as a polyimide resin film instead of the silicon oxide film SIB. The upper silicon oxide film 51C is deposited by, for example, a plasma CVD method to increase the strength of the interlayer insulating film 51 as a whole, and is formed to have a thickness of about 500 to 700 [nm].

[Connection Hole Formation Step 3] Next, as shown in FIG. 33, a connection hole 52 is formed in the interlayer insulating film 51. The connection hole 52 includes an upper connection hole 52B formed by isotropic etching on the upper silicon oxide film 51C side of the interlayer insulating film 51, and a lower connection hole 52B formed by anisotropic etching on the lower silicon oxide film 51A side. Side connection hole 52A
It is formed by each of the. After forming this connection hole 52, approximately 400 mL of etching was performed to recover from the damage caused by etching.
Heat treatment to a degree of ['C] is performed.

[Wiring Formation Step 2] Next, as shown in FIG. 1, a wiring 53 is formed extending over the interlayer insulating film 51 so as to be connected to the wiring 50 through the connection hole 52. This wiring 53 is formed by a second layer wiring formation process. The wiring 53. As described above, it has a three-layer structure in which the transition metal film 53A, the aluminum film (or its alloy film) 53B, and the transition metal 153G are sequentially laminated. The lower transition metal film 53A is formed of, for example, a MoSi film deposited by sputtering, and has a thickness of 50 to 100 [nm1].
Form the film with a thickness of approximately The middle layer aluminum film 53B is deposited by sputtering and is thicker than the aluminum film 50B of the wiring 50.
It is formed with a film thickness of about 00 to 10100 OCn. The upper transition metal film 53C is formed of, for example, a MoSi film deposited by sputtering and has a thickness of about 10 to 40 nm. This wiring 53 includes a transition metal film 53A, an aluminum film 5
After sequentially stacking the transition metal film 3B and the transition metal film 53G, they are processed using photolithography and etching. The processing technology for this wiring 53 will be explained in detail later. After the step of forming the wiring 53, heat treatment is performed to recover damage caused by etching the wiring 53.

[Passivation Film Formation Step] Next, as shown in FIGS. 1 and 15, a badge-container film 54 is formed on the entire surface of the substrate including on the wiring 53. As described above, the badge-container film 54 is formed of a composite film in which the silicon oxide film 54A, the silicon nitride film 54B, and the resin film 54C are sequentially laminated. The silicon oxide film 54A under the passivation film 54 has a thickness of 150~
It is formed with a film thickness of about 600 [nm]. The middle layer silicon nitride film 54B is deposited by, for example, a plasma CVD method, and
．． It is formed with a film thickness of about 0 to 1.2 [μm]. The upper resin film 54C is formed of a polyimide resin film applied by a coating method, for example, and has a thickness of about 3 to 12 [μm]. Next, in the formation region of the external terminal BP of the DRAMI, the upper resin film 54G of the passivation film 54 is
A bonding opening 56 is formed in. This bonding opening 56 is formed using photolithography and etching techniques. Then, after this, the external terminal BP
In the formation region, the middle silicon nitride film 54B and the lower silane film 54A of the passivation film 54 are sequentially removed to form a bonding opening 55. This bonding opening 55 is formed, for example, by anisotropic etching. Further, by the same manufacturing process as the process of forming the bonding opening 55, the transition metal film 53C on the upper layer of the wiring 53 can be removed in the region where the external terminal BP is formed, as shown in FIG. By performing these series of steps, the DRA of this example
MI is completed. Next, in the above-described DRAMI manufacturing process, the manufacturing process of each main part will be explained in detail. [Gate Wiring Formation Step 2] First, the lower electrode layer 33 of the information storage capacitor C of the stacked structure of the memory cell M shown in FIG. 27 is processed by a chopping etching method. In the chopping etching apparatus, as shown in FIG. 34 (schematic diagram of main parts), a plurality of branched etching gas supply pipes 72A to 72G are connected to an etching chamber 70 via a control valve 71A. Further, the etching chamber 70 is provided with an exhaust pipe 70A. Branched etching gas supply? -72A is a control valve 71B, a mass flow controller (MFC) 73
The etching gas G1 can be supplied to the etching chamber 70 through each of the etching gases G1 and A. The branched etching gas supply pipe 72B is configured to be able to supply the etching gas G2 to the etching chamber 70 through the control valve 71C and the mass flow controller 73B, respectively. Similarly. The branched etching gas supply pipe 72C is configured to be able to supply the etching gas G3 to the etching chamber 70 through the control valve 71D and the mass flow controller 73C, respectively. Each of the mass flow controllers 73A to 73C is a chopping controller (C
C) It is controlled by 74. The chopping controller 74 is configured to alternately control the flow rate of the etching gas flowing through each of the etching gas supply pipes 72A to 72G. The etching gas G1 flowing into the etching gas supply pipe 72A is an anisotropic etching gas such as a halogen compound (
CiCLF4) is used. The flow rate of this etching gas G1 is periodically increased or decreased as shown in FIG. 35 (gas flow rate time chart). This gas flow rate is controlled by the chopping controller 74. As shown in FIG. 38 (a diagram showing the relationship between etching speed and Taber angle), when the flow rate of etching gas G1 is increased, the anisotropy of etching can be enhanced. On the other hand, as the etching gases G2 and G3 flowing through the etching gas supply pipes 72B and 72C, respectively, an isotropic etching gas such as a halogen element (SF) is used. The flow rate of the etching gas G2 is periodically increased or decreased as shown in FIG. 36 (time chart of gas flow rate). This gas flow rate is controlled by the chopping controller 74, and the etching gas G2 is controlled by the etching gas G2.
When the flow rate of 1 is increased, it is decreased, and when it is decreased, it is increased. As shown in FIG. 38, etching gas G2
If the flow rate is increased, the isotropy of etching can be improved. The flow rate of the etching gas G3 is kept constant as shown in FIG. 37 (time chart of gas flow rate). This gas flow rate is controlled by the chopping controller 74, and the etching gas G3 is flowed less than when the flow rate of the etching gas G1 is increased and more than when it is decreased. As shown in Figure 38,
The etching gas G3 can improve the isotropy of etching. This chopping etching apparatus flows the etching gas G1 and the etching gas G2 into the etching chamber 70 as shown in FIG. 3511 and FIG. Processing polycrystalline silicon film. In other words, the polycrystalline silicon film is processed by alternately repeating anisotropic etching and isotropic etching. This etching is repeated at a high speed of 1 second or less. When etching is repeated at high speed, an organic polymer adheres to the sidewalls of a polycrystalline silicon film during anisotropic etching, and before the organic polymer is destroyed by isotropic etching, it becomes anisotropic again. Etching can be performed to deposit new organic polymers. Since the organic polymer acts as a stopper layer for side etching based on isotropic etching, it is possible to increase the etching anisotropy even during isotropic etching1.
When the polycrystalline silicon film is etched by anisotropic etching, etching remains, especially in the stepped portions of the underlying surface, resulting in over-etching of approximately 500%; however, using the chopping etching method described above Accordingly, the anisotropy of etching can be ensured while removing the etching residue by isotropic etching. Specifically, approximately 10% of the total flow rate of etching gas
] When the etching gas G1 is present, extreme anisotropy is exhibited, and when the etching gas G2 is approximately 30%, extreme isotropy is exhibited. According to the inventor's experimental results, approximately 10
Etching residue can be removed with an overetching amount of about 0 to 150%. Further, the chopping etching method may be performed using a combination of etching gas G3 (gas flow rate is constant) and etching gas Gl (gas flow rate is periodically increased and decreased). As described above, a method for forming a DRAMI in which a polycrystalline silicon film (lower electrode layer 33) formed on the surface of a base (interlayer insulating film 31) having a (43-24) step shape is patterned by anisotropic etching. In the step, the polycrystalline silicon film is patterned by alternately repeating anisotropic etching and isotropic etching. With this configuration, when patterning the polycrystalline silicon film, it is possible to reduce etching residue on the surface of the stepped portion of the base by isotropic etching while ensuring etching anisotropy, thereby reducing the amount of overetching. Reduced. Damage or destruction of the underlying surface can be prevented. (45-25) The anisotropic etching is performed again before the organic polymer adhering to the patterned side surface of the polycrystalline silicon film is destroyed by the isotropic etching. With this configuration, the organic polymer produced in the anisotropic etching acts as a stopper layer for the isotropic etching, so the amount of side etching in the isotropic etching can be reduced and the anisotropy of the etching can be increased. . Also, CI! Claim 46) The chopping etching apparatus includes an etching chamber 70, a gas supply system that supplies the anisotropic etching gas G1 via a mass flow controller 73A, and a mass flow controller 73B or 7.
Gas supply systems for supplying the isotropic etching gas G2 or G3 through the isotropic etching gas G2 or G3 are provided respectively, and the mass flow controller 73A, mass flow controller 73B or 7
A ticking controller 74 is provided to alternately and repeatedly control the amount of gas supplied to each of the 3C. With this configuration, the chopping etching method described above can be realized. Furthermore, in the chopping etching method, the anisotropic etching gas 01 and the isotropic etching gas G2 or G3 are continuously and alternately flown, so there is no exhaust treatment and the etching time can be significantly shortened. can. Note that this chopping etching method is not limited to the polycrystalline silicon film of the lower electrode layer 33, but also the gate electrode 26 of the memory cell selection MISFETQs and the upper electrode layer 35 of the stacked information storage capacitor C. It can also be applied to polycrystalline silicon films. Further, the chopping etching method can also be applied to the wirings 50 and 53 mainly made of aluminum film. In this case, the anisotropic etching gas G1 is CF, CHF, CCQF3, etc., the isotropic etching gas G2 is 0 base, or the G3 is BCfi.
Use 3rd grade.

[Gate wiring formation steps 1, 2, 3] M for memory cell selection of the memory cell M shown in FIG.
The gate electrode 26 (including the word line 2B) of ISFETQs, the lower electrode layer 33 of the information storage capacitive element C of the stacked structure of the memory cell M shown in FIG.
Each of the upper electrode layers 35 of the information storage capacitive element C having the stacked structure shown in FIG. 29 is processed by low temperature anisotropic etching. First, DRAMI (semiconductor wafer before dicing process) is directly adsorbed to a lower electrode in an etching chamber with an electrostatic adsorption plate interposed therebetween. This lower electrode is constantly cooled, and as a result, the semiconductor wafer is maintained at a temperature below room temperature. In this state, the gate electrode 26, the lower electrode layer 33, or the upper electrode layer 35 can be formed by performing anisotropic etching and processing the polycrystalline silicon film into a predetermined shape. Anisotropic etching gas (halogen compound 02CΩ2F,
) is deposited in large quantities on the surface of the semiconductor wafer, which has a lower temperature than the inner wall of the etching chamber, so the adoption of low-temperature anisotropic etching can reduce the flow rate of the anisotropic etching gas, and also deposits on the surface of the semiconductor wafer, which has a lower temperature than the inner wall of the etching chamber. It is possible to reduce the amount of contaminants attached to the surface. ■Wiring formation process 1, 2] Said 32i! The arrangement shown in 11A50. Each of the wiring lines 53 shown in FIG. 1 uses a continuous processing device that consistently processes etching processing, ashing processing, wet processing, and drying processing as shown in FIG. 39 (schematic configuration diagram of the device). and process it. The continuous processing apparatus 80 shown in FIG. 39 includes a load/unload chamber 81, a load chamber 82. Etching chamber 83, ashing chamber 84. Unloading chamber 85. A washing chamber 86 and a bake drying chamber 87 are provided in series. The load chamber 82, etching chamber 83, ashing chamber 84, and unload chamber 85 are each arranged in a buffer chamber (within the same vacuum system) 80A that is shielded from the atmosphere outside the apparatus. The buffer chamber 80A maintains a degree of vacuum of, for example, about 10 −3 to 101 [atmospheres]. The load/unload chamber 81 of the continuous processing device 80 is configured to be removably equipped with a load cassette 81A. This load cassette 81A is configured to accommodate a plurality of unprocessed semiconductor wafers 100. The semiconductor wafer 100 stored in the load cassette 81A is transferred to the buffer chamber 8 with a transfer arm 88A interposed therebetween.
It is transported to a load chamber 82 located inside 0A. The semiconductor wafer 10G transferred to the load chamber 8z is transferred to the etching chamber 83 via a swing arm 88B. The etching chamber 83 etches the wiring 50 or 53 by anisotropic etching@ (or the above-mentioned timing etching method) using an etching mask (photoresist film) formed in advance by photolithography.
form. The anisotropic etching gas includes halogen compounds (BCΩ3+CF4) and halogen elements (Cβ8
) using a mixed gas. The etching chamber 83 has a degree of vacuum of about 10-1 to 10-'' [atmospheric pressure] during etching, for example. The semiconductor wafer 100 subjected to the etching process in the etching chamber 83 is not exposed to the atmosphere. It is transported to the ashing chamber 84 via the swing arm 88G.The ashing chamber 84 has the etching mask (
photoresist film) with a halogen compound (CF or CH
Fs) and oxygen (OX). The ashing chamber 84 is maintained at a vacuum level of, for example, about 2 to 10 inches [atmospheric pressure], and the ashing chamber 84 has a vacuum of about 25 to 200 [atmospheric pressure].
The ashing process is performed at a temperature of about 'C]. The semiconductor wafer 100 that has been subjected to the ashing process in the ashing chamber 84 is transported to the unload chamber 85 via the swing arm 88C. The semiconductor wafer 100 transferred to the unloading chamber 85 is transferred to the washing processing chamber 86 via a transfer arm 88D. This water washing chamber 86 and the subsequent bake drying chamber 87 are as follows:
It is placed outside the buffer chamber 80A (inside the continuous processing device 80) and maintained at atmospheric pressure. The water washing chamber 86 is a process for removing halogen elements (CUt) generated in the etching process. This halogen element is processed using continuous processing equipment! When HlO is exposed to the atmosphere outside the wiring 80, the aluminum @ (or its alloy film) 50B of the wiring 50 or the aluminum film of the wiring 53 (
After the water washing treatment that corrodes the exposed surface of the semiconductor wafer (or its alloy film) 53B, the semiconductor wafer 100 is transported by the transport arm 88E to the bake drying chamber 87, and is dried in the bake drying chamber 87. When the drying process is completed, the semiconductor wafer 100 is transferred to the unload cassette 81.
It is stored in B. The semiconductor wafer 100 housed in the unload cassette 81B is subjected to a cleaning process, a drying process, and an inactivation process using a device different from the continuous processing bag [80]. The cleaning process removes foreign matter after etching, the aluminum film 50B of the wiring 50, or the aluminum film 5 of the wiring 53.
This is a process for removing side films (for example, compound thin films containing Afi, etc.) attached to the exposed surface of 3B. This cleaning treatment is performed using an alkaline cleaning solution or an acid cleaning solution, and the drying treatment is drying after cleaning. The inert treatment is a treatment for forming an oxide film on the exposed surface of the aluminum film SOB or 53B. As described above, in the DRAMI forming method of patterning the aluminum film (or its alloy film) 50B or 53B by (28-16) anisotropic etching, the aluminum film 50B or 53B is deposited and etched on the surface. The aluminum film 50B or 5 is etched in a vacuum system (inside the buffer chamber 80A) using a step of forming a mask (photoresist mask) and anisotropic etching using a halogen element and a metal halide as etching gas.
A step of applying a predetermined patterning to 3B, a step of removing the etching mask by ashing using a halogen compound and oxygen gas in the same vacuum system as the anisotropic etching step, and a step of removing the etching mask by ashing using a halogen compound and oxygen gas. The method includes a step of washing away the chlorine produced in the system in a system that is shielded from the atmosphere outside the device, and then drying it. With this structure, the ashing process is performed in the same vacuum system as the etching process, and the water washing process (8
6), corrosion of the aluminum film 50B or 53B can be reduced. Further, each of the wirings 50 and 53 uses a continuous processing device that consistently and continuously processes each of etching treatment, low-temperature ashing treatment, and vacuum baking treatment, as shown in FIG. 40 (schematic configuration diagram of the device), Process. The continuous processing apparatus 801 shown in FIG. 40 includes a load/unload chamber 81, a load chamber 82. Etching chamber 83, low temperature ashing chamber 84A, nitrogen gas blow vacuum baking chamber 89.
Each of the unloading chambers 85 is provided in series. The load chamber 82, etching chamber 83, and low temperature ashing chamber 84
A, nitrogen gas blower vacuum bake chamber 89, unload chamber 8
5 are arranged in the buffer chamber 80A. The semiconductor wafer 100 subjected to the etching process is transferred to the low temperature ashing chamber 8 with a swing arm 88C interposed therebetween.
Transported to 4A. The low-temperature ashing chamber 84A is placed in the buffer chamber 80A in the same vacuum system as the etching chamber 83, and performs the ashing process at a low temperature below room temperature (approximately 20 degrees Celsius).This ashing process is performed as described above. Similarly, the etching mask is removed using a mixed gas of a halogen compound and oxygen.
AQ in the side film attached to the side surface of the aluminum film 53B of No. 3 and the side surface of the resist is oxidized, and AQ, 03
This is an ashing process in a low-temperature region where it is difficult to reduce the temperature. Semiconductor wafer 10 subjected to the low temperature ashing process
0 is transported to a nitrogen gas blow vacuum baking chamber 89 via a swing arm 88C. This nitrogen gas blow vacuum baking chamber 89 uses a hot plate or a heating lamp to heat the surface of the semiconductor wafer 100 by about 200 to 400 [
'C] to reduce halogen elements generated during the etching process. Further, the nitrogen gas blowing vacuum baking chamber 89 is provided with the semiconductor wafer 10 .
High purity nitrogen gas (N2: dew point -60 [℃
] below) as a carrier gas to reduce the contamination of air and oxygen. After the vacuum baking process, a cleaning process, a drying process, and an inert process are sequentially performed in the same manner as described above. In this way, (26-15) patterning the aluminum film 50B or 53B by anisotropic etching
In the RAMI forming method, the aluminum film 50
A predetermined pattern is formed on the aluminum film 50B or 53B in a vacuum system by depositing B or 53B and forming an etching mask on this surface, and anisotropic etching using a halogen element and a halogen compound as an etching gas. The etching mask uses a halogen compound and oxygen gas in the same vacuum system as the anisotropic etching step. The method includes a step of removing by low-temperature ashing at room temperature or lower, and a step of performing a vacuum baking process on the aluminum film or its alloy film subjected to the predetermined patterning in the same vacuum system as the low-temperature ashing process. With this configuration, since the ashing process is performed at a low temperature and in the same vacuum system as the etching process, it is possible to prevent the AR in the side film attached to the side wall of the aluminum film 50B or 53B and the side surface of the resist from turning into AQ203. In addition to making it easier to remove the side film, the process from the anisotropic etching process to the vacuum baking process can be performed in the same vacuum system without being exposed to the atmosphere, and the side film can be easily removed. Since chlorine can be reduced by vacuum baking, the aluminum t
Corrosion of l150B or 53B can be reduced. Further, each of the wirings 50 and 53 is subjected to consistent and continuous processing of etching treatment, low temperature ashing treatment, vacuum baking treatment, cleaning treatment, and inactivation treatment as shown in FIG. 41 (schematic configuration diagram of the apparatus). Process using continuous processing equipment. The continuous processing apparatus 1aon shown in FIG.
, unloading chamber 85, cleaning chamber 90, inert chamber 9
1 in series. In other words. The continuous processing device 80■ is constructed by combining the continuous processing device 80I and a processing device that performs processing subsequent to that performed by the continuous processing device 80I. As described above, the cleaning chamber 90 is configured to remove foreign objects and side films using an acid and alkaline cleaning solution or an acid cleaning solution. The inert treatment chamber 91 is a treatment for forming an oxide film on the surface of the aluminum film 50B or 53B. Furthermore, the ashing treatment or low temperature ashing treatment is performed by
As mentioned above, a mixed gas of a halogen compound (CF4) and oxygen is used. Oxygen has the effect of removing the etching mask, and the halogen compound has the effect of increasing the rate of removal of the etching mask.The surface of the wiring 50 has a thin transition metal film 50C, and the surface of the wiring 53 has a thin transition metal film 50C. Each of the transition metal films 53C is provided with a film thickness, and in the ashing process using the mixed gas, each of the transition metal films 50G and 53G is removed by overashing. Therefore, in this embodiment,
The ashing process or low temperature ashing process is performed on the wiring 5.
0 transition metal film 50G or wiring 53 transition metal film 53G
Just ashing is performed with the mixed gas until the surface is exposed), and then overashing is performed with only oxygen gas. (Example 2) Example 2 is a second example of the present invention in which the area of the memory cell M in the DRAMI of Example I is reduced and the degree of integration is improved. FIG. 42 (principal part plan view) shows the planar structure of a DRAM memory cell array according to the embodiment (2) of the present invention. As shown in FIG. 42, the DRAMI of Example 3 has a connection hole 40B connecting one n-type semiconductor region 28 of the memory cell selection MISFET Qs of the memory cell M and the complementary data line (DL) 50. , is formed in self-alignment with the upper electrode layer 35 of the information storage capacitive element C having a stacked structure. In the connection hole 40B, the complementary data line 50 and the upper electrode layer 35 are electrically isolated by an isolation insulating film (35A) not shown in FIG. 42. Next, the fourth section describes a specific method of manufacturing the DRAM 1.
This will be briefly explained using FIGS. 3 to 45 (cross-sectional views of the main parts of CMOS of the memory cell array and peripheral circuits shown for each predetermined manufacturing process). First, in the same manner as in the step shown in FIG. 29 of Example I, after depositing a polycrystalline silicon film to form the upper electrode layer 35 of the information storage capacitor C of the stacked structure of the memory cell M,
An etching mask 67A is formed on this polycrystalline silicon film. The etching mask 67A is the 29th etching mask of Example I.
Unlike the etching mask B7 shown in the figure, the memory cell M
The memory cell array IIB is formed to cover the entire area of the memory cell array IIB including the connection region between the data line and the complementary data line (So). Thereafter, by sequentially etching the polycrystalline silicon film, dielectric film 34, and interlayer insulating film 31 in the peripheral circuit region using the etching mask 67A, the upper electrode layer is etched as shown in FIG. 35 is formed. By forming this upper electrode layer 35, the information storage capacitive element C having a stacked structure is substantially completed. Next, as shown in FIG. 44, an insulating film 36 is formed on the entire surface of the substrate including the surface of the upper electrode layer 35, and then interlayer insulating films 39 and 40 are sequentially laminated. Next, in the connection region between the memory cell M in the memory cell array IIB and the complementary data line (50), interlayer insulating films 40, 39. The insulating film 36 and the upper electrode layer 35 are each sequentially removed by etching to form a part of the contact hole 40B. This etching is performed, for example, by an anisotropic etching method (or a combination of isotropic etching methods), and the dielectric film 34 (or interlayer insulating film 31) is used as an etching stopper layer. Next, the dielectric film 3 exposed from a part of the connection hole 40B
4 (particularly the silicon nitride film 34A) as an oxidation-resistant mask, the surface of the upper electrode layer 35 exposed on the inner wall of a part of the connection hole 40B is oxidized, and the isolation insulating film (silicon oxide film) 35 is
Form A. This isolation insulating film 35A is formed to have a thickness of, for example, at least about 100 [nm]. After this,
By sequentially etching each of the dielectric film 341 and the interlayer insulating film 31 exposed from a part of the connection hole 40B,
As shown in FIG. 45, the connection hole 40B is completed. Further, the isolation insulating film 35A may be formed as an oxidation-resistant mask in a separate process, without using the dielectric film 34 as an oxidation-resistant mask (it may be removed during etching depending on the conditions). Next, in the same manner as in Example 2, an n° type semiconductor region 41 is formed, and complementary data lines 50 and other interconnections 50 are formed. The subsequent manufacturing steps are the same as those in Example I, and will therefore be omitted here. The memory cell M of the DRAMI of Example I has a connection hole 40B connecting the complementary data line 50, a gate electrode 26 of the memory cell selection MISFETQs,
Upper electrode layer 3 of stacked structure information storage capacitive element C
5, a margin for alignment in the manufacturing process is ensured. Upper layer electrode Jl! The lower electrode layer 35 has a sufficient fitting dimension with the lower electrode layer 33 below it, and the lower electrode layer 33 has a sufficient fitting margin with the gate electrode 26 below it. However, the DRAM of this embodiment
Since the connection hole 40B and the upper electrode layer 35 are each formed in a self-aligned manner, the area of the memory cell M can be reduced by an amount corresponding to the alignment allowance between them, and the degree of integration can be improved. can. (Example ■) This Example ■''&yo In the DRAM1 of the above-mentioned Example 1, the amount of charge storage of the information storage capacitor C of the stacked structure is improved to reduce the memory cell area. Increased line step coverage,
This is a third embodiment of the present invention. A method of manufacturing a DRAM memory cell array and peripheral circuit, which is Embodiment (2) of the present invention, will be briefly explained using FIGS. 46 to 50 (cross-sectional views of main parts shown for each predetermined manufacturing process). First, similarly to the process shown in FIG. 23 of Example I, a gate electrode (26) is formed on the entire surface of the substrate including the top of the gate insulating film 25.
and a polycrystalline silicon film 1 used as a word line (26).
The six interlayer insulating films 27G, in which each of the interlayer insulating films 27G is laminated one after another, are 0-layer insulating films formed with a thick film thickness of, for example, about 600 Cnm, in order to increase the amount of charge storage of the information storage capacitor C of the stacked structure. The insulating film 27G is deposited by the CVD method using inorganic silane gas and nitrogen oxide gas as source gases, as described above. Next, MI for memory cell selection of memory cell array IIB
SFETQs, peripheral circuit n-channel MISFETQn
, the interlayer insulation in each formation region of p-channel MI 5FETQp! Etched on l127C,
0 interlayer insulation 112 forming a thin interlayer insulation film 27
7 is etched to a film thickness of, for example, 300i, nml. Next, as shown in FIG. 46, the interlayer insulating film 27.2
70. Each of the polycrystalline silicon films is sequentially etched by anisotropic etching to form the gate electrode 2B and word line 26, respectively. As shown in FIG. 46, memory cell selection MISFETQs, n-channel MISFETQn, P
Each gate electrode 26 of channel MI S FETQp
A thin interlayer insulating film 27 is formed thereon. On the other hand, a thick interlayer insulating film 27C is formed on the word line 26. Next, as shown in FIG. 47, the n-type semiconductor region 28, p
Each of the type semiconductor regions 30 is formed. n-type semiconductor region 2
By forming 8, MISFE for memory cell selection
TQs is almost completed. Next, as shown in FIG. 48, sidewall spacers 29 are provided on the sidewalls of the gate electrode 26 and the interlayer insulating film 27 above the gate electrode 26, and sidewall spacers are provided on the sidewalls of the word line 26 and the interlayer insulating film 27C. 29A respectively. Next, an interlayer insulating film 31 is formed on the entire surface of the substrate including the interlayer insulating films 27 and 27G, and then, as shown in FIG. 49, connection holes 31A and 32 are formed in the same manner as in Example I. do. Next, as shown in FIG. 50, in the formation region of the memory cell M, the interlayer insulating film 27 is
．． The lower electrode layer 33 of the information storage capacitive element C having a stretched stacked structure is formed on top of each of the electrodes 27C. As shown in FIG. 50, the area of the lower electrode layer 33 increases in the height direction above the word line 26, so that the amount of charge storage in the information storage capacitor C of the stacked structure can be increased. I can do it. Further, since the lower electrode layer 33 has a reduced step shape and a small aspect ratio in the upper part of the gate electrode 26, the complementary data line 50 is formed in the connection area between the complementary data line 50 and the memory cell M.
step coverage can be improved. Also,
Since the lower electrode layer 33 can increase the amount of charge storage as described above, the film thickness can be reduced, and the introduction of n-type impurities and processing can be simplified. The steps after the step of forming the lower electrode layer 33 are the same as those in Example 1, so the explanation here will be omitted. In this way, the memory cell M is arranged at the intersection of the (37-20) complementary data line 50 and the word line 26. This memory cell M is MISFETQs for memory cell selection.
In a DRAMI configured of a series circuit of a stacked information storage capacitor C and a stacked information storage capacitor C, the lower electrode layer 3 of the stacked information storage capacitor C of the memory cell M
3 is the MISFE for memory cell selection of this memory cell M.
The gate electrode 26 of TQ8 and the word line 26 which selects another memory cell M adjacent to the gate electrode 26 in the gate width direction are configured to overlap with each other, and the gate electrode 26 between the lower electrode layer 33 and the word line 26 is configured to overlap. The interlayer insulating film 27C is connected to the lower electrode layer 3.
3 and the gate electrode 26. With this configuration, the lower electrode layer 33
The interlayer insulating film 27C between the word line 26 and the word line 26 is thickened. Since the step of the lower electrode layer 33 is made higher, the lower electrode layer 33
It is possible to increase the area of the information storage capacitive element C in the height direction, thereby increasing the charge storage amount of the information storage capacitor C of the stacked structure, and also to make the interlayer insulating film 27 between the lower electrode layer 33 and the gate electrode 2B thinner. <shi, MISFETQ for memory cell selection
Since the level difference at the connecting portion between s and the complementary data line 50 is lowered, the aspect ratio at the connecting portion can be reduced and disconnection defects of the complementary data line 50 can be reduced. As a result, the α-ray soft error withstand voltage can be improved, the degree of integration of the DRAM1 can be improved, and the electrical reliability of the DRAM1 can be improved. Note that the interlayer insulating films 27 and 27G may be formed by insulating films formed in separate steps. (Example ■) This Example (■) is a DRAM in which the lower electrode layer of the information storage capacitor C of the stacked structure of the memory cell is thickened to increase the amount of charge storage in the DRAM of Example I. This is a fourth embodiment of the invention. The cross-sectional structure of a DRAM memory cell according to the embodiment (2) of the present invention is shown in FIGS. 51 to 54 (cross-sectional views of main parts). In the memory cell M of the DRAM1 shown in FIG. For example, the opening dimension L of the connection hole 32 (the gate electrode 26
and the word line 26) is approximately 1.0 [μm], the thickness T of the lower electrode layer 33 is approximately 500 [nm] or more than that (T≧1/2XL). ). The stacked structure information storage capacitor C configured in this manner increases the area of the end face of the lower electrode layer 33 and increases the amount of charge storage on this end face, so the area of the memory cell M can be reduced. However, the degree of integration of DRAMI can be improved. In the DRAMI memory cell M shown in FIG. 52, the lower electrode layer 33 of the information storage capacitor C having a stacked structure is formed to have a thickness just before the connection hole 32 is filled. In the information storage capacitive element C having the stacked structure configured in this way, the thickness of the lower electrode layer 33 is thick to some extent.
The amount of charge storage can be increased at the end face of the lower electrode layer 33, and the lower electrode layer 33 is formed along the step shape of the connection holes 32 and 31A. Since the area of the lower electrode layer 33 can be increased in the height direction by an amount corresponding to the step, the amount of charge storage can be increased. In other words, an increase in the amount of charge stored in the information storage capacitive element C of the stacked structure can reduce the area of the memory cell M and improve the degree of integration of the DRAM1. In the DRAMI memory cell M shown in FIGS. 53 and 54, the lower electrode layer 33 of the information storage capacitor C having a stacked structure is composed of a plurality of layers. Lower electrode layer a of the stacked structure information storage capacitive element C shown in FIG.
3 has a two-layer structure in which lower electrode layers 33E and 33F are laminated, respectively. The lower electrode layer 33 is formed by depositing a polycrystalline silicon film forming the lower electrode layer 33E, introducing n-type impurities by thermal diffusion or ion implantation, and then depositing the polycrystalline silicon film forming the lower electrode layer 33F. After the films are deposited, n-type impurities are introduced in the same manner, and then each polycrystalline silicon film is processed. In other words, as the lower electrode layer 33 becomes thicker, it becomes difficult to control the impurity concentration distribution, so it is divided into multiple layers, and n-type impurities are introduced into each of the divided layers to increase the overall impurity concentration. distribution is made uniform. 54th
Similarly, the lower electrode layer 33 of the information storage capacitive element C having the stacked structure shown in the figure includes lower electrode layers 33E, 33F, 33
It has a three-layer structure in which G is laminated. The information storage capacitive element C having the stacked structure configured in this manner can make the impurity concentration distribution of the lower electrode layer 33 uniform. (Embodiment ■) This embodiment V is a fifth embodiment of the present invention in which the narrow channel effect of the memory cell selection MISFETQs and the n-channel MISFETQn of the memory cell in the DRAM of the embodiment I is reduced. The DRAMI according to the embodiment (2) of the present invention has a p-type impurity (channel stopper region 24) shown in FIG.
The impurity (24p forming A) is introduced by high-energy ion implantation. The energy amount of the ion implantation method is approximately 100 ~
It is carried out at about 160 [KaV]. The p-type impurity 24p introduced by this ion implantation method using high energy has a maximum impurity concentration peak value at a position deeper than the inter-element isolation insulating film 23 at the time of introduction. The p-type impurity 24p
When introducing the p-type impurity 24p, an etching mask (photoresist film) obtained by processing the mask (62) may be used.The p-type impurity 24p penetrates the silicon oxide film 60A,
Since the p-type impurity 24p may be introduced into the main surface of the n-type well region 21, when introducing the p-type impurity 24p,
An impurity introduction mask, such as a photoresist film, is formed on the main surface of 1. After introducing the p-type impurity 24p, an insulating film 23 for element isolation is formed in the same manner as in Example 1,
At the same time as this formation, the p-type impurity 24p is diffused to form a p-type channel stopper region 24A and a p-type semiconductor region 24B, respectively. As described above, in the method for manufacturing DRAM1, the p-type impurity 24p forming the p-type channel stopper region 24A is introduced by high-energy ion implantation. With this configuration, the p-type impurity 24p is introduced into the deep region of the P-type well region 22, and the
Since it is possible to reduce the amount of lateral diffusion during the formation of the p-type well region 22, especially the channel formation region, an increase in the impurity concentration of the p-type well region 22, especially the channel formation region, can be suppressed.
It is possible to reduce the narrow channel effect of each of the i- and n-channel MISFETs Qn and Qo. Furthermore, since the p-type impurity 24ptI- can be introduced into the deep region of the p-type well region 22, it is possible to reduce the fact that the p-type impurity 24p is eaten by the insulating film 23 for element isolation when it is formed.
The impurity concentration of the p-type channel stopper region 24A is increased,
It is possible to increase the threshold voltage of the parasitic MO8 and ensure isolation between elements. (Example 2) Example 2 is a sixth example of the present invention in which the resin film on the passivation film is divided in the DRAMI of Example 2. The planar structure of a semiconductor wafer forming a DRAM according to Example 2 of the present invention is shown in FIG. 55 (plan view of main parts). As shown in FIG. 55, the semiconductor wafer 100 has a plurality of DRAMIs of Example I arranged in a matrix. The semiconductor wafer 100 shown in FIG. 55 shows a state before the dicing process. Each DRAMI is arranged within an area defined by a scribing area (dicing area) 100A. The passivation film 5 described in the first embodiment is formed on the surface of each DRAM1 arranged on the semiconductor wafer 100.
4 upper layer resin film (e.g. polyimide resin film) 54C
is coated. This resin film 54C covers the scribe area 100A of the semiconductor wafer 100 and each DRAM1.
It is not coated on the area corresponding to the external terminal BP of
Furthermore, the surface of each DRAMI is divided into a plurality of parts. The resin film 54C is applied to increase the α-ray soft error withstand voltage, so the memory cell array IIA, the sense amplifier circuit (SA) 13, the column address decoder circuit (YD E C) 12, etc. It is applied to some of the direct peripheral circuits that should be secured. In other words, the resin film 54C divides the other parts of the direct peripheral circuit and the area on the indirect peripheral circuit, which do not need to ensure the α-ray soft error withstand voltage, as divided regions. Other parts of the direct peripheral circuit include a row address decoder circuit (XD E
C) 14, word driver circuit (WD) 15, etc.
Indirect peripheral circuits include clock system circuits, buffer circuits, and the like. By dividing this resin film 54C,
Silicon nitride film 54B of the lower layer passivation film 54
It is possible to alleviate the stress that acts on the films and the semiconductor wafer 100 itself. The method for forming the resin film 54G is as follows. First, a resin film is applied on the surface of the underlying silicon nitride film 54B, and a first baking process is performed.
For example, after applying 80 to 90 ['C] and 800 to 1000 [seconds], for example, 120 to 140 ['C] and 80
0 to i o o oc seconds]. Next, using photolithography and etching techniques, the scribe area 1GOA of the resin film, the external terminal BP area, and the divided area are removed, respectively. Then, the resin film is again subjected to a second baking process to form the aforementioned resin film 54C. This baking process is performed, for example, at 150 to 200[:C], 800 to 1000[seconds], and then again, for example, at 300 to 400['C],
800 to 1000 [seconds]. In the second baking process, the resin film 54C has the largest stress acting on its underlying layer and the semiconductor wafer 100;
Since the resin film 54G is divided, the stress is reduced. Note that even when the semiconductor wafer 100 is subjected to a dicing process and the DRAM1 is made into individual semiconductor chips, as shown in FIG. There isn't. In this way, (3B-21) directly controls the information write operation and information read operation of the memory cell array IIA and the memory cells M arranged on the main surface of the p-type semiconductor substrate 22 (or the main surface of the semiconductor wafer 100). In a DRAM in which a resin film 54C& is coated on the surface of a direct peripheral circuit and other indirect peripheral circuits, the resin film 54C is divided into a plurality of parts. With this configuration, stress based on the difference in linear expansion coefficient between the p-type semiconductor substrate 20 (or semiconductor wafer 1oO) and the resin film 54G can be alleviated.
It is possible to prevent warpage of the p-type semiconductor substrate 20 and generation of cranks in the film on its main surface. Since the resin film 54G is applied to the semiconductor wafer 100 before the dicing process and is formed by baking, it reduces the contact failure of the probe needle during the probe test, increases the reliability of the wafer inspection process, and improves the yield. can be improved. (40-22) The DR before the scribing step
A step of applying a resin film 54C to the entire surface of the semiconductor wafer 100 in which a plurality of AM1 formation regions are arranged in rows and columns, and a step of coating the resin film 54C between the formation regions of each DRAMI (scribe area ioOA) and external terminals. a step of removing the BP region and dividing the resin film 54G on the formation region of each DRAM 1;
0 scribe area 100A to form a plurality of DRAMs 1. With this configuration, the step of dividing the resin film 54G can be carried out between the scribe area 100A of the semiconductor wafer 100 and the external terminal B.
Since this can be performed in the step of removing the resin film 54G in the region P, the number of steps for forming the DRAMI can be reduced by the amount corresponding to the step of dividing the resin film 54C. (Embodiment 2) Embodiment 2 is a seventh embodiment of the present invention in which the number of column address decoder circuits in the DRAM of Embodiment I is reduced. The planar structure of a DRAM memory cell array according to the embodiment (2) of the present invention is shown in FIG. 56 (a plan view of the main part) and FIG. 57 (a plan view of the main part in a predetermined manufacturing process). When reducing the number of column address decoder circuits (YDEC) 12 shown in the DRAMI of the embodiment (2), as shown in FIG.
)50 are arranged. The column select signal line 50 is configured to control the column switch n-channel MISFET Qy by the column address decoder circuit 12. n-channel MISFETQ for column switch
y is configured to connect each of the complementary data line 50 and the common data line I10. The column select signal line 50 is made of the same conductive layer ( They are formed in the same manufacturing process). Basically, one column select signal line 50 is arranged for one set of complementary data lines 50, although it differs depending on the arrangement form of the column switch n-channel MISFET Qy. The DRAM1 of this embodiment has two sets of complementary data lines (four data lines DL, DL), one set for every 5G. A dummy column select signal line is arranged between the complementary data line 50 and another set of complementary data lines 50. The dummy column select signal line is arranged to reduce the widening of the spacing between the complementary data lines 50 in this region and to make the spacing of the complementary data lines 50 uniform. In other words, when forming an etching mask (for example, a photoresist film) using photolithography, the size of the etching mask is reduced in widely spaced areas compared to other areas due to the diffraction phenomenon during exposure, but the dummy column The select signal line is arranged to reduce this phenomenon. The etching masks to be used include the lower electrode layer 33 of the stacked structure information storage capacitor C;
This is a mask for processing the complementary data line 50 or the shunt word line 53. However, in the DRAM1 of the fifth embodiment, such a phenomenon can be ignored, so the dummy column select signal line is omitted. The column select signal line 50 widens the interval between the complementary data lines 50 similarly to the dummy column select signal line. In particular, the lower electrode layer 33 of the stacked structure information storage capacitor C of the memory cell M near the column select signal line 50 is larger than the lower electrode layer 33 of the other stacked structure information storage capacitor C. It consists of size (large amount of charge accumulation). In other words, since this lower electrode layer 33 causes the same phenomenon as when the dummy column select signal line is arranged, the size is made larger in advance by an amount corresponding to the reduction in size. This lower electrode layer 33 has a protrusion 33H extending (crossing) in the plane direction below the column select signal line 50.
This makes the size larger. In other words, the protrusion 3
Since 3H can be formed within the area occupied by the column select signal line 50, D
The degree of integration of RAMI can be improved. The small-sized lower electrode layer 33 is configured so as to obtain the minimum amount of charge storage that enables information read operation and ensures α-ray soft error withstand voltage. On the other hand, the lower electrode layer 33, which is large in size, is configured so that at least the minimum amount of charge storage can be obtained, taking into consideration the reduction in size during processing. There is no particular problem with this lower electrode layer 33 because of its large size.
Therefore, the DRAMI of this embodiment has two types of stacked structure information storage capacitive elements C each having a lower electrode layer 33 of a different size. In this way, the memory cell selection MISFF, T
A memory cell M consisting of a series circuit of Qs and a stacked information storage capacitive element C is arranged. Complementary data lines 50 for each of the two sets of complementary data lines 50
A DRAM 1 having a column select signal line 50 extending in the same conductive layer and in the same direction as the column select signal line 50 and connected to one data line of the complementary data lines 50 adjacent to the column select signal line 50. The lower electrode layer 33 of the information storage capacitor C of the stacked structure of the memory cell M is configured to have a larger size than the lower electrode layer 33 of the information storage capacitor C of the stacked structure of the other memory cells M. With this configuration, the size of the etching mask used to process the lower electrode layer 33 is reduced by a diffraction phenomenon during exposure based on the expansion of the dimension between the complementary data lines 50 corresponding to the arrangement of the column select signal lines 50. Therefore, the size of the lower electrode layer 33 of the information storage capacitor C of the stacked structure of the memory cell M connected to one data line adjacent to the column select signal line 50 is increased in advance. The electrode layer 33 is not reduced in size below a set value, and the amount of charge storage in the information storage capacitive element C having a stacked structure can be ensured. As a result, the α-ray soft error withstand voltage can be improved and the area of the memory cell M can be reduced, so that the degree of integration of the DRAM can be improved. (Example 2) Example 2 is an eighth example of the present invention in which the film quality of the interlayer insulating film between the gate wirings and between the wirings is improved in the DRAM of Example I. The schematic structure of the CVD apparatus which is Embodiment 2 of the present invention is shown in the 58th section.
This is shown in the figure (block diagram showing the gas supply system). The CVD apparatus shown in FIG. 58 mainly consists of one reactor body 110
, vacuum pump 111, source gas supply pipes 112 and 11
3. Carrier gas supply pipe 114. Mass flow controller 115 and control valve 116 arranged in each supply route
It consists of This CVD apparatus is configured to form a silicon oxide film with high step coverage and small film shrinkage. This CVD apparatus is similar to the embodiment I described above.
Specifically, in the DRAMI, an interlayer insulating film 27, a sidewall spacer 29, and an interlayer insulating film 31 are formed. The source gas supply pipe 112 is configured to supply a source gas G4, such as an inorganic silane gas (S i H4, Si, H, etc.) to the reactor body 110 . The source gas supply pipe 113 is connected to the source gas G5, for example, nitrogen oxide gas (
N, o') to the reactor body 110. The carrier gas supply pipe 114 is a carrier gas G.
6, for example, is configured to supply nitrogen gas (N,). As shown in FIG. 59 (schematic configuration diagram), the reactor body 110 has a double structure in which a reaction tube (inner tube) 110B is provided inside a reaction tube (outer tube) 110A. . A heater 1 is installed on the outer periphery of the reaction tube (outer tube) 110A.
10C is placed. Reactor body 1 shown in Fig. 59
One end side of 10 is connected to a vacuum pump 111. In addition, a semiconductor wafer 100 is placed on the other end side of one reactor body 110.
Inside the reactor body 110, which is provided with an opening/closing door 110D into which a plurality of wafers can be inserted (performing batch processing), there is a connection between the deposition surface of the silicon oxide film of the semiconductor wafer 100 and the supply direction of the reaction gas. The structure is such that the semiconductor wafer 100 can be inserted and held in a leaning state so that the wafers intersect. A nozzle 112A connected to the source gas supply pipe 112 is provided in the reaction tube 110B at the other end of the reactor body 110.
A nozzle 113A connected to the source gas supply pipe 113 is arranged near the nozzle 113A. Figure 60 (
As shown in the main part enlarged sectional view), the nozzle 112A supplies the source gas G4 into the reaction tube 110B, and the nozzle 11
3A is configured to supply the source gas G5 into the reaction tube 110B so as to be mixed with the source gas G4. Although not limited to this configuration, the respective gas supply directions of the nozzle 112A and the nozzle 113A are configured to intersect with each other. The source gas G4, such as SiH4, supplied from the nozzle 112A has a thermal decomposition temperature of about 400 ['C]. The source gas G5, such as N and O, supplied from the nozzle 113A has a thermal decomposition temperature of about 550 ['C]. Therefore, simply supply each of the source gases G4 and G5 to the reaction tube 1.
10B, SiH4 is thermally decomposed first, and foreign substances such as silicon and porous silicon oxide adhere to the inner wall of the reaction tube 110B and the surface of the semiconductor wafer 100. However, in the CVD apparatus of this embodiment, In particular, mixing each of source gases G4 and G5 before reaching the thermal decomposition temperature of source gas G4,
Since the source gas G4 is diluted, the attachment of foreign matter as described above can be reduced. For example, the conditions for forming a specific example of a silicon oxide film are as follows.

[Generation conditions]

1. Source gas flow rate Source gas G4 1 1 2. Gas pressure 40-60 [pa] 3. Generation temperature 800-830 ["C] Also, the source gas G
4 and G5 may be mixed outside the reaction tube 110B, that is, in the gas supply path. In this way, (47-26) the semiconductor wafer 100 is held in the reactor body 110, and the source gas G4 (inorganic silane gas) and the source gas G5 (nitrogen oxide gas) are introduced into the reactor body 110 from one end side. supply. In the CVD apparatus for forming a silicon oxide film on the surface of the semiconductor wafer 100, source gases G4 and G5 are mixed at a temperature below the thermal decomposition temperature of the source gas G4 to generate a source gas, and this source gas is subjected to the reaction. Furnace body 110
It is supplied to the semiconductor wafer 100 side held within the interior. With this configuration, the source gas can be mixed at a temperature below the thermal decomposition temperature of the source gas G4, and the concentration of the source gas G4 can be diluted. This reduces the amount of foreign matter (silicon particles, etc.) scattered between the holder and the inner wall of the reactor body 110, and the amount of foreign matter that gets mixed into the silicon oxide film formed on the surface of the semiconductor wafer 100. Since foreign matter adhering to the surface can be reduced, the quality of the silicon oxide film can be improved. Also, CVD'l
In this case, foreign matter adhering to the inner wall of the reactor body 110 can be reduced. (Example 2) Example 2 is a ninth example of the present invention in which the quality of the interlayer insulating film 51 between the wiring 50 and the wiring 53 in the DRAM of Example I is improved. FIG. 61 (schematic configuration diagram) shows a continuous processing apparatus which is Embodiment 2 of the present invention. The continuous processing apparatus shown in FIG.
In Ml, after forming a lower silicon oxide film (deposited type insulating film) 51A of the interlayer insulating film 51, a silicon oxide film (coated type insulating film) 51B, a silicon oxide film (deposited type insulating film) 51B, and a silicon oxide film (deposited type insulating film) 51A are deposited on the upper layer. This is an apparatus that continuously forms each of the films 51C and 51C. This continuous processing apparatus mainly includes a wafer loading section 120A, an SOG coating section 121. Load lock part 12
2, wafer transport section 123, lamp annealing section 124.
Etched portion 125, insulating film deposited portion 126. Each of the wafer unloading sections 120B includes a wafer unloading section 120B. A plurality of semiconductor wafers 100 are stored in the wafer loading section 120A. After the wiring 50 is formed in the DRAMI of Example I, the semiconductor wafer 100 has a silicon oxide film 51A deposited on its surface. This semiconductor wafer 100 is then transported to the SOG coating section 121, and SOG is coated on the silicon oxide film 51A.
A silicon oxide film (coating type insulating film) 51B is applied by a method. Semiconductor wafer 10 coated with the silicon oxide film 51B
0 is transported to the lamp annealing section 124 via the load lock section 122 and the wafer transport section 123, respectively. This lamp annealing section 124 performs a low temperature baking treatment (mineralization treatment) and a hardening baking treatment on the silicon oxide film 51B. The semiconductor wafer 100 subjected to the baking process is transported to an etching section 125 via a wafer transport section 123. The etched portion 125 is made of the silicon oxide film 51.
Etching (etchback) is performed on the surface of B to remove the excess silicon oxide film 51B. Specifically, the silicon oxide film coated on the wiring 50 in the portion where the connection hole 52 is to be opened is removed. The semiconductor wafer 100 on which the surface of the silicon oxide film 51B has been etched is immediately transported to the insulating film deposition section 126 via the wafer transport section 123. This insulating film deposition section 126 deposits a silicon oxide film (deposited type insulating film) 51C on the surface of the silicon oxide film 51B. Semiconductor wafer 10 on which the silicon oxide film 51G is deposited
0 is transported to the wafer unload section 120B via the wafer transport section 123. This continuous processing apparatus deposits a silicon oxide film 51B on the first interlayer insulating film 51A, performs a flattening process on this silicon oxide film 51B, then etches the silicon oxide film, and then immediately (outside the apparatus) (without contacting the atmosphere) silicon oxide film 5
In order to deposit a silicon oxide film 51C on the surface of 1B,
- It is configured so that each process can be performed continuously throughout. In this way, (41-23) the underlying surface (silicon oxide film 51
A) Silicon oxide film (coated insulating film) 51B coated on top
After baking, a silicon oxide film (deposition type insulating film) 51C is deposited on the surface of the silicon oxide film 51B.
The method for forming Ml includes a step of applying the silicon oxide film 51B in a system (inside the device) shielded from the atmosphere, a step of subjecting the silicon oxide film 51B to a baking process, and a step of etching back the silicon oxide film 51B. , the silicon oxide film 51
With this configuration, in which the steps of depositing a silicon oxide film (deposited type insulating film) 51C are sequentially performed on the surface of the silicon oxide film 51C, the silicon oxide film 51G can be covered with the silicon oxide film 51G without being exposed to the atmosphere after the application and baking process of the silicon oxide film 51B. Therefore, moisture absorption of the silicon oxide film 51B can be reduced, and deterioration of the film quality of the silicon oxide film 51B can be reduced. As a result, the silicon oxide film 51B
It is possible to improve the adhesion between the silicon oxide film 51C and the upper silicon oxide film 51C, and to prevent changes in the etching rate of the silicon oxide film 51B. Further, as shown in FIG. 62 (schematic configuration diagram), the continuous processing apparatus includes a wafer transport section 127, a wafer cooling section 128, and a wafer cassette between the SOG coating section (batch type) 121A and the wafer transport section 123. Each of the sections 129 may be arranged in sequence. This continuous processing equipment is SO
Silicon oxide film 51B is applied in a batch manner in G coating section 121A.
This device is ideal for cases where it is not possible to apply a flattening treatment immediately after coating. In other words, this continuous processing apparatus is configured so that after the silicon oxide film 51B is coated until it is transported to the lamp annealing section 124, the process does not come into contact with the atmosphere outside the apparatus. The invention made by the present inventor has been specifically explained above based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course. For example, the present invention can be applied to a semiconductor integrated circuit device such as a microcomputer (one-chip microcomputer) that uses a DRAM as one unit. Further, the present invention is not limited to the DRAM, but is applicable to SRAM.
, ROM, and other semiconductor integrated circuit devices having a zero storage function. [Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below. (1) In a semiconductor integrated circuit device having a memory function,
The degree of integration can be improved. (2) In the semiconductor integrated circuit device, soft error withstand voltage can be improved. (3) In the semiconductor integrated circuit device, the operating speed can be increased. (4) In the semiconductor integrated circuit device, electrical reliability can be improved. (5) In the semiconductor integrated circuit device, processing accuracy in manufacturing can be improved. (6) In the semiconductor integrated circuit device, manufacturing yield can be improved. (7) In the semiconductor integrated circuit device, the number of manufacturing steps can be reduced. (8) In the semiconductor integrated circuit device, the quality of the insulating film used therein can be improved. (9) It is possible to provide a device for improving the film quality of the insulating film as described in (8) above. (10) In the semiconductor integrated circuit device, the driving ability of an external device can be improved. (11) In the semiconductor integrated circuit device, it is possible to planarize the surface of the element forming surface. (12) In the semiconductor integrated circuit device, the manufacturing process can be stabilized. (13) It is possible to provide an apparatus that stabilizes the manufacturing process described in (12) above. (14) In the semiconductor integrated circuit device, it is possible to increase the breakdown voltage of the element.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part of a DRAM that is Example I of the present invention, and FIG. 2 is a partial cross-sectional plan view of a resin-sealed semiconductor device that seals the DRAM. FIG. 3 is a chip layout diagram of the DRAM, FIG. 4 is an enlarged layout diagram of the main parts of the DRAM, FIG. 5 is an equivalent circuit diagram of the main parts of the DRAM, and FIG.
FIGS. 7 and 8 are plan views of the main parts of the DRAM, and FIG. 9 is a plan view of the main parts of the DRAM in a predetermined manufacturing process. FIG. A plan view; FIG. 10 is a cross-sectional view taken along section line ■--■ in FIG. 9; FIG. 11 is a cross-sectional view taken along line mm in FIG. 6. FIG. 12 is a sectional view of a main part of the DRAM including an output stage circuit area. FIG. 13 is an equivalent circuit diagram of a main part of the word boost circuit of the DRAM. FIG. 14 is a plan view of an essential part of an element used in the word boost circuit, FIG. 15 is a sectional view of an essential part of an external terminal area of the DRAM, and FIGS. 34 is a schematic diagram of the main part of the chopping etching device; FIGS. 35 to 37 are time charts of the gas flow rate of the etching device; FIG. 38 is a sectional view of the main parts shown for each manufacturing process; , a diagram showing the relationship between etching speed and taper angle, FIGS. 39 to 41 are schematic configuration diagrams of a continuous processing apparatus, FIG. 43 to 45 are sectional views of essential parts of the DRAM showing each manufacturing process, and FIGS. 46 to 50 are DR
51 to 54 are sectional views of essential parts of an AM showing each manufacturing process, and FIGS. 51 to 54 are sectional views of essential parts of a DRAM, which is an embodiment (2) of the present invention. FIG. 55 is an embodiment (2) of the present invention. A plan view of the main parts of the semiconductor wafer. FIG. 56 is a plan view of essential parts of a DRAM which is Embodiment 2 of the present invention. FIG. 57 is a plan view of essential parts in a predetermined manufacturing process of the DRAM, and FIG. 58 is a block diagram showing a gas supply system of a CVD apparatus which is Embodiment (2) of the present invention. FIG. 59 is a schematic configuration diagram of the main parts of the CVD apparatus, FIG. 60 is an enlarged sectional view of the main parts of the CVD apparatus, and FIGS. 61 and 62 are continuous FIG. 1 is a schematic configuration diagram of a processing device. In the figure, 1...DRAM, M...memory cell, C...
・Stacked structure capacitive element for information storage, Qs... MI 5FET for memory cell selection, Qn, Qp-MI 5
It is an FET. Figure 5

Claims (1)

[Claims] 1. Memory cells each consisting of a memory cell selection MISFET connecting one semiconductor region to a data line and an information storage capacitive element connected in series to the other semiconductor region are arranged in a matrix. In a semiconductor integrated circuit device having a DRAM, a capacitive element for information storage of a memory cell of the DRAM has a lower layer in which a part is connected to the other semiconductor region of the memory cell selection MISFET and the other part is disposed on a gate electrode. It is composed of an electrode layer, a dielectric film laminated on the lower electrode layer, and an upper electrode layer laminated on the dielectric film, and a correction pattern is formed on the lower electrode layer to increase its surface area. A semiconductor integrated circuit device characterized by: 2. The correction pattern of the lower electrode layer is arranged on the connection side between one semiconductor region of the memory cell selection MISFET of this memory cell and the data line, and the correction pattern is arranged on the connection side of the lower electrode layer in the planar direction. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed to protrude. 3. In a semiconductor integrated circuit device in which wiring is extended on a base surface having a stepped shape, the wiring is formed by sequentially laminating each of a transition metal film deposited by a CVD method, an aluminum film or an aluminum alloy film deposited by a sputtering method. 1. A semiconductor integrated circuit device comprising a composite film. 4. The wiring is composed of a three-layer composite film in which a transition metal film deposited by a CVD method, an aluminum film or an aluminum alloy film deposited by a sputtering method, and a transition metal film deposited by a sputtering method are sequentially laminated. 4. The semiconductor integrated circuit device according to claim 3, wherein: 5. The upper layer wiring formed on the upper layer of the wiring is formed by sequentially laminating each of a transition metal film deposited by sputtering, an aluminum film or aluminum alloy film deposited by sputtering, and a transition metal film deposited by sputtering. 5. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is formed of a composite film having a layered structure. 6. The semiconductor integrated circuit device according to each of claims 3 to 5, wherein the transition metal film deposited by the CVD method below the wiring is a high melting point metal silicide film, a titanium nitride film, or the like. . 7. In a semiconductor integrated circuit device having an external terminal formed of the same conductive layer as the internal wiring, to which a bonding wire is connected through an opening formed in a passivation film, the internal wiring is made of an aluminum film, an aluminum alloy film, or a transition metal. 1. A semiconductor integrated circuit device comprising a composite film in which films are sequentially laminated, and wherein the external terminal is comprised of an aluminum film or an aluminum alloy film from which the transition metal film has been removed. 8. The semiconductor integrated circuit according to claim 7, wherein the transition metal film on the aluminum film or aluminum alloy film of the external terminal is removed in a region defined by an opening formed in the passivation film. Method of manufacturing the device. 9. The semiconductor according to claim 7 or 8, wherein the internal wiring is composed of a composite film in which each of a transition metal film, an aluminum film or an aluminum alloy film, and a transition metal film are sequentially laminated. Integrated circuit device. 10. Form an insulating film on the gate electrode of the MISFET,
In the semiconductor integrated circuit device in which sidewall spacers are formed on the sidewalls of the gate electrode and the sidewalls of the insulating film above the gate electrode, the insulating film on the gate electrode and the sidewall spacers are each coated with an inorganic silane gas and a nitrogen oxide gas as a source gas. A semiconductor integrated circuit device characterized in that it is formed using a silicon oxide film deposited by a CVD method. 11. Consisting of a lower electrode layer formed on a base insulating film, a dielectric film formed on the base insulating film and the surface of the lower electrode layer, and an upper electrode layer formed on this dielectric film. In a semiconductor integrated circuit device having a stacked structure capacitor, the dielectric film of the stacked structure capacitor is composed of a composite film having a silicon nitride film, and the base insulating film is formed using an inorganic silane gas and a nitrogen oxide gas as a source gas. 1. A semiconductor integrated circuit device comprising a silicon oxide film deposited by a CVD method. 12. The dielectric film of the stacked structure capacitor is CV
12. The semiconductor integrated circuit device according to claim 10, wherein the semiconductor integrated circuit device is formed of a composite film in which a silicon oxide film formed by oxidizing a silicon nitride film deposited by the D method is laminated. 13. First MISFE constituting a memory cell for storage function
T, a second MISFE constituting a peripheral circuit of the memory function;
and a third MIS constituting the output stage circuit of the storage function.
In a semiconductor integrated circuit device having a FET, when the respective channel types are the same and the respective gate length sizes are substantially the same, the first MISFET and the second MISFET
A semiconductor integrated circuit device characterized in that threshold voltages of an SFET and a third MISFET are successively lowered. 14. The semiconductor integrated device according to claim 13, wherein the memory cell is a DRAM memory cell formed by a series circuit of a memory cell selection MISFET, which is the first MISFET, and an information storage capacitive element. circuit device. 15. The third MISFET of the output stage circuit is configured on the main surface of the semiconductor substrate, and the first MISFET of the memory cell
2. Each of the second MISFETs of the peripheral circuit is formed on the main surface of a well region formed with a higher impurity concentration than the main surface of the semiconductor substrate.
The semiconductor integrated circuit device according to claim 3 or claim 14. 16. The first MISFET of the memory cell is surrounded by an isolation insulating film and a channel stopper region, and the threshold voltage of the first MISFET of the memory cell is determined by the lateral diffusion of the channel stopper region. 16. Each of the semiconductor integrated circuit devices according to claim 13, wherein the semiconductor integrated circuit device is increased in height. 17. The semiconductor integrated circuit device according to claim 13, wherein the threshold voltage of the first MISFET of the memory cell is increased by introducing impurities into that region. 18. A memory cell array is constructed in which memory cells are arranged in rows and columns, each consisting of a series circuit of a memory cell selection MISFET and a stacked information storage capacitor laminated on the upper layer. In a semiconductor integrated circuit device having a DRAM in which a circuit is arranged, a conductive layer that is the same as a lower electrode layer, an upper electrode layer, or both layers of the information storage capacitive element of the stacked structure is provided between the memory cell array and the peripheral circuit. What is claimed is: 1. A semiconductor integrated circuit device comprising a step-reducing layer formed of: 19. Between the memory cell array and the peripheral circuit, from the former toward the latter, a first step relief layer is formed of the same conductive layer as the lower electrode layer and the upper electrode layer of the information storage capacitive element of the stacked structure. 19. The semiconductor integrated circuit device according to claim 18, wherein the second step-reducing layer is formed of the same conductive layer as the lower electrode layer or the upper electrode layer. 20. According to claim 18 or 19, a guard ring region is arranged between the memory cell array and the peripheral circuit, and the step relief layer is arranged in the guard ring region. semiconductor integrated circuit devices. 21. The semiconductor integrated circuit device according to claim 20, wherein the width of the guard ring region is substantially the same as the gate width of a memory cell selection MISFET of the memory cell. 22. A plurality of memory cells are arranged at intersections of data lines and word lines to form a memory cell array, and a shunt word line is connected to the word line in an area other than the memory cell array in an upper layer of the word line. What is claimed is: 1. A semiconductor integrated circuit device having a memory function arranged in the semiconductor integrated circuit device, characterized in that a step relief layer is provided around a connection portion between the word line and the shunt word line. 23. The memory cell is a MISFET for memory cell selection.
A DRAM memory cell is a DRAM memory cell configured of a series circuit of a stacked information storage capacitive element layered on the upper layer, and the word line and A step relaxation layer is provided between the shunt word line and the same conductive layer as the lower electrode layer or the upper electrode layer of the information storage capacitive element of the stacked structure. The semiconductor integrated circuit device according to claim 22. 24. A MISFE for memory cell selection is installed at the intersection of the complementary data line extending in the column direction and the word line extending in the row direction.
In a semiconductor integrated circuit device having a DRAM of a folded bit line type in which a memory cell formed by a series circuit of T and an information storage capacitive element is arranged, one of the first data lines of the complementary data lines and a first intersection with a first word line, and a second intersection between the other second data line of the complementary data lines and another second word line adjacent to the first word line in the column direction; The memory cells are arranged, the first word line and the second word line extend in parallel in the row direction with substantially the same width dimension and a predetermined separation dimension, and the first data line , a first word line protruding in opposite directions for each of the second data lines,
Each of the second word lines extends in a zigzag pattern, the second word line side of the first word line at the first intersection protrudes along the shape of the memory cell, and the second word line at the second intersection 1. A semiconductor integrated circuit device, characterized in that a first word line side of the semiconductor integrated circuit device protrudes along the shape of a memory cell. 25. Each of the first word line and its protrusion at the first intersection, and the second word line and its protrusion at the second intersection, are connected to the memory cell selection MISF of the memory cell.
25. The semiconductor integrated circuit device according to claim 24, wherein the semiconductor integrated circuit device is used as a gate electrode of an ET. 26. In a method for forming a semiconductor integrated circuit device in which an aluminum film is patterned by anisotropic etching,
Depositing the aluminum film, forming a photoresist mask on the surface, and performing predetermined patterning on the aluminum film in a vacuum system using anisotropic etching using a halogen element and a halogen compound as an etching gas. a step of removing the photoresist mask by low-temperature ashing below room temperature using a halogen compound and oxygen gas in the same vacuum system as the anisotropic etching step; A method for forming a semiconductor integrated circuit device, comprising the step of performing a baking process on the aluminum film that has been subjected to the predetermined patterning. 27. Claim 26, wherein the baking process is a process of heating while exhausting chlorine generated in the anisotropic etching process with a carrier gas other than oxygen or air.
A method for forming a semiconductor integrated circuit device according to . 28. In a method for forming a semiconductor integrated circuit device by patterning an aluminum film by anisotropic etching,
Depositing the aluminum film, forming a photoresist mask on the surface, and performing predetermined patterning on the aluminum film in a vacuum system using anisotropic etching using a halogen element and a halogen compound as an etching gas. a step of removing the photoresist mask by ashing using a halogen compound and oxygen gas in the same vacuum system as the anisotropic etching step; and shielding chlorine generated in the anisotropic etching process from the atmosphere. 1. A method for forming a semiconductor integrated circuit device, comprising the steps of cleaning in a heated system and then drying. 29. The method for forming a semiconductor integrated circuit device according to claim 26 or 28, wherein after the baking treatment or the drying treatment, a cleaning step mainly using an acid and a drying step are performed in sequence. 30. The method of forming a semiconductor integrated circuit device according to claim 29, wherein each of the anisotropic etching treatment, low-temperature ashing treatment, baking treatment, cleaning treatment, and drying treatment is performed in the same system. 31. The etching apparatus according to claim 26, wherein vacuum chambers for performing each of the anisotropic etching process, the low-temperature ashing process, and the baking process are sequentially arranged in the same apparatus. 32. MISF surrounded by channel stopper region
In a semiconductor integrated circuit device having an ET, the MIS
In the FET, one semiconductor region to which a high voltage is applied is surrounded by the other semiconductor region to which a low voltage is applied with a channel formation region interposed therebetween, and a gate insulating film is interposed over the channel formation region. What is claimed is: 1. A semiconductor integrated circuit device configured by arranging electrodes, wherein the channel stopper region surrounds the other semiconductor region. 33. The semiconductor integrated circuit device according to claim 32, wherein the gate electrode of the MISFET has a ring shape surrounding the one semiconductor region. 34. Claim 34, wherein an outer peripheral end of the upper layer wiring connected to one semiconductor region of the MISFET is arranged on the gate electrode or extended to above the other semiconductor region. 34. The semiconductor integrated circuit device according to claim 32 or 33. 35. A memory cell selection MISFET is placed at the intersection of the complementary data line and the word line, and an information storage capacitive element with a stacked structure in which a lower electrode layer, a dielectric film, and an upper electrode layer are sequentially laminated on top of the MISFET. A semiconductor integrated device having a DRAM, in which memory cells consisting of series circuits are arranged, and column select signal lines extending in the same conductive layer and in the same direction as the complementary data lines are extended for each of the two sets of complementary data lines. The circuit device includes a lower electrode layer of a stacked-structure information storage capacitor element of a memory cell connected to one data line of complementary data lines adjacent to the column select signal line. A semiconductor integrated circuit device characterized by having a larger size than a lower electrode layer of a capacitive element for information storage in a stacked structure of other memory cells. 36. The semiconductor integrated device according to claim 35, wherein the lower electrode layer formed larger than the other lower electrode layers is configured to protrude so as to intersect the column select signal line. circuit device. 37, a memory cell is arranged at the intersection of the complementary data line and the word line, and this memory cell is used as the MI for memory cell selection.
In a semiconductor integrated circuit device having a DRAM, which is configured of a series circuit of an SFET and an information storage capacitor element of a stacked structure in which a lower electrode layer, a dielectric film, and an upper electrode layer are sequentially laminated on top of the SFET, the memory The lower electrode layer of the information storage capacitive element of the stacked structure of the cell is placed between the gate electrode of the memory cell selection MISFET of this memory cell and the word line that selects another memory cell adjacent in the gate width direction. A semiconductor characterized in that the interlayer insulating film between the lower electrode layer and the word line is thicker than the interlayer insulating film between the lower electrode layer and the gate electrode. Integrated circuit device. 38. A semiconductor integrated circuit in which a resin film is applied to the surfaces of a memory cell array arranged on the main surface of the same semiconductor substrate, a direct peripheral circuit that directly controls the information writing operation and information reading operation of the memory cell, and other indirect peripheral circuits. A semiconductor integrated circuit device, characterized in that the resin film is divided into a plurality of parts and applied. 39. The resin film is coated on the respective surfaces of at least the memory cell array and some of the direct peripheral circuits that have a weak α-ray soft error resistance voltage, and is applied to the surfaces of other direct peripheral circuits and indirect peripheral circuits. 39. The semiconductor integrated circuit device according to claim 38, wherein each region is used as a divided region of the resin film. 40. A step of applying a resin film to the entire surface of the semiconductor wafer in which a plurality of semiconductor integrated circuit device formation regions are arranged in rows and columns before the scribing step, and forming each semiconductor integrated circuit device using this resin film. removing the regions between the regions and the external terminals of each semiconductor integrated circuit device, and dividing the resin film on the formation region of each semiconductor integrated circuit device;
40. The semiconductor integrated circuit according to claim 38 or 39, further comprising the step of forming a plurality of semiconductor integrated circuit devices by scribing between formation regions of each semiconductor integrated circuit device on the semiconductor wafer. Method of forming the device. 41. In a method for forming a semiconductor integrated circuit device in which a coated insulating film coated on a base surface is subjected to a baking process, and then a deposited insulating film is deposited on the surface of the coated insulating film, a method for forming a semiconductor integrated circuit device that is shielded from the atmosphere. A step of applying the coated insulating film in a system, a step of baking the coated insulating film, a step of etching back the coated insulating film, and depositing a deposited insulating film on the surface of the coated insulating film. 1. A method for forming a semiconductor integrated circuit device, comprising sequentially performing each of the steps. 42. In the same system shielded from the atmosphere, a coating processing section that applies the coating type insulating film, a baking processing section that performs a baking process on the coated coating type insulating film, and a coating processing section that performs a baking process on the coated coating type insulating film, and Etching processing section that etches a part,
An insulating film forming apparatus characterized in that an insulating film deposition unit is provided for depositing a deposited insulating film on the surface of a coated insulating film that has been subjected to a baking process. 43. A method for forming a semiconductor integrated circuit device in which a film formed on a base surface having a stepped shape is patterned by anisotropic etching, in which the film is alternately subjected to anisotropic etching and isotropic etching. 1. A method for forming a semiconductor integrated circuit device, characterized in that patterning is performed by performing patterning. 44. Each of the anisotropic etching and isotropic etching is performed with an etching gas consisting of a halogen compound and a halogen element, the anisotropic etching is performed with a high proportion of the halogen compound, and the isotropic etching is performed with an etching gas consisting of a halogen compound and a halogen element. 44. The method for forming a semiconductor integrated circuit device according to claim 43, wherein the method is performed by increasing a proportion of the halogen compound or the halogen element. 45. The anisotropic etching is performed again before the organic polymer adhering to the patterned side surface of the film is destroyed by the isotropic etching. A method of forming the semiconductor integrated circuit device described above. 46. An etching chamber for etching the film formed on the semiconductor integrated circuit device is provided, a gas supply system for supplying anisotropic etching gas with a first mass flow controller interposed in the etching chamber, and a second mass flow controller. A chopping control circuit that alternately and repeatedly controls the amount of gas supplied to each of the first mass flow controller and the second mass flow controller is provided. Characteristic anisotropic etching equipment. 47. Using a CVD method in which a semiconductor wafer is held in a reaction chamber, a source gas consisting of inorganic silane gas and nitrogen oxide gas is supplied into the reaction chamber from one end side, and a silicon oxide film is generated on the surface of the semiconductor wafer. In the method for forming a semiconductor integrated circuit device, a source gas is generated by mixing each of an inorganic silane gas and a nitrogen oxide gas at a temperature below the thermal decomposition temperature of the inorganic silane gas, and the source gas is applied to a semiconductor wafer held in the reaction chamber. A method for forming a semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is supplied to the side. 48. In a CVD apparatus that supplies inorganic silane gas and nitrogen oxide gas as source gases into a reaction chamber, the inorganic silane gas as the source gas is mixed with the inorganic silane gas supplied from the gas supply nozzle in the vicinity of the gas supply nozzle. A CVD apparatus characterized in that a gas supply nozzle for nitrogen oxide gas is provided. 49. In a CVD apparatus that supplies inorganic silane gas and nitrogen oxide gas as source gases into a reaction chamber, each of a gas supply pipe for inorganic silane gas and a gas supply pipe for nitrogen oxide gas as source gases is connected to the reaction chamber in the gas supply path. A CVD device characterized by being connected at the front stage of the chamber.