JP3177436B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to semiconductor technology, in particular, DRAM (D ynamic R andom
When applied to a semiconductor integrated circuit device and a forming technique having A ccess M emory) a technique effectively.

[0002]

2. Description of the Related Art A memory cell of a DRAM for holding 1-bit information is composed of a series circuit of a memory cell selection MISFET and an information storage capacitor. The memory cell selection MISFET of the memory cell is formed on the main surface of the active region of the semiconductor substrate (or well region). The active region of the semiconductor substrate is provided in a region defined by an inter-element isolation insulating film (field insulating film) and a channel stopper region formed in the non-active region of the semiconductor substrate. The gate electrode of the memory cell selection MISFET is connected to a word line extending in the row direction.
One semiconductor region of the memory cell selection MISFET is connected to a complementary data line. The other semiconductor region is connected to one electrode of the information storage capacitor.
A predetermined potential is applied to the other electrode of the information storage capacitor.

[0003] DRAMs of this kind are integrated for increasing the capacity, and the size of memory cells tends to be reduced.
When the size of the memory cell is reduced, the size of the information storage capacitor is also reduced, so that the amount of charge stored as information is reduced. A decrease in the amount of charge storage lowers the α-ray soft error withstand voltage. For this reason, especially in a DRAM having a large capacity of 1 [Mbit] or more, improvement of the α-ray soft error withstand voltage is one of the important technical issues.

On the basis of such technical problems, DRAMs
Stacked structure in the information storage capacitance element of the memory cell
(STC structure) tends to be adopted. The information storage capacitor having the stacked structure includes a lower electrode layer, a dielectric film,
Each of the upper electrode layers is sequentially laminated. The lower electrode layer is partially connected to the other semiconductor region of the memory cell selection MISFET, and the other region is extended above the gate electrode. The upper electrode layer is formed on the surface of the lower electrode layer with a dielectric film interposed. The upper electrode layer is formed integrally with the upper electrode layer of the information storage capacitor having a stacked structure of another adjacent memory cell, and is used as a common plate electrode.

A DRAM in which a memory cell is composed of a stacked structure information storage capacitor is described in Japanese Patent Application No. 62-235906, for example.

[0006]

SUMMARY OF THE INVENTION The present inventor has proposed that 16 [Mbi
During the development of a DRAM having a large capacity of [t], the following problems were found.

In the DRAM, the isolation between memory cells is currently performed by using an insulating film for isolation between elements and a channel stopper region. The element isolation insulating film is formed by oxidizing the main surface of the non-active region of the semiconductor substrate using an oxidation-resistant mask (silicon nitride film) formed on the main surface of the active region of the semiconductor substrate. . On the other hand, the channel stopper region
The active region (only the memory cell array) and the non-active region of the semiconductor substrate are formed of impurities, for example, B introduced into the main surface portion. This impurity is introduced by an ion implantation method having a high energy enough to pass through the inter-element isolation insulating film after forming the inter-element isolation insulating film. That is,
Impurities introduced into the main surface of the inactive region of the semiconductor substrate under the inter-element isolation insulating film are formed as the channel stopper region. The impurity introduced into the main surface of the active region of the semiconductor substrate is introduced into a region deeper than the impurity introduced into the main surface of the non-active region, and thus does not adversely affect the memory cell. The method of forming the channel stopper region using the high-energy ion implantation method has a feature that the narrow channel effect of the memory cell selecting MISFET can be reduced. In other words, according to the formation method, the channel stopper region can be formed in a self-alignment manner with the inter-element isolation insulating film. it can.

However, a DRAM being developed by the present inventor
In this case, the capacity is increased to 16 [Mbit], and it is difficult to sufficiently secure the memory cell area and the separation area between the memory cells. That is, the insulating film for element isolation has a lateral oxidation amount.
Since (bird's beak) is large, the area of the insulating film for element isolation increases more than necessary. The increase in the area of the insulating film for element isolation conversely reduces the memory cell area more than necessary.
Therefore, when the thickness of the inter-element isolation insulating film is reduced and the amount of oxidation in the lateral direction is reduced, an impurity for forming a channel stopper region is introduced into a shallow region of the main surface of the active region of the semiconductor substrate. The impurities introduced into the main surface of the active region of the semiconductor substrate increase the impurity concentration on the surface.
The threshold voltage of the memory cell selecting MISFET of the memory cell is changed. For this reason, it is impossible to secure the memory cell area and to reduce the separation area between the memory cells, so that there is a problem that it is not possible to achieve high integration of the DRAM.

The objects of the present invention are as follows.

(1) An object of the present invention is to provide a technique capable of improving the degree of integration in a semiconductor integrated circuit device having a storage function.

(2) In the semiconductor integrated circuit device,
An object of the present invention is to provide a technology capable of improving electrical reliability.

(3) In the semiconductor integrated circuit device,
It is an object of the present invention to provide a technique capable of improving a soft error withstand voltage.

(4) In the semiconductor integrated circuit device,
It is to provide a technique capable of reducing the number of manufacturing steps.

(5) In the semiconductor integrated circuit device,
It is an object of the present invention to provide a technique capable of improving processing accuracy in manufacturing.

(6) In the semiconductor integrated circuit device,
It is an object of the present invention to provide a technique capable of improving the driving capability of a semiconductor element.

(7) In the semiconductor integrated circuit device,
It is an object of the present invention to provide a technology capable of improving the production yield.

(8) In the semiconductor integrated circuit device,
It is an object of the present invention to provide a technique capable of increasing the operation speed.

(9) In the semiconductor integrated circuit device,
An object of the present invention is to provide a technique capable of preventing a disconnection failure of a wiring.

(10) It is an object of the present invention to provide a technique capable of improving moisture resistance in the semiconductor integrated circuit device.

(11) In a semiconductor integrated circuit device having a redundant fuse element, it is an object of the present invention to provide a technique capable of simplifying a step of forming the redundant fuse element.

(12) An object of the present invention is to provide a technique capable of improving the film quality of a film used for the semiconductor integrated circuit device.

(13) An object of the present invention is to provide the manufacturing apparatus of the above (12).

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0024]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A plurality of aluminum wirings which are regularly arranged on a semiconductor substrate at predetermined intervals and have a predetermined thickness, and the aluminum is formed by a CVD method using tetraethoxysilane as a source gas. In a semiconductor integrated circuit device having a first insulating film formed on a wiring and a second insulating film formed on the first insulating film by a plasma CVD method, the first insulating film is formed of the aluminum wiring. A semiconductor integrated circuit device having a film thickness of one half or more of an interval.

(2) Further, the second insulating film is a nitride film.

(3) Further, the film thickness of the aluminum wiring is larger than the interval between the wirings.

(4) Further, a memory cell selecting MISFET formed on the semiconductor substrate, and an information storage capacitor connected in series with the memory cell selecting MISFET and formed on the memory cell selecting MISFET. A plurality of first word lines electrically connected to the element and the memory cell selecting MISFET and arranged at predetermined intervals on the semiconductor substrate; and an insulating film on the first word line. A plurality of second word lines regularly arranged at predetermined intervals, extending in the same direction as the first word lines, and electrically connected to the first word lines; Is the second word line.

(Operation) According to the above-described means, the silicon oxide film under the passivation film can be deposited at a low temperature at which the wiring is not melted and at a high step coverage, and is formed by the wiring layer. Since the step shape can be flattened, a silicon nitride film having excellent moisture resistance on the passivation film can be formed without forming a nest based on the step shape. As a result, no cavities are generated in the silicon nitride film above the passivation film, so that cracks in the silicon nitride film and moisture do not accumulate in the cavities, thereby improving the moisture resistance of the passivation film. it can.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a DRAM in which a memory cell is formed by a series circuit of a memory cell selecting MISFET and a stacked information storage capacitor.

In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals and their repeated explanation is omitted.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) DRAM according to Embodiment 1 of the present invention
Is shown in FIG. 2 (partial cross-sectional perspective view).

As shown in FIG. 2, DRAM (semiconductor pellet) 1 is sealed with SOJ (S mall O ut-line J-bend) type resin-encapsulated semiconductor device 2. DRAM 1
Is configured with a large capacity of 16 [Mbit] × 1 [bit].
It is configured in a plane rectangular shape of 48 [mm] × 8.54 [mm]. The DRAM 1 is sealed in a resin-sealed semiconductor device 2 of 400 [mil].

The main surface of the DRAM 1 is mainly provided with a memory cell array and peripheral circuits. As will be described in detail later, the memory cell array has a plurality of memory cells (storage elements) for storing 1-bit information arranged in a matrix. The peripheral circuit includes a direct peripheral circuit and an indirect peripheral circuit.
The direct peripheral circuit is a circuit that directly controls the information writing operation and the information reading operation of the memory cell. Direct peripheral circuits are row address decoder circuits, column address decoder circuits,
It includes a sense amplifier circuit and the like. The indirect peripheral circuit is a circuit that indirectly controls the operation of the direct peripheral circuit. The indirect peripheral circuit includes a clock signal generation circuit, a buffer circuit, and the like.

An inner lead 3A is arranged on the main surface of the DRAM 1, that is, on the surface on which the memory cell array and the peripheral circuits are arranged. An insulating film 4 is interposed between the DRAM 1 and the inner lead 3A. The insulating film 4 is formed of, for example, a polyimide resin film. An adhesive layer (not shown) is provided on each surface of the insulating film 4 on the DRAM 1 side and the inner lead 3A side. As the adhesive layer, for example, a polyetheramideimide resin or an epoxy resin is used. Resin-sealed semiconductor device 2 of this type employs a LOC (L ead O n C hip ) structure in which the inner leads 3A on DRAM 1. In the resin-encapsulated semiconductor device 2 employing the LOC structure, the inner leads 3A can be freely routed without being restricted by the shape of the DRAM 1, so that the DRAM 1 having a large size can be sealed by an amount corresponding to the routing. . In other words, in the resin-sealed semiconductor device 2 employing the LOC structure, even if the size of the DRAM 1 is increased due to the increase in capacity, the sealing size can be kept small, so that the mounting density can be increased.

The inner lead 3A has one end integrally formed with the outer lead 3B. Signals to be applied to the outer leads 3B are defined and numbered based on the standard. In FIG. 2, the terminal on the left side is terminal No. 1, and the terminal on the right side is terminal No. 14. The right back side (the terminal number is shown on the inner lead 3A) is the 15th terminal, and the left back side is the 28th terminal. That is, the resin-sealed semiconductor device 2 has terminals 1 to 6, terminals 9 to 14, and 15 to 2.
It is composed of a total of 24 terminals, the 0th terminal and the 23rd to 28th terminals.

The first terminal is a power supply voltage Vcc terminal.
The power supply voltage Vcc is, for example, an operation voltage 5 [V] of the circuit. Terminal 2 is a data input signal terminal (D), terminal 3 is an empty terminal, terminal 4 is a write enable signal terminal (W), 5
The terminal No. is a row address strobe signal terminal (RE), and the terminal No. 6 is an address signal terminal (A ₁₁ ).

No. 9 terminals are address signal terminals (A ₁₀ ), 10
Terminal No. is an address signal terminal (A ₀ ), Terminal No. 11 is an address signal terminal (A ₁ ), Terminal No. 12 is an address signal terminal
(A ₂ ), the thirteenth terminal is an address signal terminal (A ₃ ). 1
The fourth terminal is a power supply voltage Vcc terminal.

The 15th terminal is a reference voltage Vss terminal. The reference voltage Vss is, for example, a reference voltage 0 [V] of the circuit.
Terminal 16 is an address signal terminal (A ₄ ), terminal 17 is an address signal terminal (A ₅ ), and terminal 18 is an address signal terminal.
(A ₆ ), the 19th terminal is an address signal terminal (A ₇ ), and the 20th terminal is an address signal terminal (A ₈ ).

Terminal 23 is an address signal terminal (A ₉ ), 2
The fourth terminal is an empty terminal, the 25th terminal is a column address strobe signal terminal (CE), the 26th terminal is an empty terminal, and the 27th terminal is a data output signal terminal. The 28th terminal is a reference voltage Vss terminal.

The other end of the inner lead 3A is connected to the DR
It extends across each long side of the rectangular shape of AM1 and extends to the center side of DRAM1. The other end of the inner lead 3A is connected to the DRA with the bonding wire 5 interposed.
It is connected to external terminals (bonding pads) BP arranged at the center of M1. The bonding wire 5 uses an aluminum (Al) wire. Further, as the bonding wire 5, a gold (Au) wire, a copper (Cu) wire, a coated wire in which a surface of a metal wire is coated with an insulating resin, or the like may be used. The bonding wire 5 is bonded by a bonding method using ultrasonic vibration in combination with thermocompression bonding.

No. 1 terminal of the inner lead 3A,
The respective inner leads (Vcc) 3A of the 14th terminal are integrally formed, and a central portion of the DRAM 1 is extended in parallel with its long side. Similarly, the inner leads (Vss) 3A of the 15th terminal and the 28th terminal are integrally formed, and the central portion of the DRAM 1 is extended in parallel with its long side. Each of the inner lead (Vcc) 3A and the inner lead (Vss) 3A is other inner lead 3A.
Are extended in parallel within a region defined by the tip on the other end side. Each of the inner lead (Vcc) 3A and the inner lead (Vss) 3A is configured to supply the power supply voltage Vcc and the reference voltage Vss at any position on the main surface of the DRAM 1. That is, the resin-encapsulated semiconductor device 2 is configured to easily absorb power supply noise,
The configuration is such that the operation speed of the DRAM 1 can be increased.

The rectangular short side of the DRAM 1 is provided with a pellet supporting lead 3C.

Each of the inner lead 3A, outer lead 3B, and pellet supporting lead 3C is cut and molded from a lead frame. The lead frame is made of, for example, Fe—Ni (for example, Ni content 42 or 50).
[%]) It is formed of an alloy, Cu, or the like.

The DRAM 1, the bonding wire 5,
The inner leads 3A and the pellet supporting leads 3C are sealed with a resin sealing portion 6. The resin sealing portion 6 uses an epoxy resin to which a phenolic curing agent, silicone rubber, and a filler are added in order to reduce stress. Silicone rubber has the effect of lowering the coefficient of thermal expansion of the epoxy resin. The filler is formed of spherical silicon oxide particles, and similarly has the effect of reducing the coefficient of thermal expansion.

Next, the schematic configuration of the DRAM 1 sealed in the resin-sealed semiconductor device 2 is shown in FIG. 3 (chip layout diagram).

As shown in FIG. 3, a memory cell array (MA) 11 is arranged over substantially the entire surface of the DRAM 1.
Although the DRAM 1 of the present embodiment is not limited to this,
The memory cell array 11 is roughly divided into four memory cell arrays 11A to 11D. In FIG.
1, two memory cell arrays 11A and 11B are arranged above, and two memory cell arrays 11C and 11B are arranged below.
1D is arranged. Each of the four divided memory cell arrays 11A to 11D is further subdivided into 16 memory cell arrays (MA) 11E. That is,
The DRAM 1 arranges 64 memory cell arrays 11E. One memory cell array 11E divided into 64 pieces has a capacity of 256 [Kbit].

A sense amplifier circuit (SA) 13 is arranged between two memory cell arrays 11E of the DRAM 1 divided into 64 pieces. The sense amplifier circuit 13 is configured by a complementary MISFET (CMOS). A column address decoder circuit (YDEC) 12 is disposed at one lower end of each of the four memory cell arrays 11A and 11B of the DRAM 1.
Similarly, a column address decoder circuit (YDEC) 12 is provided at one upper end of each of the memory cell arrays 11C and 11D.
Is arranged.

The memory cell arrays 11A and 11C, which are divided into four parts of the DRAM 1, have a word driver circuit (WD) 14, a row address decoder circuit (XDEC) 15, and a unit mat control circuit 16 at one right end. Each is sequentially arranged from left to right. Similarly,
At one end on the left side of each of the memory cell arrays 11B and 11D, a word driver circuit 14, a row address decoder circuit 15, and a unit mat control circuit 16 are sequentially arranged from right to left.

Each of the sense amplifier circuit 13, column address decoder circuit 12, word driver circuit 14, and row address decoder circuit 15 constitutes a direct peripheral circuit among the peripheral circuits of the DRAM 1. This direct peripheral circuit is a circuit for directly controlling the memory cells arranged in the memory cell array 11E obtained by dividing the memory cell array 11.

A peripheral circuit 17 and an external terminal BP are respectively disposed between the memory cell arrays 11A and 11B and between the memory cell arrays 11C and 11D of the DRAM 1 divided into four. Peripheral circuit 17
Amplifier circuit 1701, output buffer circuit 1702, substrate potential generation circuit (Vss generator circuit)
1703 and a power supply circuit 1704 are arranged. A total of 16 main amplifier circuits 1701 are arranged in units of 4. A total of four output buffer circuits 1702 are arranged.

The external terminals BP are formed by forming the resin-encapsulated semiconductor device 2 in a LOC structure and extending the inner leads 3A to the center of the DRAM 1.
1 is located at the center. The external terminal BP is arranged from the upper end side to the lower end side of the DRAM 1 in a region defined by each of the memory cell arrays 11A and 11C, 11B and 11D. Since the signal applied to the external terminal BP has been described in the resin-encapsulated semiconductor device 2 shown in FIG. 2 described above, the description is omitted here. Basically, the inner lead 3A to which the reference voltage (Vss) and the power supply voltage (Vcc) are applied extends from the upper end side to the lower end side on the surface of the DRAM 1, so that the DRAM 1 extends in the extending direction. A plurality of external terminals BP for the reference voltage (Vss) and the power supply voltage (Vcc) are arranged along the line. That is, DRA
M1 is configured to sufficiently supply the respective powers of the reference voltage (Vss) and the power supply voltage (Vcc). Data input signal (D), data output signal (Q), address signal (A ₀ -A
₁₁ ), each of the clock system signal and the control signal is intensively arranged in the central portion of the DRAM 1.

Each of the memory cell arrays 11A and 11C of the DRAM 1 divided into four parts, 11B,
A peripheral circuit 18 is arranged between each of the 11Ds. On the left side of the peripheral circuit 18, a row address strobe (RE) circuit 1801, a write enable (W) circuit 1802, a data input buffer circuit 1803, a VCC limiter circuit 1804, an X address driver circuit (logic stage) 1805, X A system redundancy circuit 1806 and an X address buffer circuit 1807 are arranged. Peripheral circuit 1
8, a column address strobe (CE) circuit 1808, a test circuit 1809, a VDL limiter circuit 1810, a Y address driver circuit (logical stage) 181
1, Y-system redundant circuit 1812, Y address buffer circuit 1
813 are arranged. In the center of the peripheral circuit 18, a Y address driver circuit (drive stage) 1814,
An X address driver circuit (drive stage) 1815 and a mat selection signal circuit (drive stage) 1816 are arranged.

The peripheral circuits 17 and 18 (including 16)
It is used as an indirect peripheral circuit of the RAM 1.

Next, the main part of the memory cell array 11E divided into 16 parts of the DRAM 1 and the main part of its peripheral circuits will be described with reference to FIG. 4 (equivalent part schematic diagram).

As shown in FIG. 4, the DRAM 1 is constructed by a folded bit line system (a folded bit line system or a two-intersection system). A plurality of memory cells M are arranged in rows and columns in each of the 16 memory cell arrays 11E of the DRAM 1. Memory cell M
Are arranged at intersections between complementary data lines (complementary bit lines) DL, DL and word lines WL. The plurality of complementary data lines DL extend in the row direction in FIG. 4 and are arranged in a plurality in the column direction. The word lines WL extend in the column direction, and a plurality of word lines WL are arranged in the row direction. Shared sense type sense amplifier circuit Sa, precharge circuit DP, input / output signal selection circuit V are provided to complementary data lines DL extending in the row direction.
Each of O is connected. The word line WL is connected to a row address decoder circuit (XDEC) 15 via the word driver circuit (WD) 14 shown in FIG. Although not shown in FIG. 4, the word line WL
A shunt word line WL extending in the column direction is arranged at a position along. The shunt word line WL is short-circuited with the word line WL in a predetermined portion (for example, for each predetermined number of memory cells), and is configured to reduce the specific resistance of the word line WL.

The memory cell M is a memory cell selecting MI.
It is composed of a series circuit of SFET Qs and information storage capacitor C. MISFET Qs for memory cell selection is n
Consists of channels. MISF for memory cell selection
One semiconductor region of the ETQs is the complementary data line DL.
It is connected to the. The other semiconductor region is connected to one electrode (lower electrode layer) of the information storage capacitor C. The gate electrode is connected to the word line WL. The other electrode of the information storage capacitor C is connected to a low power supply voltage of 1/2 Vcc. The DRAM 1 uses the above-described power supply voltage Vcc, that is, 5 [V] as the operating voltage of the input stage circuit and the output stage circuit used as an interface with an external device. Internal circuit of DRAM 1, ie, memory cell array 1
1. The operating voltage of the direct peripheral circuits (12, 13, 14, 15) and the indirect peripheral circuits (16, 17, 18)
A low power supply voltage Vcc lower than cc, for example, 3.3 [V] is used. The low power supply voltage Vcc can reduce the amount of charge / discharge of the complementary data line DL particularly during the information writing operation and the information reading operation of the DRAM 1, so that the DRAM
1 can be reduced. Therefore, the low power supply voltage 1/2 Vcc is equal to the low power supply voltage Vcc and the reference voltage Vcc.
It is about 1.65 [V], which is an intermediate potential with ss.

The precharge circuit DP includes two precharge MISFETs each having a gate electrode connected to a precharge signal line φpc, and similarly a precharge signal line φ.
One short-circuit MISFET with gate electrode connected to pc
It is composed of The precharge MISFET has one semiconductor region connected to the complementary data line DL and the other semiconductor region connected to a common source line (reference voltage Vss) PN. Each semiconductor region of the short-circuit MISFET is connected to each of the complementary data lines DL. Each of the precharge MISFET and the short-circuit MISFET has an n-channel.

The sense amplifier circuit Sa includes two n-channel MISFETs Qn and two p-channel MISFETs Qn.
p. One semiconductor region of each of the n-channel MISFETs Qn of the sense amplifier circuit Sa is connected to a complementary data line DL, and the other semiconductor region is connected to a common source line (reference potential Vss) PN.
Each gate electrode of the n-channel MISFET Qn is connected to the other data line different from one data line of the complementary data line DL to which one semiconductor region is connected and crosses each other. P channel MISF of sense amplifier circuit Sa
One semiconductor region of each of the ETQp is a complementary data line D
L, and each other semiconductor region is connected to a common source line (Vcc: 3.3 [V]) PP. The respective gate electrodes of the p-channel MISFETs Qp similarly cross each other and have complementary data lines DL connected to one semiconductor region.
Is connected to the other data line different from the other data line.

The input / output signal selection circuit VO is composed of an input / output selection MISFET (column switch) formed of n channels. The input / output selection MISFET is arranged for each data line of the complementary data lines DL. The input / output selection MISFET has one semiconductor region connected to the complementary data line DL and the other semiconductor region connected to one of the complementary input / output signal lines I / O. M for input / output selection
A column select signal line YS is connected to the gate electrode of the ISFET.
L is connected. The column select signal line YSL is connected to the column address decoder circuit 12.

In the sense amplifier circuit 13, the complementary data line DL of the lower memory cell array 11E and the input / output signal selection circuit VO are connected between the complementary data line DL of the upper memory cell array 11E and the sense amplifier circuit Sa. Are provided with a mat selection MISFET. This mat selection MISFET is composed of n channels,
It is configured to be controlled by each of the mat selection signals SHL and SHR.

In the vicinity of the sense amplifier circuit 13, a dummy cell DS is arranged in the memory cell array 11E at the intersection of the complementary data line DL and the dummy word line DWL. This dummy cell DS is an n-channel MIS
It is composed of an FET.

A clear MISFET is arranged on the side of the memory cell array 11E opposite to the side connected to the word driver circuit 14 of the word line WL. This clear MISFET is controlled by a clear signal WLC.

Next, the specific structure of the elements forming the memory cell M and the peripheral circuits (sense amplifier circuit, decoder circuit, etc.) of the DRAM 1 will be described. The plan structure of the memory cell array 11E is shown in FIG. A cross-sectional structure of the memory cell array 11E and a cross-sectional structure of a peripheral circuit element are shown in FIG. Note that the cross-sectional structure of the memory cell M shown on the left side of FIG. 1 shows a cross-sectional structure of a portion taken along the line II in FIG. 1 is a complementary MISFET (CMOS) constituting a peripheral circuit.
2 shows the cross-sectional structure of the device.

As shown in FIGS. 1 and 5, the DRAM 1 is formed of a p-type semiconductor substrate 20 made of single crystal silicon. The p − type semiconductor substrate 20 is formed with a resistance value of, for example, about 10 [Ω / cm] using a (100) crystal plane as an element formation surface. Part of the main surface of the p − type semiconductor substrate 20 has not been doped with n-type impurities of about 10 ¹⁵ [atoms / cm ² ] or more by ion implantation. The partial region is at least a region of the memory cell array 11E. The introduction of the n-type impurity causes a large amount of crystal defects and leaks electric charges serving as information, so that the region for introducing the impurity is partially limited. Therefore, in order to reduce contamination by heavy metals such as Fe,
The RAM 1 has a gettering layer in a deep region of the semiconductor substrate 20.

The memory cell M of the p− type semiconductor substrate 20
(Memory cell array 11E), n-channel MISFET
The p-type well region 2 is formed on the main surface of each formation region of Qn.
2 are provided. Also, the p-type semiconductor substrate 20
The main surface of the formation region of the channel MISFET Qp has n-
A mold well region 21 is provided. That is, the DRAM 1 of the present embodiment has a twin-well structure. As will be described in a manufacturing method described later, the p-type well region 22 is formed in a self-alignment with the n-type well region 21.

An insulating film for field isolation (field insulating film) 23 is provided on the main surface (inactive region) between the semiconductor element forming regions of the well regions 21 and 22. A p-type channel stopper region 25A is provided below the element isolation insulating film 23 (inactive region) in the main surface of the region where the memory cell array 11E is formed in the p-type well region 22. Since the parasitic MOS having the element isolation insulating film 23 as the gate insulating film is easily inverted to the n-type, the channel stopper region is provided at least on the main surface of the p − -type well region 22. The p-type channel stopper region 25A is p-
It has a higher impurity concentration than each of the semiconductor substrate 20 and the p − well region 22.

In the formation region of the memory cell M of the memory cell array 11E, a p-type semiconductor region 25B is provided on the main surface of the p − -type well region 22. The p-type semiconductor region 25B is provided substantially over the entire active region of the memory cell array 11E. The p-type semiconductor region 25B is formed in the same manufacturing process as the p-type channel stopper region 25A. Although the p-type semiconductor region 25B and the p-type channel stopper region 25A will be described later in detail, after forming the element isolation insulating film 23, the active region and the inactive region of the memory cell array 11E in the p − -type well region 22 are formed. It is formed by introducing an impurity into each main surface and activating the impurity. For example, B is used as an impurity, and the impurity is introduced by a high energy ion implantation method. An impurity is introduced into the main surface portion of the non-active region of the p − -type well region 22 through the element isolation insulating film 23. The impurity is introduced into the main surface portion of the active region (the region where the memory cell M is formed) of the p − -type well region 22 by a depth corresponding to the thickness of the inter-element isolation insulating film 23 from the main surface. are doing.

The p-type channel stopper region 25A thus configured is formed in self-alignment with the inter-element isolation insulating film 23, and after a heat treatment for forming the inter-element isolation insulating film 23, which will be described later. Because it is formed,
The amount of diffusion of the p-type impurity forming the type channel stopper region 25A toward the active region can be reduced. This p
The reduction in the diffusion amount of the type impurity can reduce the narrow channel effect of the memory cell selecting MISFET Qs of the memory cell M. Further, since the p-type semiconductor region 25B is formed below the memory cell M and acts as a potential barrier region for minority carriers, the α-ray soft error withstand voltage can be increased. Further, the p-type semiconductor region 2
5B can slightly increase the impurity concentration on the main surface of the p − -type well region 22 and increase the threshold voltage of the memory cell selecting MISFET Qs, so that noise is generated in the unselected word lines WL and the like. No erroneous conduction occurs.
The p-type semiconductor region 25B is provided with a memory cell selecting MI.
Since the pn junction capacitance formed in the semiconductor region (29) on the side connected to the electrode of the information storage capacitor C of the SFET Qs can be increased, the charge storage amount of the information storage capacitor C can be increased. it can.

The memory cell selecting MI of the memory cell M
The SFET Qs has a p-type well region 22 as shown in FIG. 1, FIG. 5 and FIG.
Of the main surface. Actually, the memory cell selection MISFET Qs is formed on the main surface of the p − -type well region 22 which is covered with the p-type semiconductor region 25B and has a slightly higher impurity concentration. The memory cell selection MISFET Qs is formed in a region defined by the element isolation insulating film 23 and the p-type channel stopper region 25A. The memory cell selection MISFET Qs mainly includes a p − -type well region 22, a gate insulating film 26, a gate electrode 27, and a pair of n-type semiconductor regions 29 which are a source region and a drain region.

The p-type well region 22 is used as a channel forming region. Gate insulating film 26 is formed of a silicon oxide film formed by oxidizing the main surface of p − -type well region 22. In the case where the withstand voltage is secured as the gate insulating film 26 becomes thinner, the gate insulating film 26 may be formed of a composite film in which a silicon oxide film and a silicon nitride film are sequentially stacked.

The gate electrode 27 is provided on the gate insulating film 26. The gate electrode 27 is formed, for example, by CVD.
Formed of a polycrystalline silicon film deposited by
It is formed with a thickness of about [nm]. This polycrystalline silicon film introduces an n-type impurity (P or As) for reducing the resistance value. The gate electrode 27 is composed of a single layer of a transition metal (high melting point metal Mo, Ti, Ta, W) film or a transition metal silicide (high melting point metal silicide MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film. You may. Further, the gate electrode 27 may be formed of a composite film in which the transition metal film or the transition metal silicide film is stacked on a polycrystalline silicon film.

As shown in FIGS. 5 and 6, the gate electrode 27 is formed integrally with a word line (WL) 27 extending in the column direction. That is, the gate electrode 27, the word line 27
Are formed of the same conductive layer. The word line 27 is configured to connect the respective gate electrodes 27 of the memory cell selecting MISFETs Qs of the plurality of memory cells M arranged in the column direction.

As shown in FIG. 6, a memory cell selecting MI
The gate length of the gate electrode 27 of the SFET Qs is longer than the width of the word line 27. For example,
The gate electrode 27 has a gate length of 0.7 [μm] and the word line 27 has a width of 0.5 [μm]. In other words, the memory cell selection MISFET Qs is configured to secure an effective gate length (effective channel length) dimension and reduce the short channel effect. On the other hand, the word lines 27 are configured to minimize the interval between the word lines 27, reduce the area of the memory cells M, and improve the degree of integration. As will be described later, since the resistance value of the word line 27 is reduced by the shunt word line (WL) 55,
Even if the width is reduced, the operation speed of each of the information writing operation and the information reading operation does not decrease. In this embodiment, the DRAM 1 employs a so-called 0.5 [μm] manufacturing process in which the minimum processing dimension is 0.5 [μm].

The n-type semiconductor region 29 is formed with a lower impurity concentration than the n + -type semiconductor region (32) of the MISFET Qn constituting the peripheral circuit. Specifically, the n-type semiconductor region 29 is formed by ion implantation with a low impurity concentration of less than 1 × 10 ¹⁴ [atoms / cm ² ]. That is, the n-type semiconductor region 29 is formed so as to reduce the occurrence of crystal defects due to the introduction of the impurity and to sufficiently recover the crystal defect by heat treatment after the introduction of the impurity. Therefore, the n-type semiconductor region 29 is
2 has a small amount of leakage current at the pn junction,
The charge serving as information stored in the information storage capacitive element C can be stably held.

The n-type semiconductor region 29 has a gate electrode 2
7 is formed in a self-aligned manner, and the channel forming region side is
Because of the low impurity concentration, LDD (Lightly
DopedDMISFETQ for memory cell selection with rain) structure
s.

The MISFET for selecting a memory cell
The n-type semiconductor region 29 on one side of Qs (on the side to which the complementary data line 50 is connected) is a polycrystalline silicon film under the complementary data line (50) in a region defined by a connection hole (40A) described later. The n-type impurity introduced into (50A) is diffused, so that the impurity concentration is slightly higher. This n-type semiconductor region 2
The n-type impurity introduced into 9 can ohmic-connect each of the n-type semiconductor region 29 and the complementary data line (50), so that the resistance of the connection portion can be reduced. Further, the n-type impurity causes a mask misalignment in a manufacturing process between the n-type semiconductor region 29 and the connection hole (40A), and the connection hole (40A) is polymerized on the element isolation insulating film 23. , P-type well region 2 in connection hole (40A)
2, the complementary data line
In order not to short-circuit (50) and p-type well region 22, n
A type semiconductor region is formed.

The memory cell selecting MISFET Qs
The n-type semiconductor region 29 on the other side (on the connection side of the information storage capacitive element C) is located within the region defined by the connection hole (34).
The n-type impurity introduced into the lower electrode layer (35) of the information storage capacitive element C described later is diffused, and is formed with a slightly higher impurity concentration. The n-type impurity introduced into the n-type semiconductor region 29 is the n-type semiconductor region 29 and the lower electrode layer (35).
Can be ohmic-connected, so that the resistance value of the connection portion can be reduced. Further, the n-type impurity can increase the impurity concentration of the n-type semiconductor region 29 and increase the pn junction capacitance formed by the n-type semiconductor region 29 and the p − -type well region 22. The amount of charge stored in the capacitor C can be increased.

An insulating film 28 is provided on the gate electrode 27 of the memory cell selecting MISFET Qs, and a sidewall spacer 31 is provided on each side wall of the gate electrode 27 and the insulating film 28. The insulating film 28 is configured to mainly electrically isolate the gate electrode 27 and each of the electrodes (especially 35) of the information storage capacitor C formed thereon. The side wall spacer 31 is provided in the memory cell M formation region in the memory cell selection MIS.
It is formed so as to be connected to the other n-type semiconductor region 29 and the lower electrode layer 35 of the information storage capacitor C in a self-aligned manner with respect to the gate electrode 27 of the FET Qs. Further, the sidewall spacer 31 is configured to make the CMOS have the LDD structure in the formation region of the peripheral circuit. The insulating film 28, the sidewall spacer 3
In each of the methods (1) and (2), the production method will be described later, but CVD using inorganic silane gas and nitrogen oxide gas as source gases
It is formed of a silicon oxide film deposited by a method. This silicon oxide film has higher step coverage at the step portion of the base and less shrinkage of the film than a silicon oxide film deposited by a CVD method using an organic silane gas as a source gas. In other words, the insulating film 28 and the sidewall spacers 31 formed by this method can reduce the separation between the two due to the shrinkage of the film, so that the gate electrode 27 and the other conductive layer such as the lower electrode layer 35 can be prevented.

The information storage capacitor C of the memory cell M
As shown in FIG. 1, FIG. 5, and FIG. 7 (a plan view of a main part in a predetermined manufacturing process), mainly, a lower electrode layer 35, a dielectric film 36, and an upper electrode layer 37 are sequentially laminated. It is configured. The information storage capacitive element C has a so-called stacked structure
(Stacked type: STC).

A part (central part) of the lower electrode layer 35 of the information storage capacitor C having the stacked structure is connected to the other n-type semiconductor region 29 of the memory cell selection MISFET Qs. This connection is made through a connection hole 33A formed in the interlayer insulating film 33 and a connection hole 34 defined by the sidewall spacers 31 and 33B. The size of the opening in the row direction of the connection hole 34 is the MI for the memory cell selection.
Separation dimensions of the gate electrode 27 of the SFET Qs and the word line 27 adjacent thereto and the side wall spacer 3
It is defined by the respective film thicknesses of 1, 33B. Connection hole 33
The difference between the opening size of A and the opening size of the connection hole 34 is larger than at least the portion corresponding to the mask alignment margin in the manufacturing process. The other part (peripheral part) of the lower electrode layer 35 is extended to the upper part of each of the gate electrode 27 and the word line 27.

The interlayer insulating film 33 is an underlying insulating film 2
8. Each of the side wall spacers 31 is formed of the same insulating film. That is, it is formed of a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas.

The lower electrode layer 35 is formed of, for example, a polycrystalline silicon film deposited by a CVD method, and an n-type impurity (As or P) for reducing the resistance value is introduced into this polycrystalline silicon film at a high concentration. ing. The lower electrode layer 35 is configured to increase the area of the side wall of the surface thereof to increase the amount of charge stored in the information storage capacitor C having the stacked structure. The lower electrode layer 35 is formed so as to have a thickness equal to or larger than half the opening size of the connection hole 34 in the gate length direction so that the surface is flattened. For example,
The lower electrode layer 35 is formed with a relatively large thickness of about 400 to 600 [nm]. The planar shape of the lower electrode layer 35 is, as shown in FIG. 5 and FIG.
0) is formed in a rectangular shape long in the row direction.

The dielectric film 36 is basically a silicon nitride film 36A deposited on the upper layer (on the surface) of the lower electrode layer (polycrystalline silicon film) 35 by the CVD method, and the silicon nitride film 36A is oxidized at a high pressure. It has a two-layer structure in which the formed silicon oxide films 36B are stacked. Actually, the dielectric film 36 is formed on the lower electrode layer 3.
The natural silicon oxide film (5 [n]
m], which is a very thin film thickness (not shown), so that it has a three-layer structure in which a natural silicon oxide film, a silicon nitride film 36A, and a silicon oxide film 36B are sequentially laminated. The silicon nitride film 36A of the dielectric film 36 is formed by CVD.
Since it is deposited by the method, it can be formed under independent process conditions for the base without being affected by the crystal state or the step shape of the base polycrystalline silicon film (lower electrode layer 35). That is, the silicon nitride film 36A has a higher dielectric breakdown voltage and a smaller number of defects per unit area than the silicon oxide film formed by oxidizing the surface of the polycrystalline silicon film, so that the leakage current is very small. In addition, the silicon nitride film 36A has a feature that the dielectric constant is higher than that of the silicon oxide film. Since the silicon oxide film 36B can be formed of a very high quality film, the characteristics of the silicon nitride film 36A can be further improved. As described later in detail, the silicon oxide film 36B is formed by high-pressure oxidation.
(1.5 to 10 [toll]), it can be formed in a shorter oxidation time, that is, a heat treatment time as compared with normal pressure oxidation.

The dielectric film 36 is provided along the upper surface and the side wall of the lower electrode layer 35, and uses the side wall portion of the lower electrode layer 35 to increase the area in the height direction. The increase in the area of the dielectric film 36 can improve the charge storage amount of the information storage capacitor C having the stacked structure. The planar shape of the dielectric film 36 is defined by the planar shape of the upper electrode layer 37, and is substantially the same as the upper electrode layer 37.

The upper electrode layer 37 is provided above the lower electrode layer 35 with the dielectric film 36 interposed therebetween so as to cover the lower electrode layer 35. The upper electrode layer 37 is an upper electrode layer 3 of an information storage capacitor C having a stacked structure of another adjacent memory cell M.
7 is formed integrally. A low power supply voltage of 1/2 Vcc is applied to the upper electrode layer 37. The upper electrode layer 37 is formed of, for example, a polycrystalline silicon film deposited by a CVD method, and an n-type impurity for reducing a resistance value is introduced into the polycrystalline silicon film. The upper electrode layer 37 is, for example, the lower electrode layer 35.
It is formed with a thin film thickness as compared with. The upper electrode layer 3
An insulating film 38 is provided on the surface of 7. Insulating film 38
As will be described later, it is formed when removing the etching residue remaining on the step portion of the base surface when the upper electrode layer 37 is processed.

The dielectric film 36 of the information storage capacitor C having the stacked structure is formed on the interlayer insulating film 33 in a region other than the lower electrode layer 35. Interlayer insulating film 3
Reference numeral 3 denotes a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas as described above. That is, the silicon nitride film 36A, which is the lower layer of the dielectric film 36, in particular, is less likely to shrink.
3, the information storage capacitance element C having the stacked structure is configured to prevent the dielectric film 36 from being broken due to stress.

As shown in FIGS. 1, 5, 6, and 7, the memory cell M is connected to another memory cell M adjacent in the row direction. In other words, the two memory cells M adjacent in the row direction are the respective memory cell selecting MISFEs.
One n-type semiconductor region 29 of TQs is integrally formed, and is formed in an inverted pattern centering on that portion. This 2
The plurality of memory cells M are arranged in the column direction, and the two memory cells M and the other two memory cells M adjacent in the column direction are arranged with a shift of a half pitch in the row direction. .

MISF for selecting memory cell of memory cell M
One of the n-type semiconductor regions 29 of ETQs is shown in FIGS.
As shown in the figure, a complementary data line (DL) 50 is connected. Complementary data line 50 is connected to n-type semiconductor region 29 through connection holes 40A formed in interlayer insulating films 33 and 40, respectively.
It is connected to the.

The interlayer insulating film 40 is formed of, for example, a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas. The information storage capacitance element C having the stacked structure includes a lower electrode layer 35 and a dielectric film 3.
6. Since the upper electrode layers 37 are successively overlapped and the lower electrode layer 35 is formed thicker, the step shape becomes larger. Therefore, the surface of the interlayer insulating film 40 is flattened. That is, the interlayer insulating film 40 is formed on the lower electrode layer 35.
The stepped shape on the surface grows as much as the film thickness of the lower electrode layer 35, so that another lower electrode layer 35 adjacent to the lower electrode layer 35 is formed.
Is filled with an interlayer insulating film 40, whereby the surface of the interlayer insulating film 40 is planarized. Lower electrode layer 3 of information storage capacitive element C having a stacked structure of adjacent memory cells M
Of the five areas, the area of the minimum interval forms a large stepped shape having an aspect ratio of 1 or more. In this embodiment, the minimum distance between the lower electrode layers 35 is about 0.5 [μm]. A dielectric film 36 and an upper electrode layer 37 are interposed between the lower electrode layers 35. Therefore, the interlayer insulating film 40 is formed to have a thickness of at least half the minimum distance between the dielectric film 36 and the lower electrode layer 35 with the upper electrode layer 37 interposed therebetween. Moreover,
The interlayer insulating film 40 is formed with a film thickness that can secure a withstand voltage and reduce parasitic capacitance. The interlayer insulating film 40 is, for example, 250
It is formed with a film thickness of about 350 [nm].

The complementary data line 50 is connected to the polycrystalline silicon film 5
0A and a transition metal silicide film 50B. The lower polycrystalline silicon film 50A is deposited by a CVD method, for example, 100 to 15
It is formed with a thickness of about 0 [nm]. An n-type impurity such as P for reducing the resistance value is introduced into the polycrystalline silicon film 50A. Since the lower polycrystalline silicon film 50A has good step coverage in the step portion of the base, the disconnection failure of the complementary data line 50 can be reduced.
The upper transition metal silicide film 50B is deposited by a CVD method (or a sputtering method), for example, 100 to 200 [nm].
It is formed with a film thickness of about. The upper transition metal silicide film 50B can reduce the resistance value of the complementary data line 50 and increase the operation speed of each of the information writing operation and the information reading operation. In addition, since the upper transition metal silicide film 50B has good step coverage in the underlying step, the disconnection failure of the complementary data line 50 can be reduced. Each of the lower polycrystalline silicon film 50A and the upper transition metal silicide film 50B of the complementary data line 50 has heat resistance and oxidation resistance. The complementary data line 50 is formed with a wiring width of, for example, about 0.6 [μm].

As described above, the MISFET Qs for selecting a memory cell in which the complementary data line 50 is connected to one of the n-type semiconductor regions 29 and the lower electrode layer 35 formed thereabove. Dielectric film 36, upper electrode layer 3
And a memory cell M formed of a series circuit with a stacked information storage capacitor C in which each of the elements 7 is sequentially stacked.
In M1, a polycrystalline silicon film 50A and a transition metal silicide film 50B deposited by a CVD method with an interlayer insulating film 40 interposed therebetween are sequentially formed on the upper electrode layer 37 of the information storage capacitor C having the stacked structure. The complementary data line 50 formed of the laminated composite film is formed, and an interlayer insulating film 40 between the upper electrode layer 37 and the complementary data line 50 is formed.
The thickness of the lower electrode layer 35 of the stacked information storage capacitor C of the other memory cell M adjacent to the lower electrode layer 35 of the memory cell M having the stacked structure of the memory cell M at a minimum interval. The thickness is larger than one half of the interval between the upper electrode layers 37 between them. According to this configuration, the transition metal silicide film 50B in the upper layer of the complementary data line 50 causes interdiffusion of impurities. Therefore, a flow is performed using a BPSG film or a PSG film as the interlayer insulating film 40, and the complementary data line 50 is formed. Although the flattening of the underlayer surface cannot be promoted, the thickness of the interlayer insulating film 40 is controlled on the basis of the distance between the adjacent lower electrode layers 35 at the minimum distance. Can be buried in the interlayer insulating film 40 so that the surface of the interlayer insulating film 40 can be flattened.
At the time of processing 0, a short circuit between the complementary data lines 50 due to the etching residue remaining in the step portion of the interlayer insulating film 40 between the lower electrode layers 35 can be prevented, and the electrical reliability can be improved.

The column select signal line (YSL) 5 is provided above the complementary data line 50 with an interlayer insulating film 51 interposed therebetween.
2 are configured.

The interlayer insulating film 51 is, for example, a silicon oxide film 51A deposited by the CVD method, and a BPSG deposited by the CVD method.
It is composed of a composite film having a two-layer structure in which each of the films 51B is sequentially laminated. The lower silicon oxide film 51A is made of an upper BPSG
It is provided to prevent B and P added to the film 51B from leaking to the lower layer. The lower silicon oxide film 51A is formed of, for example, a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas.
The lower silicon oxide film 51A is, for example, 100 to 200 [nm].
It is formed with a film thickness of about. Upper BPSG film 51B
Is flowed so as to flatten its surface.
The BPSG film 51B is formed with a thickness of, for example, about 250 to 350 [nm].

Since the column select signal line 52 is deposited on the surface of the underlying interlayer insulating film 51, it is formed of, for example, a transition metal film deposited by sputtering. This transition metal film is formed of, for example, a W film. The column select signal line 52 is formed with a thickness of, for example, about 350 to 450 [nm]. Since the column select signal line 52 is formed in an upper layer different from the complementary data line 50, it is not defined by the wiring pitch of the complementary data line 50, and the connection between the complementary data line 50 and the memory cell M is not limited. There is no need to avoid parts. That is, the column select signal line 52 is wider than the wiring width of the complementary data line 50 and can extend substantially linearly, so that the resistance value can be reduced. The column select signal line 52 is formed with a wiring width dimension of, for example, about 2.0 [μm].

A shunt word line (WL) is formed above the column select signal line 52 with an interlayer insulating film 53 interposed therebetween.
55 are configured. Although not shown, the shunt word line 55 is connected to the word line (WL) 27 in a predetermined region corresponding to every several tens to several hundreds of memory cells M. The word line 27 is divided into a plurality in the extending direction in the memory cell array 11E, and the shunt word line 55 is divided into the plurality of divided word lines 27.
It is connected to the. The shunt word line 55 is configured to reduce the resistance value of the word line 27 and increase the selection speed of the memory cell M in each of the information writing operation and the information reading operation.

As shown in FIG. 1, the interlayer insulating film 53 includes a silicon oxide film (deposited insulating film) 53A, a silicon oxide film (coated insulating film) 53B, and a silicon oxide film (deposited insulating film) 53C.
Are formed in a three-layer structure formed by a composite film in which each of these is sequentially laminated. The silicon oxide film 53 under the interlayer insulating film 53
A, the upper layer of the silicon oxide film 53C each are tetraethoxysilane _{(TEOS: Si (OC 2 H} 5) 4) conformal plasma CVD to gas source gas (hereinafter, C-CVD) is deposited in method. Each of the lower silicon oxide film 53A and the upper silicon oxide film 53C deposited by the C-CVD method can be deposited at a low temperature (approximately 400 ° C. or lower) and has a high step coverage. Lower silicon oxide film 53
A, each of the upper silicon oxide films 53C is, for example, 250 to 3
It is formed with a thickness of about 50 [nm]. Interlayer insulating film 5
Silicon oxide film 53B of the third intermediate layer is SOG (S pin O n G las
It is formed of a silicon oxide film which is baked after being applied by the method s). The intermediate silicon oxide film 53B is formed for the purpose of flattening the surface of the interlayer insulating film 53. The middle silicon oxide film 53B is formed so as to be baked after being applied, and then to be subjected to etching on the entire surface so as to be buried only in the concave portion of the step portion. In particular, the intermediate silicon oxide film 53B is removed by etching so that it does not remain on the surface of the inner wall of the connection hole 53D formed in the interlayer insulating film 53, as described later. That is, the middle silicon oxide film 53B is configured to reduce corrosion of the aluminum film or the alloy film of the shunt word line 55 by moisture contained therein. The middle silicon oxide film 53B is applied with a thickness of, for example, about 100 [nm].

The shunt word line 55 is composed of a composite film formed by sequentially laminating a transition metal nitride film (or transition metal silicide film) 55A and an aluminum alloy film (or aluminum film) 55B. .

When the lower transition metal nitride film 55A has Cu added to the upper aluminum alloy film 55B,
It is formed of, for example, a TiN film having a barrier property. The lower transition metal nitride film 55A is formed of, for example, a TiN film when Si is added to the upper aluminum alloy film 55B. In this case, a transition metal silicide film such as MoSi ₂ is used. The lower transition metal nitride film 55A is deposited by, for example, a sputtering method and has a thickness of 100 [n].
m]. When a TiN film is used as the lower transition metal nitride film 55A, a TiN film having (200) crystal orientation is used, as will be described in detail later.

The upper aluminum alloy film 55B is obtained by adding Cu and Si to aluminum. Cu is added to reduce the migration phenomenon.
About 5% by weight is added. Si is added to reduce the alloy spike phenomenon, for example, about 1.5 [% by weight] is added. Aluminum alloy film 50B
Is deposited by, for example, a sputtering method, and 600 to 800 [n]
m].

The shunt word line 55 is, for example,
The wiring width is about 7 [μm].

As described above, the memory cell array 11E of the DRAM 1 according to the present embodiment has a multilayer wiring structure of a total of six layers in which a two-layer wiring structure is provided on a four-layer gate wiring structure.

The four-layer gate wiring structure is formed by the gate electrode 27 (or the word line 2) of the memory cell selecting MISFET Qs.
7), composed of the lower electrode layer 35, the upper electrode layer 37, and the complementary data line 50 of the stacked information storage capacitor C. The two-layer wiring structure includes a column select signal line 52 and a shunt word line 55.

CM constituting peripheral circuit of DRAM 1
The OS is configured as shown on the right side of FIG. C
The MOS n-channel MISFET Qn is formed on the main surface of the p − -type well region 22 in a region surrounded by the element isolation insulating film 23 and the p-type channel stopper region 24. The n-channel MISFET Qn
It is mainly composed of a p-type well region 22, a gate insulating film 26, a gate electrode 27, a pair of n-type semiconductor regions 29 serving as source and drain regions, and a pair of n + -type semiconductor regions 32.

The p-type channel stopper region 24 surrounding the periphery of the n-channel MISFET Qn is
And a p-type channel stopper region 25A surrounding the periphery of the memory cell selecting MISFET Qs. The p-type channel stopper region 24 is doped with a p-type impurity using the same mask as that for forming the inter-element isolation insulating film 23, and is subjected to a heat treatment for forming the inter-element isolation insulating film 23. It is formed by activating with. This p-type channel stopper region 24
Is formed in the same manufacturing process as the element isolation insulating film 23, the diffusion amount of the p-type impurity to the active region side is slightly large, but the n-channel MISFET Qn has a larger size than the memory cell selecting MISFET Qs. Since it is formed, the diffusion amount of the p-type impurity is relatively small. Therefore, the n-channel MISFET Qn is less affected by the narrow channel effect. Conversely, the p-type channel stopper region 2
Since the p-type impurity forming P <b> 4 is introduced only into the main surface of the non-active region of the p − -type well region 22, the impurity concentration on the main surface of the active region of the p − -type well region 22 can be reduced. That is, since the threshold voltage of the n-channel MISFET Qn can be lowered, the substrate effect can be reduced and the driving capability can be increased. In particular, when the n-channel MISFET Qn is used as an output stage circuit, a sufficient output signal level can be secured.

Each of the p − -type well region 22, the gate insulating film 26, the gate electrode 27 and the n-type semiconductor region 29 is formed in the same manufacturing process as the memory cell selecting MISFET Qs, and has substantially the same function. Have. That is, the n-channel MISFET Qn has an LDD structure.

The n + type semiconductor region 32 having a high impurity concentration is configured to reduce the specific resistance of each of the source region and the drain region. The n + -type semiconductor region 32 is defined by a side wall spacer 31 formed on the side wall of the gate electrode 26 by self-alignment, and is formed by self-alignment on the gate electrode 27. The sidewall spacer 31 is an n-type semiconductor region 2 forming the LDD structure.
9 is defined in the gate length direction.
The side wall spacer 31 is an n-channel MISFE
Since it is formed as a single layer in the formation region of TQn,
The size of the n-type semiconductor region 29 in the gate length direction can be reduced. Since the impurity concentration of the n-type semiconductor region 29 is low, the n-type semiconductor region 29 has a high resistance value.
9 is short, so that the n-channel MISFET Qn can improve the transmission conductance.

Among the n-channel MISFETs Qn, the n-channel MISFET Qn used in the input / output stage circuit is:
Since the interface with the external device is performed by the single power supply voltage Vcc (5 [V]), the external device is driven by the power supply voltage Vcc. This n
The channel MISFET Qn has a gate length of 8 μm, for example.
m] to reduce the electric field intensity near the drain region. On the other hand, an n-channel MISFET Qn used in an internal circuit such as a direct peripheral circuit or an indirect peripheral circuit has a low power supply voltage Vcc (about 3.3 [V]) in order to reduce power consumption.
It is driven by. The gate length of the n-channel MISFET Qn is, for example, 0.8 to 1.4 in order to achieve high integration.
[μm], and the electric field strength near the drain region is reduced by introducing the low power supply voltage Vcc. The respective n-channel MISFETs Q of the input / output stage circuit and the internal circuit
n has substantially the same structure except that the size of the gate length is changed and the power supply used is changed. That is,
N-channel MISFE for input / output stage circuit and internal circuit
TQn can be composed of the gate insulating film 26, the gate electrode 27, the n-type semiconductor region 29, and the n + -type semiconductor region 32. Further, each n-channel MISFET Qn
The size of the sidewall spacer 31 in the gate length direction can be substantially the same.

As described above, (11-6) the n-channel MISFET Q having the LDD structure used as the input / output stage circuit.
n, in the DRAM 1 having each of the n-channel MISFETs Qn having the LDD structure used as an internal circuit,
The operating voltage of the n-channel MISFET Qs of the input / output stage circuit is configured to be higher than the operating voltage of the n-channel MISFET Qn of the internal circuit, and the gate length of the n-channel MISFET Qn of the input / output stage circuit is set to the n channel of the internal circuit. The gate length of the low impurity concentration n-type semiconductor region 29 forming the LDD structure of each of the n-channel MISFETs of the input / output stage circuit and the internal circuit is substantially longer than the gate length of the MISFET Qn. And have the same dimensions. With this configuration, the n-channel MISFET Qn of the input / output stage circuit has a longer gate length and improved hot carrier withstand voltage, so that deterioration of the threshold voltage with time can be reduced and electrical characteristics can be improved. And an n-channel MISFE of the internal circuit.
TQn can reduce power consumption by using the low power supply voltage Vcc while securing the hot carrier breakdown voltage by using the low power supply voltage Vcc.
The channel MISFET Qn has a longer gate length, and the n-channel MISFET Qn of the internal circuit has a lower power supply voltage Vcc.
Since the hot carrier withstand voltage is improved by the use of the semiconductor device, the length of the low impurity concentration n-type semiconductor region 29 forming the LDD structure in the gate length direction can be independently controlled. The length in the gate length direction (or the length in the gate length direction of the sidewall spacer 31) of each n-type semiconductor region 29 having a low impurity concentration in each n-channel MISFET Qn of the internal circuit is made substantially the same. Can be. That is, the DRAM 1 can reduce the power consumption and improve the hot carrier breakdown voltage, and can reduce the number of manufacturing steps for forming the n-channel MISFET Qn, which will be described later.

In the n + type semiconductor region 32 of the n-channel MISFET Qn, an interlayer insulating film 40 and an interlayer insulating film 51 are provided.
The wiring 52 is connected through a connection hole 51C formed in the wiring. The wiring 52 is formed of a lower wiring layer having a two-layer wiring structure that is the same conductive layer as the column select signal line 52.

CMOS p-channel MISFET Qp
Are formed on the main surface of the n − -type well region 21 in a region surrounded by the element isolation insulating film 23. The p-channel MISFET Qp mainly includes an n − -type well region 21, a gate insulating film 26, a gate electrode 27, and a pair of p-type semiconductor regions 3 serving as a source region and a drain region.
0 and a pair of p + -type semiconductor regions 39.

N-type well region 21 and gate insulating film 26
And the gate electrode 27 are connected to the memory cell selecting M
It has substantially the same function as each of the ISFET Qs and the n-channel MISFET Qn.

The low impurity concentration p-type semiconductor region 30 is
A D-channel p-channel MISFET Qp is formed. The p + type semiconductor region 39 having a high impurity concentration is formed on the side wall of the gate electrode 27 by self-alignment with the side wall spacers 31 and 33C formed thereon. In other words, the p + -type semiconductor region 39 having a high impurity concentration of the p-channel MISFET Qp has a two-layer structure in which the sidewall spacer 33C is stacked on the sidewall of the sidewall spacer 31. These sidewall spacers 31 and 33C are n-channel MISFETs.
Compared with the sidewall spacer 31 of Qn, the dimension in the gate length direction is configured to be longer by an amount corresponding to the sidewall spacer 33C. In other words, the side wall spacers 31 and 33C can increase the dimension in the gate length direction and reduce the amount of diffusion of the p-type impurity in the p + -type semiconductor region 39 into the channel formation region, so that the effective channel length is reduced. And the short-channel effect of the p-channel MISFET Qp can be reduced. n
Since p-type impurities have a larger diffusion coefficient than p-type impurities,
The p-channel MISFET Qp has the above-described structure.

As described above, the (15-8) n-channel MISFET Qn having the LDD structure and the p-channel MI
In the DRAM 1 having each of the SFETs Qp, the dimension in the gate length direction of the sidewall spacers 31 and 33C formed on the side wall of the gate electrode 27 of the p-channel MISFET Qp in a self-alignment manner is determined by the gate electrode 27 of the n-channel MISFET Qn. The side wall spacer 31 formed on the side wall is self-aligned with respect to the side wall, and is longer than the dimension in the gate length direction. With this configuration, the dimension of the sidewall spacer 31 of the n-channel MISFET Qn in the gate length direction is reduced,
Low impurity concentration n-type semiconductor region 2 forming LDD structure
9 can be shortened in the gate length direction.
The transfer conductance of the n-channel MISFET Qn can be improved, the operating speed can be increased, and the size of the sidewall spacers 31 and 33C of the p-channel MISFET Qp in the gate length direction can be increased to increase the impurity concentration of the p + type semiconductor. Since the wraparound of the region 39 toward the channel formation region can be reduced, the short-channel effect of the p-channel MISFET Qp can be reduced, and high integration can be achieved.

In the p + type semiconductor region 39 of the p-channel MISFET Qp, a wiring 52 is formed through the connection hole 51C.
Is connected.

As shown on the right side of FIG. 1, the wiring 52 is connected to an upper wiring 55 via a transition metal film 54 embedded in a connection hole 53D formed in an interlayer insulating film 53. . The wiring 55 extending on the interlayer insulating film 53 is formed of an upper wiring layer of a two-layer wiring structure which is the same conductive layer as the shunt word line 55. Connection hole 5
The transition metal film 54 embedded in the 3D is formed, for example, by selective CVD.
It is formed of a W film selectively deposited on the surface of the wiring 52 exposed from the inside of the connection hole 53D by the method. The transition metal film 54 is formed in order to improve the step coverage in the step formed by the connection hole 53D of the wiring 55.

The wiring 55 (including the shunt word line 55) is formed of a composite film in which the transition metal nitride film 55A and the aluminum alloy film 55B are sequentially laminated as described above. The wiring 55 is mainly composed of the upper aluminum alloy film 5
5B regulates the signal transmission speed. Transition metal nitride film (transition metal silicide film) 55A below wiring 55
In the case where Si is added to the upper aluminum alloy film 55B, the upper aluminum alloy film 55B and the interlayer insulating film include a connection portion between the wiring 55 and the transition metal film 54 embedded in the connection hole 53D. 53 is provided in the entire area. That is, in the wiring 55, the material of the base of the upper aluminum alloy film 55B is made uniform in each of the connection hole 53D and the interlayer insulating film 53. Further, the transition metal film 55A in the lower layer of the wiring 55 has a higher migration breakdown voltage than the aluminum alloy film 55B in the upper layer. That is, even when the upper aluminum alloy film 55B is disconnected due to the migration phenomenon, a signal can be transmitted by the lower transition metal film 55A, so that the disconnection failure of the wiring 55 can be reduced.

As described above, (29-16) the transition metal film 54 buried by the selective CVD method in the connection hole 53D formed in the underlying interlayer insulating film 53, and extends on the interlayer insulating film 53. In the DRAM 1 for connecting each of the aluminum alloy films 55B to which Si is added, the aluminum alloy film 55B including the space between the transition metal film 54 and the aluminum alloy film 55B embedded in the connection hole 53 and the underlying interlayer. A transition metal nitride film (or transition metal silicide film) 55A is provided between the insulating film 53 and the insulating film 53. With this configuration, the base of the aluminum alloy film 55B is made uniform on the transition metal film 54 embedded in the connection hole 53D and on the interlayer insulating film 53, and Si added to the aluminum alloy film 55B is removed. Since precipitation at the interface between the transition metal film 54 and the aluminum alloy film 55B embedded in the connection hole 53D can be reduced, the resistance value at the interface can be reduced. The transition metal nitride film 55A provided below the aluminum alloy film 55B is
Even if the aluminum alloy film 55B is disconnected due to, for example, a migration phenomenon, the aluminum alloy film 55B can be connected with the broken portion interposed therebetween.
Disconnection failure of the wiring 55 can be reduced.

When the Cu is added to the upper aluminum alloy film 55B, the wiring 55 (including the shunt word line 55) is formed of at least the aluminum alloy film 55B.
A transition metal nitride film 55A is provided at a connection portion (interface portion) between B and the transition metal film 54 embedded in the connection hole 53D. This transition metal nitride film 55A has a barrier property as described above. That is, the wiring 55 is configured to prevent an alloying reaction due to mutual diffusion between aluminum of the upper aluminum alloy film 55B and W of the transition metal film 54 embedded in the connection hole 53D.

As described above, (31-17) the transition metal film 54 buried by the selective CVD method in the connection hole 53D formed in the underlying interlayer insulating film 53, and extends over the interlayer insulating film 53. In the DRAM 1 connecting each of the Cu-added aluminum alloy films 55B, the transition metal film 54 and the aluminum alloy film 55B embedded in the connection holes 53D are used.
A transition metal nitride film 55A having a barrier property is provided between the first and second layers. With this configuration, at the interface between the transition metal film 54 and the aluminum alloy film 55B buried in the connection hole 53D, an alloying reaction due to mutual diffusion between the transition metal and aluminum is prevented, and the resistance value of the interface is reduced. Can be reduced.

The transition metal nitride film 55 under the wiring 55
As A, those having a crystal orientation of (200) as described above are positively used. Fig. 8 shows the target voltage during sputtering.
The relationship between [KW] and the specific resistance [μΩ-cm] is shown. data
(A) and (B) show the distance from the center of the semiconductor wafer of the TiN film deposited on the surface of the semiconductor wafer by the sputtering method. Data (A) indicates that the distance from the center of the semiconductor wafer is 0 [μm], that is, Ti at the center of the semiconductor wafer.
This shows the characteristics of the N film. Data (B) shows the characteristics of the TiN film at a position at a distance of 50 [μm] from the center of the semiconductor wafer.

As shown in FIG. 8, the data (B), that is, the farther the distance from the center of the semiconductor wafer, the lower the specific resistance value of the TiN film. The X-ray diffraction spectrum of the TiN film in the region C having a high specific resistance value shown in FIG. 8 or more, for example, in a region of about 460 [μΩ-cm] or more is shown in FIG. (A diagram showing the relationship with the strength). In a region D having a low specific resistance value or less, for example, in a region of about 400 [μΩ-cm] or less, X is applied to the TiN film.
The result of the X-ray diffraction spectrum is shown in FIG. 10 (a diagram showing the relationship between the X-ray incident angle and the X-ray diffraction intensity). FIG. 9
As shown in the figure, in the region where the specific resistance value is high, the orientation of the crystal of (111) and the orientation of the crystal of (200) are mixed in the TiN film. On the other hand, as shown in FIG. 10, the TiN film has a single crystal orientation of (200). That is, Ti having a (200) crystal orientation
The N film is composed of (111) alone or (111) and (200)
8 compared to a TiN film having a crystal orientation mixed with
As shown in (1), since the specific resistance is low, there is a physical property that the film density is high. Therefore, the TiN film having the crystal orientation of (200) is excellent in heat resistance (barrier property) and has a characteristic that Si deposition can be reduced.

Thus, (33-18) the transition metal nitride film 55A in the lower layer of the wiring 55, in particular, the transition metal film 54 buried at least in the connection hole 53D and the upper aluminum alloy film 55B The transition metal nitride film 55A is composed of a TiN film having a crystal orientation of (200). With this configuration, the TiN film having the (200) crystal orientation can be used as the TiN film having the (111) crystal orientation or (11).
TiN having a mixed crystal orientation of (1) and (200)
Since the amount of Si deposited can be reduced compared to the film,
The resistance value at the interface (54-55B interface) can be further reduced, and since the specific resistance value is smaller than that of the TiN film having the other crystal orientation, the resistance value at the interface is further reduced. And the film density is high, so that the barrier properties can be further improved.

As shown in FIG. 1 and FIG. 15 (a cross-sectional view of a principal part showing a cross-sectional structure at a position different from the cross-sectional structure shown in FIG. 1), in the peripheral circuit region of the DRAM 1, For the lower wiring 52, the transition metal film is used as described above because the wiring width dimension is reduced due to high integration and the migration withstand voltage cannot be ensured with an aluminum film or an aluminum alloy film. In particular, the direct peripheral circuit as the peripheral circuit is the memory cell M of the memory cell array 11E.
MISFET Q corresponding to the arrangement pitch of
Since each of the n-channel and p-channel MISFETs Qp is arranged, the layout rule of the wiring 52 is strict.

In the case where the n + -type semiconductor region 32 of the n-channel MISFET Qn and the p + -type semiconductor region 39 of the p-channel MISFET Qp are connected in the region of the peripheral circuit, a transition metal silicide film or a laminated film thereof (for example, When a wiring is formed of the same conductive layer as the line 50), mutual diffusion of impurities occurs. Therefore, the wiring 52 does not use the same conductive layer as the complementary data line 50 used in the memory cell array 11E, and uses the above-described transition metal film that does not cause mutual diffusion of the impurities.

As described above, (26-15) the complementary data line, the shunt word line, and the column select signal line are provided on the memory cell array 11E, and two layers are provided in the peripheral circuit area of the memory cell array 11E. DR with wiring layer
In AM1, the complementary data line 50 on the memory cell array 11E is connected to the polycrystalline silicon film 5 deposited by the CVD method.
0A and a transition metal silicide film 50B are sequentially laminated, and the column select signal line 52 is
The shunt word line 55 is formed of a transition metal film deposited by a sputtering method on the complementary data line 50.
Is formed by an aluminum alloy film 55B (including a transition metal nitride film 55A) deposited by a sputtering method on the column select signal line 52, and the shunt word line 5
5 and the lower layer column select signal line 52 and the same conductive layer (52) are buried by a selective CVD method in connection holes 53D formed in an interlayer insulating film 53 between them. The lower layer wiring 52 of the two wiring layers in the peripheral circuit region is formed of the same conductive layer as the column select signal line 52. Of the wiring layers, the upper wiring 55 is formed of the same conductive layer as the shunt word line 55,
Each of the lower layer wiring 52 and the upper layer wiring 55 of the layer wiring layer is connected via the transition metal film 54 embedded in the connection hole 53D by the selective CVD method. With this configuration, the following effects can be obtained.

(1) The complementary data lines 50 on the memory cell array 11E have excellent heat resistance and oxidation resistance.
In addition, since the step coverage of the polycrystalline silicon film 50A deposited by the lower CVD method is high, disconnection failure can be reduced. In addition, since the complementary data line 50 is formed by depositing the upper transition metal silicide film 50B by the CVD method, the step coverage can be further improved and the disconnection failure can be reduced.

(2) The column select signal line 52 is
Since it is formed in the upper layer of the complementary data line 50 and can be extended substantially linearly without avoiding the connection portion (connection hole 40A) between the complementary data line 50 and the memory cell M,
The signal transmission speed can be increased to increase the respective speeds of the information writing operation and the information reading operation. In addition, since the complementary data lines 50 are formed in a different layer from the complementary data lines 50, the wiring intervals of the complementary data lines 50 in the lower layer can be reduced. The degree of integration can be improved by reducing the size.

(3) Since the shunt word line 55 has a lower resistance than the complementary data line 50 and the column select signal line 52 in the lower layer, the resistance of the shunt word line 55 is reduced to write information. The respective speeds of the operation and the information reading operation can be increased.

(4) The same conductive layer 52 as the column select signal line 52 and the same conductive layer as the shunt word line 55
The transition metal film 54 connecting each of the (55) supplements the step coverage at the connection portion of the same conductive layer (55) as the upper shunt word line 55, and reduces disconnection failure of the conductive layer (55). In addition, by forming the underlying conductive layer (52) with the same type of transition metal film (52), stress between the underlying conductive layer (52) and the underlying transition metal film (52) can be reduced.

(5) Wiring 5 in the lower layer of the peripheral circuit area
2 Particularly, the direct peripheral circuits (sense amplifier circuits and decoder circuits) of the memory cell array 11E are transition metal films and therefore have a high migration breakdown voltage, and reduce the width of the wiring 52 (reduce in accordance with the arrangement pitch of the memory cells M). Therefore, the degree of integration can be improved.

As shown in FIG. 1, a passivation film 56 is provided on the shunt word line 55 and the wiring 55 of the DRAM 1. Passivation film 5
Reference numeral 6 denotes a composite film in which a silicon oxide film 56A and a silicon nitride film 56B are sequentially laminated.

The lower silicon oxide film 56A is configured to planarize its surface, that is, the underlying surface of the upper silicon nitride film 56B. Since the lower silicon oxide film 56A has the aluminum alloy film 55B formed on the upper layers of the lower shunt word line 55 and the wiring 55, the aluminum oxide film 55B is deposited at a low temperature that does not melt the aluminum alloy film 55B. That is, the lower silicon oxide film 56A is deposited by a C-CVD method using, for example, tetraepoxysilane gas as a source gas. Since the lower silicon oxide film 56A has good step coverage at the step portion on the base surface, the surface can be flattened between the shunt word lines 55 or the wiring 55.
In a region where the aspect ratio, which is the ratio of the distance between the shunt and the film thickness, is 1 or more,
It is formed with a film thickness of half or more in between. The region having an aspect ratio of 1 or more corresponds to the minimum wiring interval or a size close to the minimum wiring interval. In the region having an aspect ratio of 1 or less, the step coverage of the upper silicon nitride film 56 does not matter. Since the space between the shunt word lines 55 is formed with a wiring interval of about 0.7 [μm], the lower silicon oxide film 56A is formed with a thickness of about 350 to 500 [nm].

The silicon nitride film 56B on the passivation film 56 is formed to improve moisture resistance. The upper silicon nitride film 56B is, for example, a plasma C
The film is deposited by the VD method and has a thickness of about 1000 to 1200 [nm]. This upper silicon nitride film 56B
Since the surface of the lower silicon oxide film 56A is flattened, it is possible to prevent the formation of nests or the like due to the growth of the overhang shape in the step portion of the base.

As described above, in the DRAM 1 in which the passivation film 56 is provided on the wiring 55 mainly composed of the (34-19) aluminum alloy film 55B, the passivation film 56 is formed of a C- A silicon oxide film 56A deposited by a CVD method,
Each of the silicon nitride films 56B deposited by the plasma CVD method is composed of a composite film in which the silicon nitride films 56B are sequentially stacked. Is formed with a film thickness that is one half or more of the interval between the wirings 55 in one or more regions. With this configuration, the passivation film 56
The lower silicon oxide film 56A can be deposited at a low temperature that does not melt the aluminum alloy film 55B of the wiring 55 and with high step coverage, and can flatten the step formed by the wiring 55. Therefore, the silicon nitride film 56B having excellent moisture resistance in the upper layer of the passivation film 56 can be formed without forming a cavity based on the step shape. As a result, no cavities are generated in the silicon nitride film 56B above the passivation film 56, and no cracks are generated in the silicon nitride film 56 and no water is accumulated in the cavities. Can be improved.

Memory cell array (MA) of DRAM 1
The boundary area between the peripheral circuit 11E and the peripheral circuit is configured as shown in FIG. 11 (schematic plan view) and FIG. 12 (an enlarged plan view of the main part of FIG. 11). That is, the p-type channel stopper region 25A formed in the inactive region of the memory cell array 11E,
Each of the p-type channel stopper regions 24 formed in the inactive region of the peripheral circuit does not overlap in the boundary region. The p-type channel stopper region 25A of the memory cell array 11E and the p-type channel stopper region 24 of the peripheral circuit
Are formed in different manufacturing steps, the impurity concentration in the non-active region, which is the boundary region, is reduced without being polymerized in the boundary region. This is because the n-type semiconductor region 29 and the n + -type semiconductor region 3 formed in the active region
2 and the pn junction breakdown voltage between the main surface portion of the boundary region of the p − -type well region 22 can be increased. However,
Since the impurity concentration on the main surface of the inactive region of the boundary region of the p − -type well region 22 is low, the threshold voltage of the parasitic MOS is reduced, and an n-type inversion layer is easily generated. The n-type inversion layer is formed with a large area surrounding the memory cell array 11E. If an active region exists across or near the boundary region, the active region has an area corresponding to the area of the n-type inversion layer. To increase. This apparently increases the pn junction area and increases the amount of leakage current at the pn junction. Therefore, as shown in FIG.
t For example, the n-channel MISFET Qn of the peripheral circuit is separated from the boundary region (does not cross the boundary region).
This separation is caused by at least the amount of mask misalignment in the manufacturing process, the n-type semiconductor region 29, and the n + -type semiconductor region 32.
The size is determined in consideration of the diffusion amount of each n-type impurity.

The memory cell array (MA) 11E
FIG. 13 (schematic plan view) and FIG.
4 (enlarged plan view of the main part of FIG. 13). That is, the p-type channel stopper region 25A of the memory cell array 11E and the p-type channel stopper region 24 of the peripheral circuit are overlapped at the boundary region. This overlapping is performed at least by an amount corresponding to a mask alignment allowance in the manufacturing process. When each of the p-type channel stopper regions 24 and 25A is overlapped, the impurity concentration in the boundary region of the non-active region increases. When the impurity concentration in the main surface portion of the non-active region of the p-type well region 22 increases,
The separation capability can be improved by increasing the threshold voltage of the parasitic MOS. Deteriorates.

Therefore, as shown in FIG. 14, active region Act, for example, n-channel MISFET Qn
Is separated from the boundary area. This separation is determined by at least the amount of mask misalignment in the manufacturing process and the amount of diffusion of the respective p-type impurities in the p-type channel stopper regions 24 and 25A and the respective n-type impurities in the n-type semiconductor region 29 and the n + -type semiconductor region 32. Perform with the dimensions considered.

A guard ring region (not shown) for preventing minority carriers generated from a normal substrate potential generation circuit ( _VBB generator circuit) 1703 from entering the memory cell array 11E is arranged in the boundary region. The guard ring region is arranged around the memory cell array 11E, and is composed of the n-type semiconductor region 29 or the n + -type semiconductor region 32. The guard ring region is provided in the memory cell array 11E (separated from the boundary region) inside each boundary region of the p-type channel stopper regions 25A and 24. Above the guard ring region, there is provided a step reducing layer formed of the same conductive layer as the lower electrode layer 35, the upper electrode layer 37, or both layers of the information storage capacitor C having the stacked structure of the memory cell M. Have been. This step reducing layer is provided in the memory cell array 11E.
The configuration is such that the step formed between the semiconductor device and the peripheral circuit is reduced, and the processing accuracy of the upper layer wiring, for example, the column select signal line 52 and the shunt word line 55 is improved and the disconnection failure is reduced.

As described above, the (8-5) p-type well region 2
P-type well region 2 whose periphery is defined by a p-type channel stopper region formed in the main surface of the non-active region 2
2, the memory cell M and the n-channel MISFET Qn of the peripheral circuit are respectively arranged on the main surface in different active regions.
In the DRAM 1, p surrounding the periphery of the memory cell M
The channel stopper region 25A and the p-type channel stopper region 24 surrounding the periphery of the n-channel MISFET Qn of the peripheral circuit are separately formed in separate manufacturing steps. The memory cells M,
The active region Act such as the n-channel MISFET Qn of the peripheral circuit is not arranged. With this configuration, the p-type channel stopper region 25A, the p-type channel stopper region 2
When each of 4 is separated at the boundary region, a large n-type inversion layer corresponding to the area of the region is easily generated in the boundary region. When an active region Act exists in the boundary region, the active region Act is formed in the active region Act. The area of the n-type semiconductor region 29 or the n + type semiconductor region 32 apparently increases by the sum of the n-type inversion layers, and the junction between the p− type well region 22 and the n-type semiconductor region 29 or the n + type semiconductor region 32 is increased. , The amount of leakage current increases, but the boundary region has an active region Act
Is not arranged, so that the amount of leak current at the junction can be reduced. When each of the p-type channel stopper region 25A and the p-type channel stopper region 24 overlaps at the boundary region, the impurity concentration of the region becomes high, but the active region Act is not arranged at the boundary region. , The pn junction breakdown voltage between the p − well region 22 and the n type semiconductor region 29 or the n + type semiconductor region 32 can be improved.

Next, a specific method of manufacturing the above-described DRAM 1 will be briefly described with reference to FIGS. 16 to 49 (a cross-sectional view of a main portion showing each manufacturing step).

First, a p − type semiconductor substrate 20 made of single crystal silicon is prepared.

(Well Forming Step) Next, a silicon oxide film 60 and a silicon nitride film 61 are formed on the main surface of the p− type semiconductor substrate 20.
Are sequentially laminated. The silicon oxide film 60 has a thickness of about 900 to
It is formed by a steam oxidation method at a high temperature of about 1000 ° C., for example, with a film thickness of about 40 to 50 nm. This silicon oxide film 60 is used as a buffer layer. The silicon nitride film 61 is used as an impurity introduction mask and an oxidation resistant mask. The silicon nitride film 61 is deposited by, for example, a CVD method, and is formed with a thickness of about 40 to 60 [nm].

Next, the silicon nitride film 61 in the n-type well region (21) formation region is removed, and a mask is formed. mask
The formation of (61) is performed using a photolithography technique (a technique for forming a photoresist mask) and an etching technique.

Next, as shown in FIG.
Using (61), an n-type impurity 21n is introduced into the main surface of the p − -type semiconductor substrate 20 through the silicon oxide film 60. The n-type impurity 21n is introduced, for example, by ion implantation using P having an impurity concentration of about 10 ¹³ [atoms / cm ² ] and energy of about 120 to 130 [KeV].

Next, using the mask (61), as shown in FIG. 17, a silicon oxide film 60 exposed from the mask is grown, and a silicon oxide film 60A thicker than that is formed.
The silicon oxide film 60A is formed only in the n-type well region (21) formation region and is used as a mask for removing the mask (61) and an impurity introduction mask. Silicon oxide film 60
A is formed by a steam oxidation method at a high temperature of about 900 to 1000 [° C.].
It is formed so as to have a thickness of about [nm]. By the heat treatment step for forming the silicon oxide film 60A, the introduced n-type impurity 21n is slightly diffused.

Next, the mask (61) is selectively removed with, for example, hot phosphoric acid.

Next, as shown in FIG. 18, using the silicon oxide film 60A as an impurity introduction mask, the silicon oxide film
A p-type impurity 22p is introduced into the main surface portion of the p − -type semiconductor substrate 20 through which the p-type impurity 22p passes. This p-type impurity 22p is, for example, 1
B (or BF ₂ ) having an impurity concentration of about 0 ¹² to 10 ¹³ [atoms / cm ² ] is used, and ion implantation is performed with an energy of about 20 to 30 [KeV]. The p-type impurity 22p is not introduced into the region where the n − -type well region (21) is formed because the silicon oxide film 60A has a large thickness.

Next, the n-type impurity 21n and the p-type impurity 22p are respectively extended and diffused to form an n-type well region 21 and a p-type well region 22, as shown in FIG. The n-type well region 21 and the p-type well region 22 are formed by performing a heat treatment in a high temperature atmosphere of about 1100 to 1300 [° C.]. Consequently, p-
The type well region 22 is formed in self-alignment with the n − type well region 21.

(Isolation Region Forming Step) Next, each of the silicon oxide films 60 and 60A is removed, and the n − -type well region 2 is removed.
1. The respective main surfaces of the p-type well region 22 are exposed.

Then, as shown in FIG. 20, a silicon oxide film 62, a silicon nitride film 63, and a polycrystalline silicon film 6
4 are sequentially laminated. The lower silicon oxide film 62 is used as a buffer layer.

The silicon oxide film 62 has a thickness of about 900 to 900, for example.
It is formed by a steam oxidation method at a high temperature of about 1000 [° C.] and has a thickness of about 15 to 25 [nm]. The middle silicon nitride film 63 is mainly used as an oxidation resistant mask.
This silicon nitride film 63 is deposited by, for example, a CVD method,
It is formed with a film thickness of about 0 to 250 [nm]. The upper polycrystalline silicon film 64 is mainly used as an etching mask for the lower silicon nitride film 63, a mask for determining the trench depth, and a mask for controlling the length of the sidewall spacer. The polycrystalline silicon film 64 is deposited by, for example, a CVD method and is formed with a thickness of about 80 to 120 [nm].

Next, as shown in FIG. 21, the upper polycrystalline silicon film 64 on the main surface of each of the inactive regions of the n-type well region 21 and the p-type well region 22 is removed to remove the active region. Is formed using the remaining polycrystalline silicon film 64. This mask (64) is formed using a photolithography technique and an etching technique. After forming the mask (64), the etching mask (photoresist film) formed by the photolithography technique is removed.

Next, as shown in FIG.
Using (64) as an etching mask, the silicon nitride film 63 exposed in the non-active region is removed, and a mask (63) is formed under the mask (64). The patterning of the mask (63) prevents contaminants from the photoresist film from being trapped in the main surfaces of the n − -type well region 21 and the p − -type well region 22 and in the silicon oxide film 62. Therefore, the mask (64) is used without using a photoresist film for patterning the mask (64).

Next, as shown in FIG.
(64) A silicon nitride film 65 and a silicon oxide film 66 are sequentially laminated on the entire surface of the substrate including the upper surface. The lower silicon nitride film 65
It is mainly used as an oxidation resistant mask, and is formed with a smaller film thickness than the mask (63). This silicon nitride film 65
Is deposited by, for example, a CVD method and is formed with a film thickness of about 15 to 25 [nm]. The upper silicon oxide film 66 is mainly used as an etching mask. This silicon oxide film 66
For example, it is deposited by a CVD method using an inorganic silane gas (SiH ₄ or SiH ₂ Cl ₂ ) and a nitrogen oxide gas (N ₂ O) as a source gas, and is formed with a thickness of about 150 to 250 [nm].

Next, as shown in FIG. 24, anisotropic etching corresponding to the thicknesses of the silicon oxide film 66 and the silicon nitride film 65 is performed, and the mask (63) and the
Mask each side wall of (64) by self-alignment
Each of (65) and (66) is formed. This mask (65),
Each of (66) is formed as a so-called sidewall spacer.

Next, as shown in FIG.
Using each of (64) and (66) as an etching mask,
A shallow groove 67 is formed in the main surface of each of the inactive regions of the n-type well region 21 and the p-type well region 22. The shallow groove 67
The depth of the lower surface of the inter-element isolation insulating film (23) formed in a later step is formed to be deeper than the junction depth of, for example, the n-type semiconductor regions (29) and (32), so that the inter-element isolation capability is improved. It is formed to enhance. The depth of the shallow groove 67 depends on the mask.
It is controlled by the film thickness of (64). That is, the mask (64) is removed while the shallow groove 67 is formed, and the mask (6) is removed.
The reaction gas component of 4) is detected, and the etching for forming the shallow groove 67 is stopped at or near the time when the reaction gas component in the mask (64) is exhausted. The shallow groove 67 is made of, for example, RI
E is formed by anisotropic etching such as E.
m].

Thus, (claim 3) a mask (6) formed of a material having an etching rate substantially equal to that of each of the n-type well region 21 and the p-type well region 22.
4), the main surfaces of the respective inactive regions of the n-type well region 21 and the p-type well region 22 are masked with the mask (64).
The shallow groove 67 is formed by etching corresponding to the film thickness.

According to this configuration, the depth of the shallow groove 67 can be controlled by the thickness of the mask (64), so that the controllability of the depth of the shallow groove 67 can be improved.

Next, the n − -type well region 21 and the p − -type well region 2 exposed by the formation of the shallow groove 67 are formed.
A silicon oxide film 62A is formed on the main surface of each of the two inactive regions. This silicon oxide film 62A is used as a buffer layer when introducing impurities. The silicon oxide film 62A is formed by, for example, a thermal oxidation method and has a thickness of about 8 to 12 [nm].

Next, as shown in FIG. 26, in the peripheral circuit forming region, the p-type impurity 2 is formed on the main surface portion of the inactive region of the p − -type well region 22 through the silicon oxide film 62A.
4p is introduced. To introduce the p-type impurity 24p, the masks (63) and (66) and a photoresist mask (not shown) are used as impurity introduction masks. p-type impurity 2
4p is introduced by ion implantation at an energy of about 50 to 70 [KeV] using, for example, BF ₂ having an impurity concentration of about 10 ¹³ [atoms / cm ² ]. This p-type impurity 24p is introduced in a peripheral circuit formation region in a self-aligned manner with respect to the active region.

Next, each of the masks (63) and (65) is mainly used as an oxidation resistant mask,
An isolation insulating film (field insulating film) 23 is formed on the silicon oxide film 62A on the main surface of each inactive region of the p − -type well region 22. At this time, the silicon oxide film 66 is removed with a hydrofluoric acid-based etchant before the formation of the element isolation insulating film 23. The element isolation insulating film 23 is,
In a nitrogen gas atmosphere containing a very small amount of oxygen (about 1 [%] or less) at a considerably high temperature of about 0
After performing a heat treatment of 0 to 40 [minutes], it can be formed by oxidizing about 30 to 50 [minutes] by a steam oxidation method. The element isolation insulating film 23 is, for example, 400 to 60.
It is formed with a thickness of about 0 [nm].

The end of the insulating film for element isolation 23 on the active region side has a thin mask (65) directly contacting the substrate, so that it is in the lateral direction (the active region side) at the beginning of oxidation. Is reduced, and the mask (63) having a large thickness can reduce the growth in the lateral direction even if the oxidation progresses.
Bird's beak can be reduced. On the other hand, the mask (65) having a small film thickness can be lifted on the bird's beak as the oxidation proceeds, so as to relieve stress and reduce occurrence of defects. That is, the inter-element isolation insulating film 23 is
Bird's beak is small and a thick film can be formed. Therefore, the inter-element isolation insulating film 23 can be formed to have a size that is somewhat equal to the size of the mask (63) forming the same, so that the inter-element isolation area is reduced and the effective area of the active region is increased. be able to.

By the heat treatment for forming the element isolation insulating film 23, the p-type
P-type impurity 24 introduced into the main surface of p-type well region 22
The p is expanded and diffused, and the p-type channel stopper region 24 is formed.
Is formed. The heat treatment also diffuses the p-type impurity 24p in the lateral direction (on the active region side). The lateral diffusion amount of the impurity 24p is relatively small.
That is, the n-channel MISFET Qn is less affected by the narrow channel effect.

Next, the masks (63) and (65) and the silicon oxide film 62 are removed, and the n-type well region 21 and the p-type well region 21 are removed.
The main surface of each active region of the mold well region 22 is exposed. Thereafter, as shown in FIG. 27, the exposed n-
A silicon oxide film 68 is formed on each main surface of the p-type well region 21 and the p-type well region 22. The silicon oxide film 68 is formed at the end of the inter-element isolation insulating film 23 by each of the silicon nitride films (masks) 63 and 65 mainly used when forming the inter-element isolation insulating film 23. This is performed to oxidize the nitride of so-called white ribbon. The silicon oxide film 68 is formed by, for example, a high-temperature steam oxidation method of about 900 to 1000 [° C.] and has a thickness of about 40 to 100 [nm].

Next, as shown in FIG. 28, in the formation region of the memory cell array 11E, the p − type well region 22 is formed.
A p-type channel stopper region 25A and a p-type semiconductor region 25B are formed on the main surface of the semiconductor device. The p-type channel stopper region 25A is formed in a non-active region below the element isolation insulating film 23. The p-type semiconductor region 25B is formed in an active region that is a region where the memory cell M is formed. Each of the p-type channel stopper region 25A and the p-type semiconductor region 25B
For example, it is formed by introducing B having an impurity concentration of about 10 ¹² to 10 ¹³ [atoms / cm ² ] by a high energy ion implantation method of about 200 to 300 [Kev]. In the main surface portion of the inactive region of the p− type well region 22,
The type impurity is introduced through the element isolation insulating film 23.
In the main surface portion of the active region, the p-type impurity is introduced into a deep portion of the main surface portion of the p − -type well region 22 by an amount corresponding to the thickness of the inter-element isolation insulating film 23. Each of the p-type channel stopper region 25A and the p-type semiconductor region 25B formed by this method is formed in self-alignment with the element isolation insulating film 23.

As described above, (1-1) p-type well region 2
2 in which a MISFET Qs for selecting a memory cell is formed on a main surface in an active region surrounded by two non-active regions.
Forming a first mask in which masks (63) and (64) are sequentially laminated on the main surface of the active region of the p − -type well region 22, and forming a first mask on the side wall of the first mask. A mask of the first mask formed by self-alignment
Forming a second mask in which masks (65) and (66) each having a smaller thickness than that of (63) are sequentially laminated;
The p-type well region 2 is formed by using a mask and a second mask.
Etching is applied to the main surface of the non-active region 2
Forming a shallow groove 67 in an inactive region of the p-type well region 22; and performing a thermal oxidation process using the first mask and the second mask to form a main surface of the inactive region of the p-type well region 22. Forming an element isolation insulating film (field insulating film) 23 thereon; and removing the first mask and the second mask, and then removing the active region and the inactive region of the p-type well region 22. P-type impurities are introduced into the main surface of
Forming the p-type channel stopper region 25A in the main surface portion of the p-type well region 22 below the element isolation insulating film 23. With this configuration, the amount of lateral oxidation of the inter-element isolation insulating film 23 can be reduced, so that the size of the inter-element isolation insulating film 23 can be reduced and the film thickness can be increased. Utilizing the shallow groove 67, the position of the lower surface of the inter-element isolation insulating film 23 is made deeper than the main surface of the active region of the p − -type well region 22 so that the separation dimension between the memory cell selecting MISFETs Qs is p− Since the gain in the depth direction of the mold well region 22 can be increased, the separation capability between the memory cell selecting MISFETs Qs can be increased, and the inter-element isolation insulating film 23 is formed to have a large thickness.
When the p-type impurity for forming the p-type channel stopper region 25A is introduced, the p-type impurity introduced into the main surface portion of the active region of the p-type well region 22 is removed.
Can be introduced at a deep position, so that the variation of the threshold voltage of the memory cell selecting MISFET Qs due to the introduction of the p-type impurity can be reduced.

(4-2) Insulating film 2 for element isolation
Step 3 is performed by a high-temperature oxidation method in a range of about 1050 to 1150 [° C.]. With this configuration, when the inter-element isolation insulating film 23 is formed, the fluidity of the silicon oxide film based on the high-temperature oxidation method is promoted, and the inter-element isolation insulating film 23 and the n-type well region 21 and the p-type Since stress generated between the non-active region of the well region 22 and the main surface of each inactive region can be reduced, the main surface of each of the inactive regions of the n-type well region 21 and the p-type well region 22 can be reduced. Shallow groove 6 formed in
It is possible to reduce the occurrence of crystal defects at the corners of No. 7.

The shallow groove 67 formed on the main surface of each of the inactive regions of the n − -type well region 21 and the p − -type well region 22 is used when crystal defects cannot be recovered or when unnecessary. Need not be formed. In this case, the mask
(64) is eliminated, and the thickness of the mask (65) is reduced to 200 to 300.
[nm] may be used.

(5-3) The memory cell selecting MISFET Qs forming the memory cell M and the n-channel MISFET Qn forming the peripheral circuit are respectively formed by the element isolation insulating films 23 and p in the p − -type well region 22. DRAM 1 formed on a main surface of an active region in a region surrounded by an inactive region formed by a mold channel stopper region,
MISF for selecting memory cells in the p-type well region 22
On the main surface of the active region forming the ETQs and the non-active region surrounding the active region, the non-active region is formed by passing a p-type impurity through the element isolation insulating film 23 to form a p-type channel stopper region. 25A, a p-type impurity 2 is formed on the main surface of the inactive region surrounding the active region forming the n-channel MISFET Qn of the p − -type well region 22.
The p-type channel stopper region 24 is provided by introducing 5p. With this configuration, the p-type channel stopper region 2
5A, the threshold voltage of the parasitic MOS is increased, and the memory cell M
And memory cell selecting MISFET Qs forming the same
And the memory cells M surrounding the memory cells,
The p-type channel stopper region 25A is formed in self-alignment with the element isolation insulating film 23, and the amount of p-type impurities forming the p-type channel stopper region 25A is reduced toward the active region. Accordingly, the channel effect of the memory cell selecting MISFET Qs can be reduced, and the p-type impurity 24p forming the p-type channel stopper region 24 is introduced only into the non-active region, thereby reducing the n-channel MISFET Qn. Since it is not introduced into the active region to be formed, the influence of the substrate effect can be reduced, and the fluctuation of the threshold voltage of the n-channel MISFET Qn can be reduced.

Note that, as described above, the n-channel MI
The SFET Qn is a MIS for selecting a memory cell of the memory cell M.
Since the size is larger than that of the FET Qs, the n-channel MISFET Qn has a relatively small diffusion amount of the p-type impurity 24p forming the p-type channel stopper region 24p to the active region side, and almost causes a narrow channel effect. Absent.

Further, the n-channel MISFET Qn
In this method, the p-type impurity 24p forming the p-type channel stopper region 24 is not introduced into the active region, and the impurity concentration on the surface of the active region can be reduced. Can increase. In particular,
When the n-channel MISFET Qn is used as an output stage circuit, a sufficient output signal level can be secured.

(7-4) MISFET Qs for selecting a memory cell of the memory cell M, n-channel MISFET
Each of Qn is provided on the main surface of p-type well region 22 having a higher impurity concentration than p-type semiconductor substrate 20.
With this configuration, the memory cell selecting MISFET Qs and the n-channel MISFET Q in the p − -type well region 22 are formed.
Since the impurity concentration of each of the n channel formation regions can be increased, the short channel effect can be reduced, and
The p-type well region 22 and the p-type semiconductor substrate 20
Since the potential barrier region can be formed by the difference between the respective impurity concentrations, the α-ray soft error withstand voltage of the memory cell M can be particularly improved.

The n-channel MISFET Qn
When a direct peripheral circuit such as the column address decoder circuit (YDEC) 12 or the sense amplifier circuit (SA) 13 is formed, similarly, the α-ray soft error withstand voltage can be improved.

(Step of forming gate insulating film) Next, the n-
A silicon oxide film 68A is formed on the main surface of each of the active regions of the p-type well region 21 and the p-type well region 22. The silicon oxide film 68A is formed again after removing the silicon oxide film 68. The silicon oxide film 68A may have a thickness of about 15 to 24 [nm].

Next, as shown in FIG. 29, in the region where the peripheral circuit is formed, the active region defined by the inter-element isolation insulating film 23 of each of the n − -type well region 21 and the p − -type well region 22. A p-type impurity 69p for adjusting the threshold voltage is introduced into the main surface of the substrate. The p-type impurity 69p is, for example, 10
Using B having an impurity concentration of about ¹² [atoms / cm ² ],
It is introduced by an ion implantation method with an energy of about 30 [KeV]. This p-type impurity 69p is mainly composed of an n-channel MISFE
It is introduced to adjust the respective threshold voltages of TQn and Qp. Further, p-type impurity 69p may be introduced into the respective main surfaces of n-type well region 21 and p-type well region 22 by separate steps.

Next, the silicon oxide film 68A is selectively removed to expose the respective main surfaces of the p − -type well region 22 and the n − -type well region 21.

Next, the exposed p-type well region 22,
A gate insulating film 2 is formed on each main surface of n-type well region 21.
6 is formed. The gate insulating film 26 has a thickness of 800 to 1000
Formed by steam oxidation at a high temperature of about [° C]
It is formed with a thickness of about 8 [nm].

(Gate Wiring Forming Step 1) Next, a polycrystalline silicon film is formed on the entire surface of the substrate including the gate insulating film 26 and the inter-element isolation insulating film 23. Polycrystalline silicon film is CVD
It is deposited by a method and formed to a thickness of about 200 to 300 [nm]. An n-type impurity such as P for reducing the resistance value is introduced into the polycrystalline silicon film by a thermal diffusion method. After this,
A silicon oxide film (not shown) is formed on the surface of the polycrystalline silicon film by a thermal oxidation method. This polycrystalline silicon film is formed in a first-layer gate wiring forming step in the manufacturing process.

Next, an interlayer insulating film 28 is formed on the entire surface of the polycrystalline silicon film. This interlayer insulating film 28 is formed by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas. The interlayer insulating film 28 is, for example, 240 to 350 [nm].
It is formed with a film thickness of about

Next, as shown in FIG. 30, the interlayer insulating film 28 and the polycrystalline silicon film are sequentially etched using an etching mask (not shown) to form a gate electrode 27 and a word line (WL) 27. . Also, the gate electrode 27,
An interlayer insulating film 28 is left over each of the word lines 27. The etching is performed by anisotropic etching.

(Step of Forming Low Concentration Semiconductor Region) Next, in order to reduce contamination due to impurity introduction, a silicon oxide film (not denoted by a reference numeral) is formed on the entire surface of the substrate. This silicon oxide film is formed in the p-type well region 2 exposed by the etching.
2, formed on each main surface of the n − -type well region 21 and on each side wall of the gate electrode 27 and the word line 27. The silicon oxide film is formed in a high-temperature oxygen gas atmosphere of, for example, about 850 to 950 [° C.] and has a thickness of about 10 to 20 [nm].

Next, the memory cell array 11E and the n-channel MISF are formed by using the element isolation insulating film 23 and the interlayer insulating film 28 (and the gate electrode 27) as an impurity introduction mask.
In each formation region of the ETQn, an n-type impurity 29n is introduced into the main surface of the p − -type well region 22. N-type impurity 29n is introduced in self-alignment with gate electrode 27. The n-type impurity 29n is, for example, 10 ¹³ [atoms / cm ² ]
Using P (or As) with an impurity concentration of about 30 to 50
It is introduced by an ion implantation method with energy of about [KeV]. Although not shown, when the n-type impurity 29n is introduced, the formation region of the p-channel MISFET Qp is covered with an impurity introduction mask (for example, a photoresist film).

Next, as shown in FIG. 31, the p-channel MISFET is formed by using the element isolation insulating film 23 and the interlayer insulating film 28 (and the gate electrode 27) as an impurity introduction mask.
In the Qp formation region, a p-type impurity 30p is introduced into the main surface of the n − -type well region 21. The p-type impurity 30p is introduced in self-alignment with the gate electrode 27. The p-type impurity 30p is, for example, B (or BF ₂ ) having an impurity concentration of about 10 ¹² [atoms / cm ² ] and is introduced by ion implantation at an energy of about 20 to 30 [Kev]. Although not shown, when the p-type impurity 30p is introduced, the respective formation regions of the memory cell array 11E and the n-channel MISFET Qn are covered with an impurity introduction mask (photoresist film).

(High concentration semiconductor region forming step 1)
Sidewall spacers 3 are provided on the respective side walls of the gate electrode 27, the word line 27, and the interlayer insulating film 28 thereon.
Form one. The side wall spacer 31 can be formed by depositing a silicon oxide film and performing anisotropic etching such as RIE by an amount corresponding to the thickness of the deposited silicon oxide film. The silicon oxide film of the sidewall spacer 31 has the same film quality as that of the interlayer insulating film 28, and has a CV having an inorganic silane gas and a nitrogen oxide gas as a source gas.
Formed by method D. This silicon oxide film is, for example, 130 to 18
It is formed with a thickness of about 0 [nm]. The length of the side wall spacer 31 in the gate length direction (channel length direction) is about 15
It is formed at about 0 [nm].

Next, the n-channel MISFET of the peripheral circuit
As shown in FIG. 32, an n-type impurity 32n is introduced into the formation region of Qn. The introduction of the n-type impurity 32n is mainly performed using the sidewall spacer 31 as an impurity introduction mask. Also, an n-channel MISFET Q
n region other than the formation region, that is, the memory cell array 1
1E, the respective formation regions of the p-channel MISFET Qp are covered with an impurity introduction mask (photoresist film) (not shown) when introducing the n-type impurity 32n. As the n-type impurity 32n, for example, As (or P) having an impurity concentration of about 10 ¹⁵ [atoms / cm ² ] is used, and 70 to 90 [Ke] is used.
[V] is introduced by ion implantation.

Next, as shown in FIG. 33, a heat treatment is performed to extend and diffuse each of the above-described n-type impurities 29n, n-type impurities 32n and p-type impurities 30p. Semiconductor region 32, p-type semiconductor region 30
To form each. The heat treatment is, for example, 900 to 100.
This is performed at a high temperature of about 0 ° C. for about 20 to 40 minutes. The n
By forming the type semiconductor region 29, the memory cell M
MISFET Qs for selecting a memory cell having the LDD structure is completed. Further, by forming the n-type semiconductor region 29 and the n + -type semiconductor region 32, the n-channel MISFET Qn having the LDD structure is completed. This n-channel MISF
The ETQn is used in a peripheral circuit (for low voltage) and an input / output stage circuit (for high voltage) of the DRAM 1. Also, the p-channel M
Although the p-type semiconductor region 30 constituting the LDD structure of the ISFET Qp is completed, the p-type semiconductor region 39 is formed after the completion of the memory cell M.
Qp is completed in a later step.

As described above, (13-7) the n-channel MIS having the LDD structure for the high voltage used as the input / output stage circuit.
FET Qn, LD for low voltage used as peripheral circuit
D having each of n-channel MISFETs Qn having a D structure
In the RAM 1, the high-voltage n-channel MISFET is provided on the main surface of each of the different active regions of the p − -type well region 22.
Forming the respective gate insulating films 26 and the gate electrodes 27 of the Qn and low-voltage n-channel MISFETs Qn in the same manufacturing process; Channel MISFETQ
forming a low impurity concentration n-type semiconductor region 29 for forming an LDD structure in a self-alignment manner with each of the gate electrodes 27 of the n-channel MISFET Qn for low voltage in the same manufacturing process; MISFETQ
forming a sidewall spacer 31 on the side wall of each gate electrode 27 of the n-channel MISFET Qn for low voltage and n-type in the same manufacturing process;
High-voltage n-channel MISFET Q in the active region of
forming a high impurity concentration n + -type semiconductor region 32 in self-alignment with the sidewall spacer 31 on each main surface of the n-channel MISFET Qn for low voltage. With this configuration, the high-voltage n-channel MI
Since all the steps of forming the SFET Qn and the low-voltage n-channel MISFET Qn are shared, and in particular the respective sidewall spacers 31 can be formed in the same manufacturing step, the number of manufacturing steps of the DRAM 1 can be reduced.

(Interlayer Insulating Film Forming Step 1) Next, an interlayer insulating film 33 is formed on the entire surface of the substrate including the interlayer insulating film 28, the sidewall spacers 31 and the like. The interlayer insulating film 33 is used as an etching stopper layer when processing each electrode layer of the information storage capacitor C having a stacked structure. The interlayer insulating film 33 includes a lower electrode layer (35) of the information storage capacitor C having a stacked structure, the gate electrode 27 of the memory cell selection MISFET Qs, and the word line 2.
7 are formed to electrically isolate each of them.
The interlayer insulating film 33 is configured to increase the thickness of the sidewall spacer 31 of the p-channel MISFET Qp. The interlayer insulating film 33 is formed with a film thickness that mainly takes into account the amount of shaving due to over-etching during processing of the upper conductive layer, the amount of shaving in the cleaning step, and the like. Interlayer insulating film 33
Is formed of a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas. That is, the interlayer insulating film 33 is formed of the dielectric film (36) of the stacked information storage capacitor C or the underlying interlayer insulating film 28.
Can be reduced due to the difference in linear expansion coefficient between the two. The interlayer insulating film 33 is, for example, 130 to 1
It is formed with a thickness of about 80 [nm].

Next, as shown in FIG.
The other n-type semiconductor region (the lower electrode layer 3 of the information storage capacitor C) of the memory cell selection MISFET Qs in the formation region
The above-mentioned interlayer insulating film 33 on the side (to which 5 is connected) 29 is removed, and connection holes 33A and 35 are respectively formed. The connection hole 35 is formed when the sidewall spacer 31 and the interlayer insulating film 33 are etched.
Is formed in a region defined by each of the side wall spacers 33B deposited on the side wall.

(Gate Wiring Forming Step 2) Next, as shown in FIG. 35, the lower electrode layer 35 of the information storage capacitor C having the stacked structure of the memory cell M is formed on the entire surface of the substrate including the interlayer insulating film 33. A polycrystalline silicon film to be formed is deposited. A part of the polycrystalline silicon film is connected to the n-type semiconductor region 29 through each of the connection holes 33A and 35. This polycrystalline silicon film is formed of a polycrystalline silicon film deposited by a CVD method, and has a thickness of about 150 to 240 [nm]. This polycrystalline silicon film is formed by the second-layer gate wiring forming step in the manufacturing process. After the deposition, an n-type impurity such as P for reducing the resistance value is introduced into the polycrystalline silicon film by a thermal diffusion method. The n-type impurity is diffused in a large amount into the n-type semiconductor region 29 through the connection hole 35,
The n-type impurity is introduced at a low impurity concentration so that the n-type impurity does not diffuse into the channel formation region of the memory cell selecting MISFET Qs.

Next, as shown in FIG. 36, a polycrystalline silicon film is further deposited on the polycrystalline silicon film. The upper polycrystalline silicon film is deposited by a CVD method,
It is formed with a thickness of about [nm]. After deposition, an n-type impurity such as P for reducing the resistance value is introduced into the upper polycrystalline silicon film by a thermal diffusion method. This n-type impurity is introduced at a high impurity concentration in order to improve the amount of charge stored in the information storage capacitor C having a stacked structure.

Next, as shown in FIG. 37, the lower-layer electrode layer 35 is formed by processing the polycrystalline silicon film having the two-layer structure into a predetermined shape by using a photolithography technique and an anisotropic etching technique. The photolithography technique includes a step of forming an etching mask (photoresist film) and a step of removing the etching mask. The step of removing the etching mask includes, for example, freon gas (CHF ₃ ) and oxygen gas (O ₂ ).
And a downstream plasma process using a mixed gas of This process has the effect of reducing damage to each element of the DRAM 1.

As described above, (19-11) the DRAM in which the memory cell M is constituted by the series circuit of the memory cell selecting MISFET Qs and the information storage capacitor C having the stacked structure
1, one of n of the memory cell selecting MISFETs Qs of the information storage capacitor C having the stacked structure
The lower electrode layer 35 connected to the type semiconductor region 29 is
It is composed of a composite film in which a polycrystalline silicon film into which an n-type impurity for reducing the resistance value is introduced at a low concentration and a polycrystalline silicon film into which the n-type impurity is introduced at a high concentration are sequentially laminated. With this configuration, the thickness of the lower electrode layer 35 of the information storage capacitor C having the stacked structure of the memory cell M is increased, and the area of the side wall of the lower electrode layer 35 is increased in the height direction by the increased thickness. Therefore, the amount of charge accumulation can be increased, the area of the memory cell M can be reduced, and the degree of integration can be improved.
Since the impurity concentration on the surface of the upper polycrystalline silicon film of the lower electrode layer 35 is high, the charge storage amount can be increased and the degree of integration can be further improved.
5 can reduce the impurity concentration of the polycrystalline silicon film and reduce the amount of diffusion of the n-type impurity into one n-type semiconductor region 29 of the memory cell selecting MISFET Qs. The channel effect can be reduced, the area of the memory cell M can be reduced, and the degree of integration can be further improved. In the present invention, the lower electrode layer 35 may be formed by depositing a polycrystalline silicon film in three or more layers and introducing an n-type impurity into each polycrystalline silicon film.

(21-12) MI for memory cell selection
SFET Qs and stacked structure information storage capacitor C
In the DRAM 1 in which the memory cell M is formed by a series circuit with the memory cell selection M in the p − -type well region 22,
Depositing a first-layer polycrystalline silicon film over the entire surface of the interlayer insulating film 33 including over the ISFET Qs, and then introducing an n-type impurity for reducing the resistance value into the first-layer polycrystalline silicon film; A step of depositing a second-layer polycrystalline silicon film over the entire surface of the first-layer polycrystalline silicon film and then introducing an n-type impurity for reducing the resistance value into the second-layer polycrystalline silicon film Then, predetermined patterning is sequentially performed on each of the second-layer polycrystalline silicon film and the first-layer polycrystalline silicon film by anisotropic etching to obtain the information storage capacitor C having the stacked structure.
And forming a lower electrode layer 35. With this configuration, even when the thickness of the lower electrode layer 35 of the information storage capacitor C having the stacked structure is increased, the amount of impurities introduced therein is ensured to some extent and is made uniform. Can be increased and the etching rate can be increased. Since the improvement of the anisotropy of the anisotropic etching can reduce the size of the lower electrode layer 35, the area of the memory cell M can be reduced and the integration degree of the DRAM 1 can be improved.

(Dielectric Film Forming Step) Next, as shown in FIG. 38, a dielectric film 36 is formed on the entire surface of the substrate including the lower electrode layer 35 of the information storage capacitor C having the stacked structure of the memory cell M. Form. As described above, the dielectric film 36 is basically formed in a two-layer structure in which the silicon nitride film 36A and the silicon oxide film 36B are sequentially laminated. The lower silicon nitride film 36A is deposited by, for example, a CVD method, and
It is formed with a thickness of about [nm]. When the silicon nitride film 36A is formed, entrapment of oxygen is suppressed as much as possible. When the silicon nitride film 36A is formed on the lower electrode layer 35 (polycrystalline silicon film) at a normal production level, a trace amount of oxygen is involved, so that the lower electrode layer 35 and the silicon nitride film 3 are formed.
6A, a natural silicon oxide film (not shown) is formed.

The silicon oxide film 36 above the dielectric film 36
B is formed by applying a high-pressure oxidation method to the lower silicon nitride film 36A, and is formed to a thickness of about 1 to 3 [nm]. When the silicon oxide film 36B is formed, the thickness of the lower silicon nitride film 36A is slightly reduced. The silicon oxide film 36B is basically 1.5 to 1
It is formed in an oxygen gas atmosphere at a high pressure of 0 [toll] and a high temperature of about 800 to 1000 [° C.]. In this embodiment, the silicon oxide film 36B has a high pressure of 3 to 3.8 [toll] and an oxygen flow rate (source gas) of 2 [l / min] and a hydrogen flow rate (source gas) of 3 to 3 [toll] during oxidation. It is formed as 8 [l / min]. The silicon oxide film 36B formed by the high pressure oxidation method has a normal pressure.
A desired film thickness can be formed in a shorter time than a silicon oxide film formed by (1 [toll]). In other words, the high-pressure oxidation method can shorten the time of heat treatment at a high temperature,
The pn junction depth of the source region and the drain region of the memory cell selection MISFET Qs and the like can be reduced.
The natural silicon oxide film can be made thinner by reducing entrapment of oxygen. Although the number of manufacturing steps increases, the natural silicon oxide film can be nitrided to form the dielectric film 36 in a two-layer structure.

(Gate Wiring Forming Step 3) Next, a polycrystalline silicon film is deposited on the entire surface of the substrate including the dielectric film 36.
The polycrystalline silicon film is deposited by a CVD method,
It is formed with a thickness of about [nm]. This polycrystalline silicon film is formed in a third-layer gate wiring forming step in the manufacturing process. Thereafter, an n-type impurity such as P for reducing the resistance value is introduced into the polycrystalline silicon film by a thermal diffusion method.

Next, the memory cell selecting MISFET Qs
An etching mask is formed on the polycrystalline silicon film over the entire surface of the memory cell array 11E except for the connection region between the one n-type semiconductor region 29 and the complementary data line (50). The etching mask is formed of, for example, a photoresist film using a photolithography technique. After this, FIG.
As shown in FIG. 9, an upper electrode layer 37 is formed by sequentially performing anisotropic etching on each of the polycrystalline silicon film and the dielectric film 36 using the etching mask. By forming the upper electrode layer 37, the information storage capacitor C having a stacked structure is substantially completed, and as a result, the memory cell M of the DRAM 1 is completed. After the completion of the memory cell M, the etching mask is removed.

Next, as shown in FIG. 40, an insulating film (silicon oxide film) 38 is formed on the surface of the upper electrode layer 37 by performing a thermal oxidation treatment. The step of forming the insulating film 38 is performed when the upper electrode layer 37 is patterned.
This is a step of oxidizing the etching residue (polycrystalline silicon film) remaining on (the surface of the interlayer insulating film 33). The information storage capacitive element C having a stacked structure includes a MISFE for selecting a memory cell.
Two lower electrode layers 35 and an upper electrode layer 3 are formed above the TQs.
Since 7 is deposited, the shape of the step is large, and particularly, the shape of the step at the connection portion between the complementary data line (50) and the memory cell M is large, and etching residue is likely to occur. This etching residue short-circuits the complementary data line (50) and the upper electrode layer 37.

As described above, (22-13) the MISFET Qs for selecting the memory cell in which one n-type semiconductor region 29 is connected to the complementary data line (50), the lower electrode layer 35 formed on the Information storage capacitor C having a stacked structure in which a body film 36 and an upper electrode layer 37 are sequentially stacked.
In the DRAM 1 forming the memory cell M in a series circuit with the above, a polycrystalline silicon film is deposited on the dielectric film 36 of the memory cell M by the CVD method, and a predetermined pattern is formed on the polycrystalline silicon film by anisotropic etching. Forming the upper electrode layer 37 by performing the polishing, and forming an insulating film 38 (silicon oxide film) on the surface of the upper electrode layer 37 by a thermal oxidation method. With this configuration, the etching residue of the polycrystalline silicon film remaining on the stepped portion of the underlying surface after patterning of the polycrystalline silicon film can be oxidized by a thermal oxidation step performed thereafter. And the complementary data line (50) can be prevented from being short-circuited, and the production yield can be improved.

(High concentration semiconductor region forming step 2)
In the region where the p-channel MISFET Qp of the peripheral circuit is formed, the interlayer insulating film 33 formed in the above-described process is subjected to anisotropic etching to form a sidewall spacer 33C as shown in FIG. The side wall spacer 33C is formed on the side wall of the side wall spacer 31 and is formed in self alignment with the gate electrode 27. The sidewall spacer 33C is formed so as to lengthen the dimension of the sidewall spacer 31 of the p-channel MISFET Qp in the gate length direction. The total dimension in the gate length direction of the side wall spacers 31 and 33C is about 200 [nm] as described above.

Next, an n-channel MISFET is formed on the upper electrode layer 37 of the information storage capacitor C having the stacked structure.
An insulating film (not shown) is formed on the entire surface of the substrate including each of the p-channel MISFETs Qp and the formation region of Qn. This insulating film is mainly used as a contamination preventing film when introducing impurities. This insulating film is formed of, for example, a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas, and has a small thickness of about 10 [nm].

Next, the p-channel MISFET of the peripheral circuit
In the formation region of Qp, as shown in FIG.
Pure substance 39p is introduced. In introducing p-type impurity 39p
The sidewall spacers 31 and 33C
Used as an object introduction mask. Also, p-channel MISF
Regions other than ETQp formation region, ie, memory cell array
11E, forming regions of n-channel MISFETs Qn
Are impurities not shown when p-type impurity 39p is introduced.
It is covered with an introduction mask (photoresist film). The p-type
The impurity 39p is, for example, 10^Fifteen[atoms / cm^Two] Of the degree
Pure concentration BF _Two(Or B) using 50 to 70 [Kev]
It is introduced by an ion implantation method of about energy.

Thereafter, a heat treatment is performed, and the above-mentioned p-type impurity 39p is stretched and diffused to form ap + -type semiconductor region 39. The heat treatment is performed at a high temperature of, for example, about 900 to 1000 [° C.] for about 20 to 40 [minutes]. By forming the p + type semiconductor region 39, a p-channel MISFET Qp having an LDD structure is completed. This p-channel MI
The SFET Qp is subjected to a heat treatment (for example, a dielectric film 36) for increasing the dimension of the sidewall spacer 31 in the gate length direction by the sidewall spacer 33C and forming the information storage capacitor C having the stacked structure of the memory cell M. It is formed later. That is, the p-channel MISFE
TQp can reduce the diffusion of the p + -type semiconductor region 39 toward the channel formation region, and can reduce the short channel effect.

As described above, (17-9) the memory cell M constituted by the series circuit of the memory cell selecting MISFET Qs and the stacked information storage capacitance element C, and the LDD structure complementary MISFET constituting the peripheral circuit In the DRAM 1, the memory cell selecting MISFET of the memory cell M and the n-channel M of the peripheral circuit are provided.
A step of sequentially forming each of the gate insulating film 26 and the gate electrode 27 of the ISFET Qn and the p-channel MISFET Qp, and the memory cell selecting MISFET Qs and the n-channel MI
L of each of SFET Qn and p-channel MISFET Qp
Low impurity concentration n-type semiconductor region 2 forming DD structure
9, the step of forming each of the p-type semiconductor regions 30, and the memory cell selecting MISFET Qs and the n-channel MIS
Forming a sidewall spacer 31 on the side wall of each gate electrode 27 of each of the FET Qn and the p-channel MISFET Qp; Forming the memory cell M and the information storage capacitor C having a stacked structure of the memory cell M.
And forming the sidewall spacer 3 on the side wall of the gate electrode 27 of the p-channel MISFET Qp.
Forming a sidewall spacer 33C in a self-alignment manner with respect to the gate electrode 27 with the interposition of a p + type semiconductor region having a high impurity concentration of the p-channel MISFET Qp in a self-alignment manner with the sidewall spacer 33C. 39 is formed. With this configuration, the n-channel MISFET Qn defines the dimension in the gate length direction of the low impurity concentration n-type semiconductor region 29 forming the LDD structure with the single-layer sidewall spacer 31. 29 can be reduced in the gate length direction, and the p-channel MIS
The FET Qp includes a plurality of side wall spacers 31,
33C defines the amount of wraparound of the high impurity concentration p + type semiconductor region 39 toward the channel formation region side, and performs a heat treatment for forming the information storage capacitor C having the stacked structure of the memory cell M. Is formed, the p + type semiconductor region 39 is formed.
Can be further reduced to the channel formation region side.

(18-10) The n-channel MIS
After the step of forming the n + -type semiconductor region 32 having a high impurity concentration of the FET Qn and before the step of forming the information storage capacitor C having the stacked structure of the memory cell M, a step of forming an interlayer insulating film 33 is provided. After the formation of the interlayer insulating film 33, the sidewall spacers 33C are formed using the interlayer insulating film 33. With this configuration, part of the process of forming the sidewall spacer 33C
Since the (film deposition step) can be used also in the step of forming the interlayer insulating film 33, the amount of the DR
The number of AM1 manufacturing steps can be reduced.

(Interlayer insulating film forming step 2) Next, the DR
An interlayer insulating film 40 is stacked on the entire surface of the substrate including each element of AM1. The interlayer insulating film 40 is formed of, for example, a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas. The interlayer insulating film 40 is formed with a thickness of, for example, about 250 to 350 [nm].

Next, as shown in FIG.
A connection hole 40A is formed in the interlayer insulating film 40 at a connection portion between the semiconductor device and the complementary data line (50). This connection hole 4
0A is formed by, for example, anisotropic etching.

(Gate Wiring Forming Step 4) Next, as shown in FIG. 44, it is connected to one n-type semiconductor region 29 of the memory cell selecting MISFET Qs through the connection hole 40A and extends over the interlayer insulating film 40. Complementary data line (DL)
Form 50. The complementary data lines 50 are formed in a fourth-layer gate wiring forming step in the manufacturing process. The complementary data line 50 has a two-layer structure in which a polycrystalline silicon film 50A and a transition metal silicide film 50B are sequentially stacked. The lower polycrystalline silicon film 50A is deposited by a CVD method,
For example, it is formed with a film thickness of about 80 to 120 [nm]. After the deposition, an n-type impurity such as P is introduced into the polycrystalline silicon film 50A by a thermal oxidation method. Since the polycrystalline silicon film 50A deposited by the CVD method has high step coverage at the step-shaped portion of the connection hole 40A, the disconnection failure of the complementary data line 50 can be reduced.

Further, at the connection portion between the memory cell M and the complementary data line 50, the mask is misaligned in the manufacturing process of the connection hole 40A and the inter-element isolation insulating film 23, so that the inter-element isolation insulating film 23 is removed. When a part of the connection hole 40A is formed above, the n-type impurity is diffused from the polycrystalline silicon film 50A to the main surface of the p − -type well region 22 to connect the n-type semiconductor region 29 to the complementary data line 50. Therefore, a short circuit between the complementary data line 50 and the p − -type well region 22 can be prevented. The upper transition metal silicide film 50B is formed of, for example, a WSi ₂ film deposited by a CVD method and has a thickness of about 100 to 200 [nm]. The upper transition metal silicide film 50B is formed mainly to reduce the resistance value of the complementary data line 50B and to increase the speed of each of the information writing operation and the information reading operation. The upper transition metal silicide film 50B has a CV
Since the deposition is performed by the method D, the disconnection failure of the complementary data line 50 can be further reduced.

The complementary data line 50 is formed by depositing a lower polycrystalline silicon film 50A and an upper transition metal silicide film 50B, and then patterning them into a predetermined shape by, for example, anisotropic etching. I have.

(Interlayer Insulating Film Forming Step 3) Next, an interlayer insulating film 51 is formed on the entire surface of the substrate including on the complementary data lines 50. The interlayer insulating film 51 is made of a silicon oxide film 51A, BPSG
It has a two-layer structure in which each of the films 51B is sequentially laminated. The lower silicon oxide film 51A is deposited by, for example, a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas, and is formed with a thickness of about 100 to 200 [nm]. The lower silicon oxide film 51A is formed to prevent leakage of impurities (P and B, respectively) from the upper BPSG film 51B. The upper BPSG film 51B is deposited by, for example, a CVD method and has a thickness of about 250 to 350 [nm]. The BPSG film 51 is subjected to a flow at a temperature of about 800 ° C. or more in a nitrogen gas atmosphere, and the surface thereof is planarized.

Next, as shown in FIG. 45, a connection hole 51C is formed in the interlayer insulating film 51. The connection hole 51C is D
On the n + type semiconductor region 32, the p + type semiconductor region 39, the wiring 50 (not shown), the upper electrode layer 3 of each element of the RAM 1
7 is formed by removing the upper interlayer insulating film 51 above. The connection hole 51C is formed by, for example, anisotropic etching.

In the formation region of the p-channel MISFET Qp, the p + -type semiconductor region 39 has a large diffusion coefficient of p-type impurities. In the p + type semiconductor region 32, a region having a high impurity concentration on the surface is etched by overetching when forming the connection hole 51C, and the impurity concentration on the surface is further reduced. Also,
In the p + -type semiconductor region 39, the wiring 52 connected to the p + -type semiconductor region 39 is formed of a transition metal film (W film). Therefore, the p-channel MISFET Qp is provided on the surface of the p + type semiconductor region 39 in the region defined by the connection hole 51C.
A type impurity may be introduced to increase the impurity concentration on the surface of the p + type semiconductor region 39. With this configuration, the p + type semiconductor region 39 of the p-channel MISFET Qp and the wiring (52)
Can be reduced.

(Wiring Forming Step 1) Next, as shown in FIG. 46, the n + type semiconductor region 3 is formed through the connection hole 51C.
2. A wiring (including a column select signal line) 52 on the interlayer insulating film 51 so as to be connected to the p + type semiconductor region 39 and the like.
To form The wiring 52 is formed of a transition metal film, for example, a W film deposited by a sputtering method, for example, 350 to 450 [nm].
It is formed with a film thickness of about The wiring 52 can be formed by depositing the entire surface of the interlayer insulating film 51 and then patterning it into a predetermined shape by, for example, anisotropic etching.

(Interlayer Insulating Film Forming Step 4) Next, as shown in FIG. 47, an interlayer insulating film 53 is formed on the entire surface of the substrate including the wiring 52. The interlayer insulating film 53 has a three-layer structure in which a silicon oxide film (deposited insulating film) 53A, a silicon oxide film (coated insulating film) 53B, and a silicon oxide film (deposited insulating film) 53C are sequentially laminated. I have. The lower silicon oxide film 53A is deposited by C-CVD method with source gas Tetorae bets Kishishirangasu, 250-350 [n
m]. The middle silicon oxide film 53B is formed to planarize the surface of the interlayer insulating film 53. The silicon oxide film 53B is formed several times (2 to 5 times) by the SOG method.
(Approximately 100 to 150 [nm] in total), followed by baking (approximately 450 [° C.]), and the surface is etched back.

Due to the recession by the etching, the silicon oxide film 53B is formed only in the concave portion of the step shape on the surface of the lower silicon oxide film 53A. Further, the middle layer of the interlayer insulating film 53 may be formed of an organic material, for example, a polyimide resin film instead of the silicon oxide film 53B. The upper layer of the silicon oxide film 53C in order to increase the strength of the film as a whole an interlayer insulating film 53, for example a Tetorae preparative Kishishirangasu deposited by C-CVD method with source gas, 250-350 [n
m].

Next, a portion of the interlayer insulating film above a predetermined wiring 53 is removed to form a connection hole 53D. The connection hole 53D is formed by, for example, anisotropic etching.

Next, a transition metal film 54 is laminated (embedded) on the surface of the wiring 52 exposed in the connection hole 53D. The transition metal film 54 is formed of, for example, a W film deposited by a selective CVD method and has a thickness of about 600 to 800 [nm].
The reaction generation formula of this W film is as follows.

[0221]

(Equation 1)

(Wiring forming step 2) Next, as shown in FIG. 49, the transition metal film 54 embedded in the connection hole 53D
A wiring (including a shunt word line) 55 is formed on the interlayer insulating film 53 so as to be connected to the wiring. The wiring 55 has a two-layer structure in which a transition metal nitride film (or transition metal film) 55A and an aluminum alloy film 55B are sequentially laminated. The lower transition metal nitride film 55A is formed of, for example, a TiN film deposited by a sputtering method, and has a thickness of about 130 to 180 [nm]. This transition metal nitride film 55A
As described above, in the connection hole 53D portion, the precipitation phenomenon of Si and the alloying reaction between W and aluminum are prevented. Upper aluminum alloy film 55B
Is deposited by, for example, a sputtering method and has a thickness of 600 to 800 nm.
It is formed with a film thickness of about The wiring 55 can be formed by sequentially laminating a lower transition metal silicide film 55A and an upper aluminum alloy film 55B, and then patterning it into a predetermined shape by, for example, anisotropic etching.

(Passivation Film Forming Step) Next, as shown in FIG. 1, a passivation film 56 is formed on the entire surface of the substrate including the wiring 55. As described above, the passivation film 56 is formed of a composite film in which the silicon oxide film 56A and the silicon nitride film 56B are sequentially stacked. The lower silicon oxide film 56A is deposited by the C-CVD method using tetraepoxysilane gas as a source gas as described above. The upper silicon nitride film 56B is deposited by a plasma CVD method.

Although not shown in FIG. 1, a resin film is applied on the passivation film 56.
This resin film is formed to improve the α-ray soft error withstand voltage. This resin film is formed to a thickness of about 8 to 12 [μm] using a polyimide resin film applied by, for example, a potting technique (including a resin drop application step, a baking step, and a patterning step). I have. The resin film basically has an opening at a position corresponding to the external terminal, and is applied to the entire surface of the DRAM 1 excluding this region.

The resin film may be arranged on the surface of the DRAM 1 in a shape divided into a plurality. In other words, the resin film is disposed in each of the regions where the α-ray soft error withstand voltage of the DRAM 1 is desired to be ensured, for example, each of the memory cell array 11E and a part (12 and 13) of the direct peripheral circuit. This area is used as a division area without being arranged in the section. Thus, by dividing the resin film, the stress of the resin film can be reduced, and the cracking of the passivation film can be prevented.

(Fuse opening step)
1 has a defective complementary data line (DL) 50 and a defective word line
Each of a Y-system redundancy circuit 1812 and an X-system redundancy circuit 1806 that rescue each of the (WL) 27 (or the shunt word line 55) is arranged. This Y-system redundant circuit 1812
From the defective complementary data line 50 to the redundant complementary data line 50
The switching to is performed based on whether the fuse element F is cut or not. Similarly, the X-related redundant circuit 1806 includes the defective word line 2
7 is switched to the redundant word line 27 depending on whether the fuse element F is cut or not.

The fuse element F is formed of the same conductive layer as the complementary data line 50 and the wiring 50, as shown in FIG. Since the DRAM 1 of this embodiment employs the laser cutting method, the fuse element 50
Is cut by a laser beam. Since the cutting of the fuse element 50 becomes unstable when a thick passivation film 56 is present, a fuse opening 56C formed in the passivation film 56 is provided above the fuse element 50. Since the etching gas used for the opening of the fuse opening 56C is also an etching gas for etching the fuse element 50, an appropriate film thickness of the interlayer insulating film 51 and the interlayer insulating film 53 (800
[nm] or less of the insulating film is left. Since the conductive layer below the fuse element 50, for example, the same conductive layer as the upper electrode layer 37 of the information storage capacitor C having a stacked structure has a small thickness, the resistance value becomes high, which is not preferable as the fuse element F. Further, since the same conductive layer as each of the lower electrode layer 35 and the gate electrode 27 has a large number of insulating films on the same conductive layer, the step of forming a fuse opening is increased and complicated. Also, the wiring 5 in the upper layer of the fuse element 50
The same conductive layers 2 and 55 are not preferable as the fuse element F because they have a property of reflecting a laser beam.

This fuse element 50 and fuse opening 5
The method of forming 6C will be briefly described with reference to FIGS. 51 to 53 (cross-sectional views of main parts shown in respective manufacturing steps).

First, as shown in FIG.
0 on the region where the fuse element F is formed.
Then, the fuse element 50 is formed in the same manufacturing process.

Next, the interlayer insulating film 51 (51A and 51B)
After that, as shown in FIG. 52, a wiring 52 is formed. As shown in FIG. 52, the wiring 52 does not exist on the fuse element 50.

Next, an interlayer insulating film 53 (53A, 53B and 53C) is formed, and thereafter, a wiring 55 is formed as shown in FIG. The wiring 5 is provided on the fuse element 50.
5 does not exist.

Next, a passivation film 56 is formed,
As shown in FIG. 50, a fuse opening 56C is formed in the passivation film 56 on the fuse element 50. Although not described, the fuse opening 56C can be formed in the same manufacturing process as the step of opening the (bonding) portion of the passivation film 56 where the external terminals BP are present.

As described above, at the intersection of the (38-23) complementary data line 50 and the word line 27, the memory cell selecting MI
SFET Qs and stacked structure information storage capacitor C
And a redundant fuse element 50 for laser cutting for relieving the defective complementary data line 50 or the defective word line 27 among the complementary data lines 50 or the word lines 27. In the DRAM 1, the complementary data line 50 is composed of a composite film in which a polycrystalline silicon film 50A and a transition metal silicide film 50B deposited by a CVD method are sequentially laminated, and the laser cutting redundant fuse element 50 is formed by the complementary method. And the same conductive layer as the conductive data line 50.

With this configuration, the complementary data line 50
Is a MISFET Q for selecting a memory cell of the memory cell M
s and the stacked-structure information storage capacitance element C, so that the number of insulating layers on the laser cutting redundant fuse element 50 is reduced. The opening process of the upper insulating film can be simplified, and the composite film formed of the polycrystalline silicon film 50A and the transition metal silicide film 50B has the laser light absorption rate formed on the complementary data line 50. Since the wirings 52 and 55 are higher than the respective wirings 52 and 55, the laser cutting redundant fuse element 50 can be easily and reliably cut.

The DRAM 1 of this embodiment is completed by performing a series of these steps of forming the passivation film 56 and an opening therein.

Next, in the above-described DRAM 1 manufacturing process, the manufacturing steps of individual main parts will be described in detail.

(Steps of Forming Wiring / Connection Holes) The above-mentioned DRA
In the manufacturing method of M1, a complementary data line (DL) 50,
Each of the wiring 52, the wiring 55, and the connection holes 40A, 51C, 53D is basically processed by a photolithography technique using a multilayer resist mask. This multilayer resist mask is made of a non-photosensitive resin film (an organic film such as a polyimide resin film),
An intermediate film (an inorganic film such as a silicon oxide film applied by the SOG method),
The photosensitive resin film is formed in a three-layer structure in which each of the photosensitive resin films is sequentially laminated.

In the multilayer resist mask, a step formed by a multilayer structure is relaxed mainly by the lower film and the intermediate film.
It is used for the purpose of improving the processing accuracy of the upper photosensitive resin film and the processing accuracy of the material to be etched. The multilayer resist mask is formed by the following method.

First, a non-photosensitive resin film, an intermediate film, and a photosensitive resin film are sequentially laminated on the surface of a material to be etched (for example, the complementary data line 50) to form a multilayer resist film.

Next, the photosensitive resin film as the upper layer of the multilayer resist film is processed by ordinary exposure processing and phenomenon processing to form an etching mask.

Next, using the etching mask, the intermediate film of the multilayer resist film and the non-photosensitive resin film are sequentially patterned by anisotropic etching to form a multilayer resist mask. In this patterning, the lower non-photosensitive resin film is formed of oxygen (O ₂ ) gas and halogen (Cl ₂ , Br _2).
Etc.) Patterning by anisotropic etching technology using gas. As the etching device, for example, a reactive ion etching (RIE) device, a magnetron type RIE device, or a microwave ECR device is used. The etching pressure is, for example, about 1 to 10 [mtoor], and the high-frequency output is 0.25 to 30.
[W / cm ² ] is used. The halogen gas used in the anisotropic etching is not a method in which a solid, for example, vinyl chloride is placed in a vacuum chamber, and a halogen gas (a halogen compound is simultaneously generated) as an outgas of the vinyl chloride is used. , From the outside of the vacuum chamber to the inside.

The anisotropic etching gas of oxygen gas and halogen gas generates carboxylic acid when the lower non-photosensitive resin film is etched by oxygen gas, and when a halogen gas is added to this carboxylic acid, the vapor pressure becomes lower. Since the acid chloride is generated, the generated gas escapes well, and the amount of side etching of the lower non-photosensitive resin film can be reduced.

As described above, the multilayer resist film is formed in a three-layer structure, and the lower non-photosensitive resin film is patterned by anisotropic etching using oxygen gas and halogen gas. With this configuration, since the halogen gas is used as the anisotropic etching gas, the amount of side etching of the lower non-photosensitive resin film can be reduced, and the processing accuracy can be improved. Since a halogen compound (CF ₄ , CCl ₄ ) is not used, it is possible to prevent organic substances from adhering to the patterned side surface of the lower non-photosensitive resin film. The prevention of the adhesion of the organic substance can reduce the removal step and the contamination of the inner wall of the vacuum chamber of the etching apparatus. In addition, it is possible to reduce contamination that adheres to the inner wall of the vacuum chamber and reduce reattachment of organic substances that have fallen from the inner wall to the surface of the semiconductor wafer during a manufacturing process, thereby improving manufacturing yield. it can.

Since a halogen compound, particularly carbon (C), is not used as the anisotropic etching gas, the anisotropic etching rate can be increased.

In the anisotropic etching, since a pure halogen gas is used from outside the vacuum chamber without using a halogen gas as a solid outgas, the same effects as described above can be obtained.

(Wiring Forming Step 1) In the above-described method for manufacturing the DRAM 1, the processing accuracy of the wiring 52, that is, the W film, can be improved by employing low-temperature anisotropic etching.

Anisotropic etching for processing the wiring 52 is performed in a vacuum chamber such as an RIE apparatus. The vacuum chamber is usually maintained at a degree of vacuum in a range of about 10 to ² to ³ [torr], and anisotropic etching is performed in this state. As shown in FIG. 54 (a diagram showing the relationship between the temperature and vapor pressure of tungsten hexafluoride WF ₆ ), WF ₆ has a vapor pressure with respect to the degree of vacuum in the vacuum chamber at a low temperature of about −40 ° C. or less. Becomes 0 [mtorr] or close to it. In other words, by performing anisotropic etching in the low-temperature region, ions do not collide with the processed side wall and thus do not vaporize, and the ions collide with the bottom surface being processed and vaporize. Can be improved. As a result, the processing accuracy of the wiring 52 can be improved.

(Connection Hole Forming Step) In the above-described method for manufacturing the DRAM 1, each of the connection holes 51C (or 53D) can be formed in a tapered shape using a magnetron RIE device or a microwave ECR device.

The connection hole 51C can control a taper angle (a step angle of the connection hole) by controlling an etching pressure, an etching gas flow rate, or a high-frequency output among etching conditions. To control the taper angle without impairing the etching performance, it is desirable to control the etching pressure or the flow rate of the etching gas. The etching rate of anisotropic etching is determined by the product of the ion current and the average ion energy. When the ion current is constant, the taper angle is determined by the average ion energy. On the other hand, the ion current is proportional to the high-frequency output, and when the high-frequency output is constant, tends to be inversely proportional to the voltage Vdc between the semiconductor wafer (electrode) and the plasma.

As shown in FIG. 55 (A), the relationship between the etching pressure and the energy shows that the anisotropic etching using the RIE device has a narrow stable discharge region with respect to the etching pressure and a sharp change in the voltage Vdc. Moreover, the change of the average ion energy is also rapid. That is, the controllability of the taper angle is poor.

On the other hand, as shown in FIG. 55B, the relationship between the etching pressure and the energy is similarly shown, and the anisotropic etching using the magnetron RIE device (or the microwave ECR device) is 1 to 2 times. Since the ion amount is large by about an order of magnitude, the stable discharge region with respect to the etching pressure is widened. Accordingly, as shown in FIG. 55C, the relationship between the ion energy and the etching rate, and FIG. 55D, the relationship between the ion energy and the taper angle, the controllability of the taper angle is improved. The etching rate of the step is an etching rate determined by the ion energy corresponding to cos θ times the ion energy of the flat part. This means that the ion current density at the step portion of the taper angle θ is cos θ times the ion current density at the flat portion. As the taper angle θ approaches 90 degrees, the step portion of the connection hole becomes steeper, and the taper angle θ becomes zero.
As the degree approaches, the step is reduced.

As described above, by forming the connection hole 51C by anisotropic etching using a magnetron RIE device (or a microwave ECR device), a stable discharge region with respect to the etching pressure is widened, and the change in the voltage Vdc and the average Since each change in ion energy can be reduced, controllability of the taper angle can be improved without impairing the etching performance. That is, as shown in FIG.
The taper angle can be easily formed without variation from 60 to 80 degrees. As a result, since a tapered shape can be formed in the connection hole 51C, the disconnection failure of the wiring 52 can be reduced at the step portion of the connection hole 51C. In the present embodiment, there is no problem in the connection hole 53D because the transition metal film 54 is buried in the connection hole 53D.

(Connection Hole Forming Step) In the above-described method of manufacturing the DRAM 1, the insulating film such as the connection holes 51C and 53D is processed by low-temperature anisotropic etching.

First, the DRAM 1 (semiconductor wafer before the dicing step) is directly adsorbed to the lower electrode in the vacuum chamber of the etching apparatus via an electrostatic attraction plate. The lower electrode is constantly cooled, and as a result, the semiconductor wafer is kept at a temperature lower than normal temperature. In this state, anisotropic etching is performed on each of the interlayer insulating films 51 and 53 to form connection holes 51C and 53D.

Anisotropic etching gas (halogen compound C)
Since HF ₃ ) is deposited more on the surface of the semiconductor wafer having a lower temperature than the inner wall of the etching chamber, the use of low-temperature anisotropic etching can reduce the flow rate of the anisotropic etching gas, Contaminants adhered to the inner wall can be reduced.

(Embodiment 2) In Embodiment 2, a transition metal film is buried in connection holes connecting different wiring layers in order to improve the production yield of the DRAM 1 of Embodiment I described above. This is a second embodiment of the present invention in which a single-wafer type is adopted in the step of inserting.

FIG. 56 (sectional view of main part) shows a main part of DRAM 1 according to the second embodiment of the present invention.

As shown in FIG. 56, D in the second embodiment
The RAM 1 includes a wiring 81 formed on a base insulating film 80.
Is connected to a transition metal film 83 buried in a connection hole 82A formed in the interlayer insulating film 82. The wiring 81 is formed of an aluminum film or an aluminum alloy film.
The interlayer insulating film 82 is formed of a single layer of a silicon oxide film or a composite film mainly including the silicon oxide film. The transition metal film 83 embedded in the connection hole 82A is formed of a W film deposited by a selective CVD method. Although not shown, a wiring extending on the interlayer insulating film 82 is connected to the transition metal film 83.

The structure shown in FIG. 56 can be formed by a manufacturing method employing the following single-wafer method.

First, a contact hole 82A is formed in the interlayer insulating film 82.
Is formed, and the surface of the wiring 81 is exposed in the connection hole 82A. The surface of the wiring 81 is oxidized by being exposed, and alumina (Al ₂ O ₃ ) is generated.

Next, the alumina generated on the surface of the wiring 81 is removed by sputtering. As a sputtering method, fluorine (NF ₃ , XeF, CF) is added to argon (Ar) gas.
₄ or a CHF ₃ ) gas mixed sputtering method is used.
The argon gas can remove, by sputtering, alumina generated on the surface of the wiring 81 by the argon ions. The fluorine-based gas can enhance the sputtering rate of the alumina. Further, the fluorine-based gas removes a dangling layer formed by bombardment of argon ions on the surface of the interlayer insulating film 82, thereby improving the selectivity of the transition metal film 83 and corroding the surface of the wiring 81. Nothing. In other words, when only argon gas is used, dangling bonds are formed on the surface of the interlayer insulating film 82 and the transition metal film 83 is formed.
When a halogen compound such as Cl ₂ is mixed with argon gas, the unbonded layer can be removed, but the surface of the wiring 81 is corroded.
As described above, the sputtering method is formed by mixing a fluorine-based gas with an argon gas.

Next, a transition metal film 83 is selectively deposited on the surface of the wiring 81 in the connection hole 82A.
A transition metal film 83 is embedded in 2A.

As described above, by removing the alumina on the surface of the wiring 81 by the sputtering method using the above-described mixed gas, the wiring 81 and the transition metal film 83 can be connected well, The selectivity of the metal film 83 can be ensured.

As shown in FIG. 56, fluorine (F) of a fluorine-based gas used in the sputtering method
To sputter the surface of the aluminum particles and beat out the aluminum particles. The aluminum particles adhere to the inner wall of the connection hole 82A,
The cross contamination 81A is generated. Since the cross contamination 81A has a higher deposition rate of the transition metal film 83 than the surface of the interlayer insulating film 82, as a result, the upper portion of the transition metal film 83 protrudes from the surface of the interlayer insulating film 82. The protrusion of the transition metal film 83 lowers the processing accuracy of the upper wiring connected thereto.

DRAM 1 shown in FIG. 57 (sectional view of main part)
In order to reduce the protrusion of the transition metal film 83, the cross contamination 81A is left as it is, and a tapered portion 82B is provided above the connection hole 82A. The tapered portion 82B can be formed by isotropic etching. The connection hole 82A can be formed by anisotropic etching. That is, the tapered portion 82B removes a portion of the upper side of the cross contamination 81A to expose the surface of the interlayer insulating film 82, and the transition metal film 83 in this portion is removed.
Of the transition metal film 83 can be prevented. Meanwhile, cross contamination 81
By leaving A, the deposition rate of the transition metal film 83 can be increased, so that the manufacturing time can be reduced.

Further, the DRA shown in FIG.
M1 actively generates cross contamination 81 on the inner wall of the connection hole 82A to further increase the deposition rate of the transition metal film 83.

Although the deposition rate of the transition metal film 83 is slightly reduced, the connection holes 82A may be formed in a completely tapered shape by removing substantially all of the cross contamination 81A.

Further, by employing the single-wafer method, the controllability of the film thickness of the transition metal film 83 can be improved as compared with the batch method.

(Embodiment 3) The present embodiment 3 is different from the DRAM 1 of the above-described embodiment 2 in that a transition metal film is embedded in a connection hole connecting a semiconductor substrate and a wiring layer. The third embodiment of the present invention in which a single-wafer method is employed in this step.
It is an embodiment.

FIG. 59 shows a main part of a DRAM 1 according to the third embodiment of the present invention.

As shown in FIG. 59, according to the third embodiment,
In the RAM 1, a transition metal film 84 buried in a connection hole 80 </ b> A formed in the interlayer insulating film 80 is connected to the n + -type semiconductor region 32 formed on the main surface of the p − -type well region 22. The n + type semiconductor region 32 is made of silicon (Si) as described in the first embodiment. The interlayer insulating film 80 is formed of a single layer of a silicon oxide film or a composite film mainly including the silicon oxide film. The transition metal film 84 embedded in the connection hole 80A is
W film 84 deposited by a selective CVD method using a silicon reduction reaction (reaction between Si in n + type semiconductor region 32 and WF ₆ )
A, a W film 84B deposited by a selective CVD method utilizing a silane reduction reaction (reaction between SiH ₄ and WF ₆ ) is formed of a composite film in which each is sequentially laminated. The lower W film 84A is
Since the reaction is a silicon reduction reaction, the adhesiveness between the n + type semiconductor region 32 and the transition metal film 84 can be improved. Since the upper W film 84B is a silane reduction reaction, the amount of reduction of the surface of the n + -type semiconductor region 32 can be reduced, and the n + -type semiconductor region 32 having a shallow pn junction depth can be formed. The upper part of the transition metal film 84 is connected to a wiring (for example, an aluminum alloy film) 81 extending on the interlayer insulating film 80.

The structure shown in FIG.
In the step of forming the transition metal film 84 embedded in A,
When the upper layer W film 84B is deposited after a certain period of time has elapsed after the formation of the lower layer W film 84A, the interface between them is separated.
(The peeling portion is indicated by reference numeral 84C). This peeling occurs because the stress of the upper W film 84B is larger than that of the lower W film 84A. Further, the peeling is also caused when a reaction by-product such as a fluorine-based gas is present.

DRAM 1 shown in FIG.
Are the lower W film 84A and the upper W film 84A.
Each of the films 84B is formed continuously to prevent separation at the interface between them. The continuous formation method of the lower W film 84A and the upper W film 84B of the transition metal film 84 is as follows.

[0274] First, as shown a relationship between deposition time and source gas flow rate of the W film in selective CVD method employing the FIG. 61 (A) two wafer, WF as a source gas into the reaction furnace of the CVD apparatus ₆ Supply. WF ₆ reacts with Si on the surface of n + type semiconductor region 32 exposed in connection hole 80A shown in FIG. 60, and starts forming lower W film 84A. Along with the supply of WF ₆ , the relationship between the deposition time and the amount of reaction by-products (F ₂ , SiF ₃ , SiF ₄ ) is monitored, as shown in FIG. The amount of reaction by-products generated is
It can be measured by a gas mass (gas mass analyzer) arranged in an exhaust gas supply pipe from the reactor or a plasma emission monitor arranged in the reactor (chamber).

Next, when the lower W film 84A is formed, Si on the surface of the n + type semiconductor region 32 is not exposed, and the deposition of the W film is automatically stopped. As shown in each of (A) and (B), before the end of the silicon reduction reaction, silane gas is supplied to the reaction furnace from the decrease in the amount of reaction by-products, and the upper W film 84B starts to be deposited. In other words, the silicon reduction reaction is switched to the silane reduction reaction, and the lower W film 84A and the upper W film 84B are sequentially formed. The upper W film 84B is deposited with a predetermined thickness.

As described above, by successively forming the lower W film 84A and the upper W film 84B of the transition metal film 84, separation at the interface between them can be prevented.

Further, by employing the single-wafer method, the controllability of the film thickness of the transition metal film 84 can be improved as compared with the batch method.

(Embodiment 4) The present embodiment 4 is directed to the information storage capacitor C of the stacked structure of the memory cell M of the DRAM 1 of the above-described embodiment 1 in which the dielectric film 36 is used.
It is a fourth embodiment of the present invention, which describes a preferred forming method and apparatus.

[0279] Single-wafer CV according to Embodiment 4 of the present invention
The D apparatus is shown in FIG. 62 (schematic configuration diagram).

As shown in FIG. 62, the single wafer type CVD apparatus mainly comprises a load / unload chamber 90, a transfer chamber 91, a pretreatment chamber 92, a first reaction chamber 93, and a second reaction chamber 94. Have been. Each of the processing chambers 90 to 94 is connected via a gate valve 96.

The load / unload chamber 90 is configured such that a cassette 90A accommodating a plurality of semiconductor wafers 100 is removably mounted. The load / unload chamber 90 is configured to supply the unprocessed semiconductor wafer 100 to the transfer chamber 91 and to store the processed semiconductor wafer 100 from the transfer chamber 91.

The transfer chamber 91 is configured to supply the unprocessed semiconductor wafer 100 to each of the processing chambers 92 to 93, and to take out the processed semiconductor wafer 100 from each of the processing chambers 92 to 93. I have. As shown in FIG. 63 (main part schematic configuration diagram), the supply and unloading of the semiconductor wafer 100 is performed by a wafer transfer arm & tray 91B which is connected to and driven by the rotary drive device 91A. The transfer chamber 91 includes processing chambers 90, 92 to 93.
As in the case of each of the above, it is shut off from the atmosphere outside the apparatus, and is maintained at a high degree of vacuum where H ₂ O and O ₂ do not exist.

In the transfer chamber 91, as shown in FIG.
As shown in FIG. 3, an ultraviolet irradiation lamp 95 is provided. The ultraviolet irradiation lamp 95 has at least 5 to 6
It is configured to irradiate ultraviolet rays having energy of about [eV] or more to break the bond between Si and F, as described later.

The pre-processing chamber 92 contains the pre-processing module 9
2A is provided. This preprocessing module 92A
Mainly include a hot plate 92a, a temperature controller 92b, an exhaust pipe 92c, a vacuum pump 92d, a radical generation pipe 92e,
It comprises a microwave generator 92f, a microwave power supply 92g and a gas controller 92h. That is, the pretreatment chamber 9
Numeral 2 is configured so that a natural silicon oxide film formed on the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100 can be removed by anisotropic etching. This polycrystalline silicon film corresponds to the lower electrode layer 35 of the information storage capacitor C having the stacked structure in the DRAM 1 of the first embodiment. The anisotropic etching (dry etching) uses an oxygen gas and a halogen compound (CHF ₃ or CF ₄ ).

The first reactor chamber 93 and the second reactor chamber 94
Are provided with a common (independent) cleaning module 93A. As shown in FIG. 64 (main part schematic configuration diagram), each of the first reaction chamber 93 and the second reaction chamber 94 mainly includes a source gas supply pipe 93a, a source gas blowing plate 93b, a plate cooling pipe 93c, Susceptor 9
3d, wafer heater 93e, reactor cooling tube 93
f, an exhaust pipe 93g, a vacuum gate valve 93h, and a vacuum pump 93i. Without limitation,
The first reaction chamber 93 deposits a silicon nitride film (a silicon nitride film 36A under the dielectric film 36), and the second reaction chamber 94 deposits a polycrystalline silicon film (the lower electrode layer 35 or the upper electrode layer 37). It is configured so that it can be deposited.

If the DRAM 1 has a large capacity of 16 [Mbit], for example, high controllability of the thickness of the lower electrode layer 35 and the dielectric film 36 of the information storage capacitor C having a stacked structure is required. Therefore, a single-wafer CVD apparatus is suitable for manufacturing the DRAM 1. The first reaction chamber 9
3. In each of the second reactor chambers 94, a source gas blow-out plate 93b is disposed at a position facing the surface of the semiconductor wafer 100 held by the susceptor 93d, which is to be a deposition surface, so that the surface of the semiconductor wafer 100 is uniformly formed. It is configured so that a film can be deposited with an appropriate thickness and film quality. Each of the first reaction chamber 93 and the second reaction chamber 94 is maintained at a low temperature as a whole by a reactor cooling pipe 93f, and only the semiconductor wafer 100 is heated to a temperature optimum for the reaction by a wafer heater 93e. ing.

The source gas blow-out plate 9
3b is provided with a plate cooling pipe 93c in order to reduce a temperature rise due to radiant heat of the semiconductor wafer 100. The fine particles immediately generated by the reaction in the vicinity of the outlet of the source gas grow into coarse particles and become foreign matters when they reach the surface of the semiconductor wafer 100. Therefore, the source gas blowing plate 93b needs to be cooled by the plate cooling pipe 93c. There is.

The single-wafer CVD apparatus is an integrated continuous process in which a pretreatment chamber 92 is provided at a stage preceding each of the first reaction chamber 93 and the second reaction chamber 94 as described above. Is as follows.

First, as shown in FIG. 62, the semiconductor wafer 100 is transferred from the load / unload chamber 90 to the pre-processing chamber 92 via the transfer chamber 91. Semiconductor wafer 1
On the surface of No. 00, a polycrystalline silicon film is deposited.

Next, as shown in FIGS. 62 and 63, the pretreatment chamber 92 removes the natural silicon oxide film formed on the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100 by anisotropic etching. I do. This anisotropic etching is performed using an oxidizing gas and a halogen compound as an etching gas as described above.

Next, the semiconductor wafer 100 from which the natural silicon oxide film has been removed in the pretreatment chamber 92 is transferred to the transfer chamber 91, where ultraviolet light is applied to the surface of the polycrystalline silicon film by an ultraviolet irradiation lamp 95. Irradiate. The irradiation of the ultraviolet rays has an effect of causing fluorine (F) generated by anisotropic etching to adhere to the surface of the polycrystalline silicon film, so that the fluorine is emitted as radicals from the surface of the polycrystalline silicon film.

Next, the semiconductor wafer 100 is transferred to the transfer chamber 91.
Are sequentially transported to the first reaction chamber 93 and the second reaction chamber 94 respectively through the first reaction chamber 93 and the second reaction chamber 9.
4, a silicon nitride film or the like is deposited on the surface of the polycrystalline silicon film.

Then, the semiconductor wafer 1 for which the processing has been completed
Reference numeral 00 denotes a loader / unloader chamber 90 with a transfer chamber 91 interposed.
Is stored in.

As described above, in the (39-24) film deposition method for depositing an insulating film or a conductive film on the polycrystalline silicon film (or the surface of the semiconductor wafer 100) deposited on the surface of the semiconductor wafer 100, the vacuum system And the semiconductor wafer 10
Cleaning the surface of the polycrystalline silicon film on the surface of No. 0 in the pretreatment chamber 92, exposing the surface of the polycrystalline silicon film, and forming the surface of the polycrystalline silicon film in the same vacuum system as the cleaning step. Depositing an insulating film or a conductive film in the first reaction chamber 93 or the second reaction chamber 94. With this configuration, after removing the natural silicon oxide film formed on the surface of the polycrystalline silicon film in a cleaning step, depositing an insulating film or a conductive film on the surface of the polycrystalline silicon film without contacting the atmosphere. Therefore, the natural silicon oxide film is not interposed between the surface of the polycrystalline silicon film and the insulating film or the conductive film. As a result, the thickness of the surface of the polycrystalline silicon film and the thickness of the insulating film deposited on the surface, for example, the silicon nitride film 36A of the dielectric film 36 can be reduced by an amount corresponding to the natural silicon oxide film. The amount of charge stored in the information storage capacitor C having a stacked structure can be increased. In addition, conduction between the surface of the polycrystalline silicon film and the conductive film deposited on the surface can be ensured.

Also, (40-25) semiconductor wafer 100
In the film deposition method for depositing an insulating film on the surface of the polycrystalline silicon film (or the semiconductor wafer 100) on the surface of the semiconductor wafer 100, a method of using a halogen compound on the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100 in a vacuum system. Cleaning by anisotropic etching to expose the surface of the polycrystalline silicon film; irradiating the exposed surface of the polycrystalline silicon film with ultraviolet rays in the same vacuum system as the cleaning step; Depositing the insulating film (for example, a silicon nitride film) on the surface of the polycrystalline silicon film in the same vacuum system. According to this configuration, when the surface of the polycrystalline silicon film is cleaned, radicals of a halogen element adhering to the surface can be removed by the ultraviolet light, so that an insulating film deposited on the surface of the polycrystalline silicon film, for example, An increase in leak current and a change in etching rate of the silicon nitride film can be reduced.

(Embodiment 5) The present embodiment 5 is directed to the information storage capacitor C having the stacked structure of the memory cell M of the DRAM 1 of the embodiment 1 described above.
Fifth Preferred Embodiment A fifth preferred embodiment of the present invention, which describes the fifth preferred forming method and the preferred embodiment.

The single-wafer type CV according to the fifth embodiment of the present invention.
Method D is shown in FIG. 65 (a time chart showing the opening and closing operation of the source gas valve of the CVD apparatus) and FIG. 66 (a time chart showing the flow rate of the source gas).

As described above, the lower electrode layer 35 of the information storage capacitance element C of the stacked structure of the memory cell M of the DRAM 1 of the first embodiment is formed with a large film thickness in order to increase the charge storage amount. ing. When the lower electrode layer 35 has a large thickness, it is difficult to introduce an n-type impurity for reducing the resistance value. However, in the fifth embodiment, a technique of depositing a polycrystalline silicon film into which the n-type impurity is introduced is a so-called technique. The lower electrode layer 35 is formed by using a doped polysilicon technology.

Normally, a polycrystalline silicon film to which an n-type impurity is not introduced, which is deposited by the CVD method, has a high step coverage at the step portion of the base. However, when the film thickness is large, the introduction of the n-type impurity after the deposition is difficult. difficult. On the other hand, a polycrystalline silicon film into which an n-type impurity deposited by a CVD method is introduced
Although the introduction of the type impurity is simple, the step coverage is poor at the step portion of the base. Therefore, the fifth embodiment
In this method, a polycrystalline silicon film into which an n-type impurity has not been introduced and a polycrystalline silicon film into which an n-type impurity has been introduced are alternately laminated to improve step coverage at a step portion of a base. After depositing each polycrystalline silicon film, a heat treatment is performed to introduce an n-type impurity from the polycrystalline silicon film into which the n-type impurity has been introduced to the polycrystalline silicon film into which the n-type impurity has not been introduced.

FIG. 65 shows the opening / closing operation of a control valve arranged in the source gas supply pipe of the CVD apparatus. As the source gas, an inorganic silane (SiH ₄ or Si ₂ H ₆ ) gas and a phosphine (PH ₃ ) gas are used. FIG. 65 shows a valve for controlling the supply of the inorganic silane gas in the source gas.
As shown in (A), it is opened for a certain time to reach a predetermined film thickness. On the other hand, the control valve for supplying the phosphine gas periodically repeats the opening / closing operation when the control valve for the inorganic silane gas is opened as shown in FIG. FIG. 66A shows the flow rate of the inorganic silane gas whose supply is controlled by the control valve, and FIG. 66B shows the flow rate of the phosphine gas. The intermittent supply of the phosphine gas can also be controlled by raising or lowering the set value of the mass flow controller. The intermittent switching of the phosphine gas by the control valve or the mass flow controller can be performed at a high speed of about 1 to 2 seconds.

As shown in FIG. 67 (schematic diagram of a single wafer type CVD apparatus), a source gas (PH ₃ ) supply pipe 9 is provided.
A stop valve 93j may be provided in the vicinity of the reaction chamber 93 (or 94) of 3a, and the stop valve 93j may supply a source gas to the reaction chamber 93 and the vacuum pump 93i at high speed. The CVD apparatus shown in FIG. 67 can perform intermittent switching of the supply of phosphine gas in about 0.1 [second].

As described above, the polycrystalline silicon film (for example, the lower electrode layer 3) is formed on the base surface having the (43-26) step shape.
5) In the film deposition method for depositing, a polycrystalline silicon film containing an n-type impurity for reducing a resistance value and a polycrystalline silicon film containing no n-type impurity are alternately formed on the base surface by a plurality of layers. Depositing and heat-treating the laminated polycrystalline silicon film to diffuse the n-type impurity from the n-type impurity-containing polycrystalline silicon film to the n-type impurity-free polycrystalline silicon film. Is provided. With this configuration, in the step-shaped region of the base surface, the step coverage of the polycrystalline silicon film containing the n-type impurity can be supplemented by the polycrystalline silicon film containing no n-type impurity. The n-type impurity can be diffused from the polycrystalline silicon film containing the n-type impurity to the polycrystalline silicon film not containing the n-type impurity while the film thickness can be made uniform. A thick film thickness can be ensured while making the impurity concentration of the polycrystalline silicon film uniform.

(44-27) In a film deposition method for depositing a polycrystalline silicon film on an undersurface having a stepped shape, an inorganic silane gas is flowed at a constant flow rate into a vacuum system for depositing the polycrystalline silicon film. Depositing a polycrystalline silicon film containing no impurities based on thermal decomposition, and periodically increasing or decreasing the flow rate in the vacuum system to flow a phosphine gas, and periodically depositing n on the deposited polycrystalline silicon film. Type impurity (P) is contained. With this configuration, the polycrystalline silicon film containing the n-type impurity and the polycrystalline silicon film not containing the n-type impurity can be successively deposited in the same vacuum system. Time can be reduced. That is, the throughput of the DRAM 1 can be improved.

(Embodiment 6) Embodiment 6 is a sixth embodiment of the present invention in which the step of setting the threshold voltage of the MISFET is reduced in the method of manufacturing the DRAM 1 described above.

A method of manufacturing DRAM 1 according to the sixth embodiment of the present invention will be briefly described with reference to FIGS. 68 to 71 (cross-sectional views showing main parts in respective manufacturing steps).

The sixth embodiment is different from the first embodiment in that
The threshold voltages of the six MISFETs used in the RAM 1 are set. That is, as the n-channel MISFET, the MISFET Qs for selecting the memory cell of the memory cell M,
N-channel MISFET Q having a standard threshold voltage
n, n-channel MISFET Q having low threshold voltage
n. The p-channel MISFET includes a p-channel MISFET Qp having a standard threshold voltage, a p-channel MISFET Qp having a low threshold voltage, and a p-channel MISFET Qp having a high threshold voltage.

The memory cell selecting MISFET Qs
(Formed in region I in a manufacturing method described later) is n
The channel MISFET is set to the highest threshold voltage. That is, the memory cell selecting MISFE
In the TQs, in the memory cell array 11E, the p-type semiconductor region 25B is formed in the main surface portion of the p − -type well region 22, so that the impurity concentration on the surface is increased and the threshold voltage is set high. Specifically, the memory cell selection MI
When the gate length dimension of the SFET Qs is 0.8 [μm], the threshold voltage is set to 0.8 [V].

The n-channel MISFET Qn having the standard threshold voltage (formed in the region III) is used in most of the peripheral circuits except the sense amplifier circuit (SA) 13, that is, in the region operated at the low power supply voltage Vcc. ing. N-channel MISFET Q having this standard threshold voltage
For n, when the gate length is formed at 0.8 [μm], the threshold voltage is set to 0.5 [V].

The n-channel M having the low threshold voltage
The ISFET Qn (formed in the region II) is mainly used in each of the sense amplifier circuit 13 and the output buffer circuit 1702. The n-channel MISFET Qn having the low threshold voltage has a long gate length in order to reduce a variation in threshold voltage due to a variation in processing of the gate electrode 27, particularly a change in the gate length. The sense amplifier circuit 13 has a problem that the sensitivity at the time of information determination is reduced when the gate length dimension is increased.
The threshold voltage of Qn is lowered. In addition, the output buffer circuit 1702 has the n-channel MISFET Q
The threshold voltage of n is set low. The n-channel MISFET Qn having this low threshold voltage has a gate length of 1.4 [μm] and a threshold voltage of 0.5 [V].
Is set to That is, the n-channel MISFET Qn having a low threshold voltage has a gate length of 0.8 [μ].
m], the threshold voltage is set to 0.3 [V].

On the other hand, the p-channel MISFET Qp having the standard threshold voltage (formed in the region IV) is used in most of the peripheral circuits except the sense amplifier circuit 13, that is, in the region operated at the low power supply voltage Vcc. I have. P-channel MISFET Qp having this standard threshold voltage
Sets the threshold voltage to -0.5 [V] when the gate length is formed at 0.8 [μm].

The p-channel M having the low threshold voltage
ISFET Qp (formed in region V) is used in sense amplifier circuit 13. The p-channel MISFET Qp having a low threshold voltage is connected to the reference potential of each of the reference voltage generating circuits of the VCC limiter circuit 1804 and the VDL limiter circuit 1810 (the low power supply voltage Vcc of about 3.
It is used as one p-channel MISFET Qp that forms a reference potential of -1.0 [V] for forming 3 [V]. The p-channel MISFET Qp having a low threshold voltage used as the sense amplifier circuit 13 has a gate length of 1.4 [μm] and a threshold voltage of -0.5.
[V] (threshold voltage is low in absolute value).
That is, a p-channel MISFE having a low threshold voltage
When the gate length is converted back to 0.8 [μm], the threshold voltage of TQp is set to −0.2 [V]. On the other hand, the p-channel MISFET Qp having a low threshold voltage used in the reference voltage generating circuit has a gate length of 8 [μm] and a threshold voltage of -0.6 [V].
Is set to That is, the p-channel MISFET Qp having a low threshold voltage has a gate length of 0.8 [μ].
m], the threshold voltage is set to -0.2 [V].

The p-channel M having the high threshold voltage
ISFET Qp (formed in region VI) is the other p-channel MIS that forms the reference potential of the reference voltage generation circuit.
Used as FET Qp. P-channel MISF having a high threshold voltage used in this reference voltage generating circuit
ETQp has a gate length of 8 [μm] and a threshold voltage of -1.6 [V] (the threshold voltage is high in absolute value). That is, the p-channel MISFET Qp having a high threshold voltage has a gate length of 0.8 [μ].
m], the threshold voltage is set to -1.2 [V].

Next, each MISFE of the DRAM 1
A method for forming T will be briefly described.

First, similarly to the method of manufacturing DRAM 1 of the first embodiment, n-type semiconductor substrate 20 has n
Each of the − well region 21 and the p − well region 22 is formed, and thereafter, an insulating film for element isolation 23, a p-type channel stopper region 24, a p-type channel stopper region 25 A,
Each of the p-type semiconductor regions 25B is sequentially formed. This formed state is shown in FIG. Since the DRAM 1 is highly integrated, the separation dimension between the p-channel MISFETs Qp is reduced and the separation capability is reduced, so that the impurity concentration of the n − -type well region 21 is set slightly higher. Specifically, n
The type well region 21 is, for example, 1 × 10 ^{13 to} 3 × 10 ¹³ [a
The impurity concentration is set to about toms / cm ² ]. The impurity concentration of n-type well region 21 can set a high threshold voltage (absolute value) of p channel MISFET Qp formed in region VI. On the other hand, the DRAM 1 has an n-channel MISF having a standard threshold voltage due to high integration.
Since the gate length dimension of the ETQn is reduced, the substrate effect constant decreases, and the impurity concentration of the p − -type well region 22 can be set slightly higher to suppress the short channel effect. Specifically, the p− type well region 22 is, for example, 7 × 1
The impurity concentration is set to about 0 ^{12 to} 9 × 10 ¹² [atoms / cm ² ]. The impurity concentration of the p-type well region 22 is the region II
Can be set to a low threshold voltage of the n-channel MISFET Qn. Further, the high threshold voltage of the memory cell selecting MISFET Qs in the region I can be set by the impurity concentration of the p − -type well region 22 and the rise of the impurity from the p-type semiconductor region 25B.

Next, as shown in FIG. 69, p
N-type MISFET Qn
Set the standard threshold voltage of The p-type impurity 22p is
For example, B is used at an impurity concentration of about 1 × 10 ^{12 to} 2 × 10 ¹² [atoms / cm ² ] and is introduced by ion implantation at an energy of about 15 to 25 [KeV]. When introducing the p-type impurity 22p, an impurity introduction mask (for example, a photoresist film) 110 shown in FIG. 69 is used.

[0316] Next, as shown in FIG. 70, by introducing a p-type impurity 21p ₁ in the region IV, p-channel MISFETQp
Set the standard threshold voltage of p-type impurity 21p
₁ is, for example, 2.0 × 10 ^{12 to} 2.2 × 10 ¹² [atoms / c
m ² ] with an impurity concentration of about 15 to 25 [KeV].
It is introduced by an ion implantation method of about energy. Upon introduction of the p-type impurity 21p ₁ uses impurity introduction mask (e.g. photoresist film) 111 shown in FIG 70.

Next, as shown in FIG. 71, a p-type impurity 21p ₂ is introduced into region V, and p-channel MISFET Qp
Set the low threshold voltage of This p-type impurity 21p ₂
Is, for example, 2.4 × 10 ^{12 to} 2.6 × 10 ¹² [atoms / cm ² ]
The impurity is implanted by ion implantation using B having an impurity concentration of about 15 to 25 [KeV]. At the time of the introduction of the p-type impurity 21p ₂ using the impurity introduction mask (e.g. photoresist film) 112 shown in FIG 70.

The order of introducing the above-described threshold voltage adjusting impurities is not limited to this, and any of them may be introduced first or later.

As described above, the (35-20) complementary MIS
In the DRAM 1 having the FET, the n-channel MIS
In the impurity concentration that sets the low threshold voltage of the FET Qn, p
Forming each of the n-type well region 21 and the n-type well region 21 on the main surface of a different region of the p-type semiconductor substrate 20 with an impurity concentration that sets a high threshold voltage (absolute value) of the p-channel MISFET Qp. And a p-type impurity 22p for adjusting a threshold voltage on the main surface of the p-type well region 22.
To set the standard threshold voltage of the n-channel MISFET Qn, and to add a threshold voltage adjusting impurity 21p ₁ (or 21) to the main surface of the n − -type well region 21.
p ₂ ) and setting a standard (or low absolute) threshold voltage of the p-channel MISFET. With this configuration, the low threshold voltage of the n-channel MISFET is set by the impurity concentration of the p − -type well region 22, and the high threshold voltage of the p-channel MISFET Qp is set by the impurity concentration of the n − -type well region 21. The threshold voltage can be set by setting the threshold voltage of the four types twice by introducing the threshold voltage adjusting p-type impurities 22p and 21p ₁ (or 21p ₂ ) _twice. It is possible to reduce the number of steps of introducing the value voltage adjusting impurity.

(36-21) The n-type well region 21 and the p-type well region 22 are formed on the main surface of the p-type semiconductor substrate 20 in a self-aligned manner. With this configuration, there is no need to perform a step of exposing the surface of the p − -type semiconductor substrate 20 except for the n − -type well region 21 and the p − -type well region 22. Can be reduced.

(37-22) DRAM 1 provided with p-channel MISFET Qp for generating a reference voltage and p-channel MISFET Qp having a standard threshold voltage
, A p-channel MIS for generating the reference voltage
Forming the n − -type well region 21 with an impurity concentration that sets a high threshold voltage (high in absolute value) of the FET Qp; Introduce 21p ₁ (or 21p ₂ )
a step of setting a standard threshold voltage (or a low threshold voltage) of the p-channel MISFET Qp;
1p ₂ (or 21p ₁ ) is introduced and p-channel MISFE
Setting a low threshold voltage (or a standard threshold voltage) of TQp. With this configuration, the low threshold voltage of the p-channel MISFET Qp that generates the reference voltage can be set by the impurity concentration of the n − -type well region 21, and the setting of three types of threshold voltages is performed twice. Since the threshold voltage adjusting impurities 21p ₁ and 21p ₂ can be introduced by the introduction thereof, the number of steps of introducing the threshold voltage adjusting impurities can be reduced.

(Embodiment 7) Embodiment 7
This is a seventh embodiment of the present invention in which the amount of charge stored in the information storage capacitive element C of the stacked structure of the memory cell M in the DRAM 1 of the first embodiment is increased.

A DRAM 1 according to a seventh embodiment of the present invention
72 (a plan view of a main part of the memory cell array in a predetermined manufacturing process).

As shown in FIG. 72, in the memory cell M of the DRAM 1 according to the seventh embodiment, a groove 35g is provided in the lower electrode layer 35 of the information storage capacitor C having a stacked structure. That is, the information storage capacitance element C having a stacked structure
Since the surface area can be increased in the height direction by the inner wall of the groove 35g of the lower electrode layer 35, the charge storage amount can be improved. This groove 35g is provided with a word line (W
L) It is configured to cross the lower electrode layer 35 in the direction in which the 27 extends.

Next, a method of forming the information storage capacitance element C having the stacked structure of the memory cell M will be briefly described with reference to FIGS. 73 to 76 (a cross-sectional view of a main portion in each manufacturing process).

First, similarly to the method of manufacturing DRAM 1 of the first embodiment, memory cell selecting memory cell M
After forming the ISFET Qs, an interlayer insulating film 33 is formed as shown in FIG.

Next, as shown in FIG. 74, a polycrystalline silicon film 35B is formed on the entire surface of the substrate including on the interlayer insulating film 33. The polycrystalline silicon film 35B is formed to have a large thickness as described above, and an n-type impurity for reducing a resistance value is introduced. For the introduction of the n-type impurity, the method described in the first embodiment in which the polycrystalline silicon film is divided and a plurality of layers are deposited, and the n-type impurity is introduced by a thermal diffusion method for each deposition is adopted. Further, for the introduction of the n-type impurity, each of the polycrystalline silicon film into which the n-type impurity is not introduced and the polycrystalline silicon film into which the n-type impurity is introduced as described in the fifth embodiment are alternately formed. A method of laminating and then performing a heat treatment is adopted.

Next, as shown in FIG. 75, at the connection between the memory cell selecting MISFET Qs and the lower electrode layer 35 of the stacked information storage capacitor C, the polycrystalline silicon film 35B and the interlayer insulating film 33 are formed. Remove each one in turn,
A groove 35g is formed. The groove 35g is formed by, for example, anisotropic etching. By forming this groove 35g,
The surface of the other n-type semiconductor region 29 of the memory cell selecting MISFET Qs is exposed.

Next, the polycrystalline silicon film 3 including the surface of the inner wall of the groove 35g and the exposed surface of the n-type semiconductor region 29 is formed.
A polycrystalline silicon film 35C is formed on the entire surface of 5B. This polycrystalline silicon film 35C is formed with a small thickness (thickness that can secure a step shape) so as not to fill the trench 35g. An n-type impurity is introduced into the polycrystalline silicon film 35C, and the n-type impurity is introduced at a lower impurity concentration than the polycrystalline silicon film 35B in order to reduce the short channel effect of the memory cell selecting MISFET Qs.

Next, as shown in FIG. 76, each of the polycrystalline silicon films 35C and 35B is sequentially patterned to form a lower electrode layer 35. Since the manufacturing method thereafter is the same as the manufacturing method of the DRAM 1 of the first embodiment in terms of the embodiment, the description is omitted here.

As described above, in the information storage capacitive element C of the stacked structure of the memory cell M of the DRAM 1, the groove 35g is provided in the lower electrode layer 35, whereby the groove 35g is formed.
The charge accumulation amount can be improved by an amount corresponding to g.

As shown in FIG. 77 (a plan view of a main part of a memory cell in a predetermined manufacturing process), the lower electrode layer 35 of the information storage capacitive element C having the stacked structure has a complementary data line (DL). A groove 35g that crosses in the direction in which 50 extends may be provided. Since the DRAM 1 of the seventh embodiment employs the folded bit line method, the interval between the lower electrode layers 35 in the extending direction of the word lines 27 is small, and the lower electrode layers 35 are connected to the complementary data lines 50. Are formed in a rectangular shape that is long in the extending direction. Therefore, the groove 3
The increase in the surface area of the lower electrode layer 35 by 5 g is larger than that described above.

The method of forming the information storage capacitive element C having the stacked structure shown in FIG. 77 will be described with reference to FIGS.
0 (a cross-sectional view of a main part shown for each manufacturing process).

[0334] First, as shown in FIG.
A polycrystalline silicon film 35B is formed on the entire surface of the substrate including the substrate 3 above.

Next, as shown in FIG. 79, a groove 35g is formed in the polycrystalline silicon film 35B.

Next, a polycrystalline silicon film 35C is formed on the polycrystalline silicon film 35B, and the polycrystalline silicon films 35C and 35C are formed.
By patterning each of B, the lower electrode layer 35 can be formed as shown in FIG.

The lower electrode layer 35 of the information storage capacitor C having the stacked structure described with reference to FIGS. 72 to 76 is shown in FIGS. 81 to 84 (a cross-sectional view of a main portion in each manufacturing process). Thus, the charge storage amount can be further improved.

First, after forming a polycrystalline silicon film 35B as shown in FIG. 81, a groove 35g is formed as shown in FIG.

Next, as shown in FIG. 83, the polycrystalline silicon film 35B is patterned into the shape of the lower electrode layer 35 in advance, and a groove 35g is formed.

Next, a polycrystalline silicon film 35C is formed on the entire surface of the substrate including the surface of the inner wall of the groove 35g, the surface of the polycrystalline silicon film 35B, and the exposed surface of the n-type semiconductor region 29.

Next, the lower electrode layer 35 is formed by patterning the polycrystalline silicon film 35C by anisotropic etching. The lower electrode layer 35 can improve the charge storage amount in the same manner as described above by the groove 35g, and can leave the polycrystalline silicon film 35C on the outer peripheral side wall of the polycrystalline silicon film 35B of the lower electrode layer 35. So you can
An amount corresponding to the film thickness of the remaining polycrystalline silicon film 35C,
Further, the charge storage amount can be improved.

Similarly, the lower electrode layer 35 of the information storage capacitance element C having the stacked structure described with reference to FIGS. 77 to 80 is shown in FIGS. 85 to 88 (a cross-sectional view of a main portion in each manufacturing process). As shown, the charge storage amount can be further improved.

First, after forming a polycrystalline silicon film 35B as shown in FIG. 85, a groove 35g is formed as shown in FIG.

Next, as shown in FIG. 87, the polycrystalline silicon film 35B is patterned into the shape of the lower electrode layer 35 in advance.

Next, a polycrystalline silicon film 35C is formed on the entire surface of the substrate including the surface of the inner wall of the groove 35g, the surface of the polycrystalline silicon film 35B, and the exposed surface of the n-type semiconductor region 29.

Next, the lower electrode layer 35 is formed by patterning the polycrystalline silicon film 35C by anisotropic etching. The lower electrode layer 35 is formed of a polycrystalline silicon film 35.
Since the polycrystalline silicon film 35C can be left on the outer peripheral side wall of B, the charge storage amount can be further improved by an amount corresponding to the thickness of the remaining polycrystalline silicon film 35C.

(Eighth Embodiment) An eighth embodiment of the present invention is directed to a method of manufacturing the DRAM 1 according to the first embodiment in which the amount of mask alignment (alignment) is reduced and the degree of integration is improved. There are eight embodiments.

In the manufacturing process of DRAM 1 according to the eighth embodiment of the present invention, the alignment relationship is shown in FIG. 89 (alignment tree diagram).

In the manufacturing process of the DRAM 1 of the first embodiment, an upper layer pattern is aligned (position is adjusted) with a lower layer pattern. FIG.
(A) shows an alignment relationship in the X direction (for example, the extending direction of the word line). DRAM 1 of Embodiment 8
Is based on the n-type well region 21 as a reference for alignment. The element isolation insulating film 23 is formed in the n− type well region 2.
1 is aligned in the X direction. The gate electrode (word line) 27 is aligned in the X direction with the element isolation insulating film 23. The gate electrode 27 serves as a reference for alignment of the upper layer. Each of the lower electrode layer 35, the upper electrode layer 37, and the connection hole 40A of the information storage capacitor C having the stacked structure is connected to the gate electrode 27.
Are aligned in the X direction.

On the other hand, FIG. 89B shows the alignment relationship in the Y direction (for example, the direction in which the complementary data lines extend). The DRAM 1 of the eighth embodiment performs alignment in two directions, that is, an X direction and a Y direction. Similarly,
The n − -type well region 21 is used as a reference for alignment, and the element isolation insulating film 23 performs alignment in the Y direction with respect to the n − -type well region 21. The gate electrode 27 performs alignment in the Y direction with respect to the element isolation insulating film 23. Unlike the alignment in the X direction, the lower electrode layer 35 performs the alignment in the Y direction with respect to the element isolation insulating film 23. Upper electrode layer 37, connection hole 4
Each of 0A is aligned with the gate electrode 27 in the Y direction.

If the lower electrode layer 35 of the information storage capacitor C having the stacked structure has a large misalignment with respect to the inter-element isolation insulating film 23, the other n-type semiconductor region 29 of the memory cell selection MISFET Qs A hole is formed in the connection hole 34 connecting the electrode and the lower electrode layer 35 (see FIG. 1). This opening causes the surface of the n-type semiconductor region 29 exposed from the inside of the connection hole 34 to be etched when the lower electrode layer 35 is processed. Therefore, it is necessary to minimize the amount of misalignment of the lower electrode layer 35 with respect to the element isolation insulating film 23.

When the lower electrode layer 35 is simply aligned in the X and Y directions with respect to the gate electrode 27 as a lower layer, the gap between the element isolation insulating film 23 and the gate electrode 27 is reduced. Since the respective amounts of misalignment σ between the gate electrode 27 and the lower electrode layer 35 are generated, the amount of misalignment of the lower electrode layer 35 with respect to the isolation insulating film 23 is 1.4σ.

Therefore, in the eighth embodiment, as shown in FIG. 89 (A), the lower electrode layer 35 is in the X direction (or Y direction) with respect to the gate electrode 27 which is a pattern one layer below.
Then, as shown in FIG. 89 (B), alignment in the Y direction (or X direction) is performed on the inter-element isolation insulating film 23 which is a two-layer lower pattern. That is,
Lower electrode layer 3 of information storage capacitor C having a stacked structure
Reference numeral 5 denotes a gate electrode 2 for the device isolation insulating film 23;
7, only the misalignment amount σ occurs. Since the lower electrode layer 35 does not serve as a reference for alignment of the upper layer, alignment can be performed over different layers as described above.

As described above, in the (46-28) alignment method for aligning three different patterns of the element isolation insulating film 23, the gate electrode 27, and the lower electrode layer 35 in the X direction and the Y direction, Electrode (second
The lower layer electrode layer (third layer pattern) 27 formed on the gate electrode 27 is aligned in the X direction and the Y direction with respect to the underlying element isolation insulating film (first layer pattern) 23. The (layer pattern) 35 is aligned in the X direction (or Y direction) with respect to the gate electrode 27 in the lower layer, and is further aligned in the Y direction (or X direction) with respect to the lower layer isolation insulating film 23. With this configuration, the device isolation insulating film 23 and the gate electrode 27 are formed.
Respectively, and the amount of alignment shift between the inter-element isolation insulating film 23 and the lower electrode layer 35 can be made substantially the same. The amount of misalignment with the lower electrode layer 35 can be reduced. As a result, the degree of integration of the DRAM 1 can be improved by an amount corresponding to the mask alignment allowance in the manufacturing process. Further, as described above, there is no aperture in the connection hole 34 connecting the other n-type semiconductor region 29 of the memory cell selection MISFET Qs and the lower electrode layer 35.

(Embodiment 9) This embodiment 9 relates to a preferred method of forming a target mark when performing the alignment method described in the embodiment 8 in the DRAM 1 of the embodiment 1 described above. Explain the ninth aspect of the present invention.
It is an embodiment.

A structure of a target mark portion of DRAM 1 according to the ninth embodiment is shown in FIG.

As shown in FIG. 90, the target mark T
M includes a connection hole 53D formed in the interlayer insulating film 53 of the DRAM 1 and a wiring 55 formed on the interlayer insulating film 53. In the semiconductor wafer state, the target mark TM is a scribe area between the formation regions of the respective DRAMs 1, the inside of the formation region of the DRAM 1, or the dummy DRA.
M1 (not used as DRAM but used as a target mark for alignment) is arranged in the formation area.

The target mark TM can be formed by forming a connection hole 53D in a region where the wiring (transition metal film) 52 is not formed on the interlayer insulating film 51. Since the wiring 52 does not exist in the lower layer inside the connection hole 53D, the transition metal film 54 for embedding is not deposited by the selective CVD method, and the wiring 55 is formed by using the aluminum alloy film 55B having poor step coverage. Therefore, a stepped shape is formed on the surface of the wiring 55 by the stepped shape of the connection hole 53D. This step shape is used as the target mark TM.

As described above, the get mark TM is expressed by D
Since the step of forming the connection hole 53D and the step of forming the wiring 55 in the manufacturing process of the RAM 1 can be used in combination, the number of manufacturing processes can be reduced.

(Embodiment 10) Embodiment 10
In the method for manufacturing the DRAM 1 according to the first embodiment,
This is a tenth embodiment of the present invention in which the depth of focus and the resolution at the time of exposure of the photolithography technique are improved.

The DRAM 1 according to the tenth embodiment of the present invention
91 (conceptual diagram) and FIG. 92 (process flow diagram) show respective steps of the photolithography technique used in the manufacturing process of FIG.

[0362] photolithography of the tenth embodiment, FLEX (F ocus L atitudeenhancement Ex pos
ure) method and the CEL (C ontrast E nhancement L ithogr
The depth of focus and resolution of the photoresist film during exposure are improved by using the aphy) method. The procedure of the exposure processing of this photolithography technique is as follows.

As shown in FIGS. 91 and 92, first, a photoresist film 120 is applied to the semiconductor wafer 100 (1).

Next, a photochromic CEL material 121A is dropped on the surface of the photoresist film 120 applied to the semiconductor wafer 100, and the photochromic CEL film 121 is applied (2). Photochromic CEL film 1
As the 21, for example, a nitrone is used as shown in FIG. 93 (structural formula). This photochromic CEL film 121
As shown in FIG. 94 (a diagram showing transmittance with respect to exposure), has a property of being transparent (bleaching) when light irradiation of a certain amount or more is performed (irradiation start t ₁ ). Further, the photochromic CEL film 121 has a property of gradually becoming opaque when light irradiation is stopped (irradiation end t ₂ ). Moreover, these properties have repetitive properties.

Next, in the projection exposure apparatus, the pattern of the reticle 125 is transferred to the photoresist film 120 applied on the surface of the semiconductor wafer 100, with the projection optical system 124 and the photochromic CEL film 121 interposed. 3). This exposure is performed by using the FLEX method while superimposing a pattern while changing the depth of focus.

FIG. 95 shows a photochromic CEL film 121.
To line and space pattern depending on presence or absence of
5 shows the difference in the depth of focus when the LEX method is applied. FIG. 95 (A)
Shows a light intensity profile at the time of exposure on the surface (in the photoresist film 120) of the semiconductor wafer 100 in a line and space pattern. As shown in FIG. 95 (A), light is applied to a portion of the reticle 125 corresponding to a position where the chrome pattern 125A does not exist, the light intensity at the focal position (0 [μm]) is maximum, As the light shifts, the light intensity decreases.

FIG. 95B shows the relationship between the light intensity profile and the characteristics of the photochromic CEL film 121 when the FLEX method is applied and the surface of the semiconductor wafer 100 is stepped up and down to increase the depth of focus. Is shown. FIG. 9
In FIG. 5 (B), the surface of the semiconductor wafer 100 is set at 0.
When the light intensity is increased by 5 [μm], the light intensity at the deep position of the photoresist film 120 increases (a). When the light intensity reaches a certain amount for making the photochromic CEL film 121 transparent, (b) the photoresist film 120 is irradiated with light exceeding the certain amount. When the light intensity is equal to or less than a predetermined amount, that is, at a shallow position of the photoresist film 120, light irradiation is blocked by the photochromic CEL film 121.
Next, in FIG. 95 (B), the semiconductor wafer 100
Is lowered by 0.5 [μm], (c) the light intensity increases at the shallow position of the photoresist film 120. When the light intensity reaches a certain amount for making the photochromic CEL film 121 transparent, (d) the photoresist film 120 is irradiated with light in an amount exceeding the certain amount. When the light intensity is equal to or less than a predetermined amount, that is, at a deep position of the photoresist film 120, light irradiation is blocked by the photochromic CEL film 121.

FIG. 95 (C) shows the total light intensity profile of the two light irradiations to which the FLEX method shown in FIG. 95 (B) is applied, and (a + b) shows the photochromic CEL.
When there is no film 121, (a × b + c × d) is when there is a photochromic CEL film 121. In the case where the former photochromic CEL film 121 is not provided, when the FLEX method is applied to the line-and-space pattern, the light intensity profile exceeds the dissolution level of the photoresist film 120 in the non-exposed portion, thereby improving the depth of focus. Is not preferred. In contrast, when the latter photochromic CEL film 121 is provided, the photochromic CEL film 121 is formed.
By improving the bleaching effect of the EL film 121 and changing the focal position by the FLEX method, it is possible to improve the resolution and the depth of focus.

After the exposure process shown in FIGS. 91 and 92, the photochromic CEL film 12 is
1 is removed (4), and the photoresist film 120 is developed with a developing solution 123 (5).

As shown in FIG. 91, a photochromic CEL film 121B may be used instead of the step of applying the photochromic CEL film 121.
This photochromic CEL film 121A is a photoresist film 1 applied to the surface of the semiconductor wafer 100.
Press against the surface of No. 20 for use.

As described above, in the photolithography technique, by using the FLEX method and the CEL method,
High resolution and high depth of focus of the pattern can be obtained.

(Embodiment 11) Embodiment 11
This is an eleventh embodiment of the present invention in which the alignment accuracy of each layer is improved in the manufacturing process of the DRAM 1 according to the first embodiment.

The DRAM 1 according to the eleventh embodiment of the present invention
96 (schematic plan view) shows the configuration of the semiconductor wafer 100 before the dicing step.

As shown in FIG. 96, the semiconductor wafer 10
Reference numeral 0 indicates that a plurality of DRAMs 1 are arranged in a matrix before the dicing step (before being formed into a pellet). A scribe area (not shown) is provided between each DRAM 1. As shown in FIG. 97 (enlarged plan view of part A in FIG. 96) and FIG. 98 (enlarged plan view of part B in FIG. 97),
DRAMs (α to α) adjacent to each other on the semiconductor wafer 100
In the scribe area between ε) 1, target marks TM shared by adjacent DRAMs 1 are arranged. The target mark TM serves as a reference for positioning at the time of alignment in a reduction projection exposure apparatus, for example.
As shown in FIGS. 97 and 98, the adjacent DRAM 1
Target mark T shared between the two, for example, between β-γ
M is arranged so that it can be detected by one scanning of the alignment beam AB in the X direction. FIGS. 97 and 98 also show the waveform of the alignment signal S when the target mark TM is detected by scanning with the alignment beam AB. Based on this alignment signal,
97, the center position Xβ in the X direction, the center position Yβ in the Y direction, and the rotation amount Wβ of the DRAM (β) 1 can be calculated by the following equations.

[0375]

(Equation 2)

In the alignment of the eleventh embodiment, the DRA of the first layer arranged on the surface of the semiconductor wafer 100 is used.
When the pattern (pellet pattern) of the DRAM 1 of the second layer is arranged with respect to the pattern (pellet pattern) of M1, the position of the target mark TM of the pattern of the DRAM 1 of the first layer is detected by the alignment beam AB and the position is detected. Is calculated, and the position deviation between the patterns of the adjacent second-layer DRAM 1 is corrected so as to be small.
This is performed by a method of arranging the pattern of the DRAM 1 of the layer. In other words, an associative alignment method is employed in which the pattern of the second-layer DRAM 1 is associatively aligned with the pattern of the first-layer DRAM 1. This associative alignment method can ensure regularity of mutual arrangement between patterns of the DRAM 1 as compared with the pellet alignment method. The pellet alignment method is a method of repeating alignment and exposure for each pattern of each DRAM 1 on the surface of the semiconductor wafer 100.

In the associative alignment method, even when the target mark TM is detected erroneously largely, a large alignment error is not directly generated, and high alignment accuracy can be obtained.

The associative alignment method can obtain higher alignment accuracy than the multi-point wafer alignment method even when the pattern arrangement of the first-layer DRAM 1 has a large distortion. The multi-point wafer alignment method is a method in which a plurality of target marks TM on the surface of the semiconductor wafer 100 are sampled and aligned, the arrangement of the DRAM 1 is estimated from the results by statistical calculation, and only exposure is performed thereafter.

The associative alignment method is the first type.
Based on the detection of target marks TM arranged on four sides of the pattern of the DRAM 1 of the second layer, the DRAM 1
The rotation amount of the pattern can be calculated and corrected, so that the correction accuracy of the rotation amount is higher than that in a case where two points of the DRAM 1, for example, target marks TM arranged vertically or horizontally are detected and the rotation amount is corrected. Obtainable. Even in the case of the correction of the rotation amount, the associative alignment method does not directly cause a large rotation amount correction error even when one target mark TM is erroneously detected, so that high alignment accuracy can be obtained.

When the above-described pellet alignment method and the multi-point wafer alignment method are mixed, the alignment accuracy generally decreases. However, when the associative alignment method is mixed with any of the methods, a high alignment accuracy can be obtained. it can.

In the associative alignment method, two DRs adjacent to each other are scanned by one scanning of the alignment beam AB.
Since the target mark TM of the pattern of AM1 can be detected, it is possible to obtain a throughput substantially equivalent to that of the pellet alignment method.

FIG. 99 shows a comparison of the alignment accuracy between the associative alignment method, the pellet alignment method, and the multi-point wafer alignment method when the pattern arrangement of the DRAM 1 of the first layer has distortion or rotation. FIG. 99 (A) shows (a) the ideal arrangement of the pattern (1) of the DRAM 1 of the first layer, and (b) the DR of the first layer.
Each of the arrangements when the pattern (1) of AM1 has arrangement distortion and rotation is shown. In the latter pattern (1) of the first-layer DRAM 1, the X coordinates of the respective α to γ do not match, and
The pitch in the Y coordinate direction between β and β-γ is different,
Each of α and γ has a rotation error. The arrangement distortion and the rotation are caused by warpage generated in the semiconductor wafer 100 due to repeated heat treatment and the like.

FIG. 99 (B) shows the case where the pattern (2) of the second-layer DRAM 1 is aligned when the pattern (1) of the first-layer DRAM 1 has the aforementioned arrangement distortion and rotation. The comparison of each alignment method is shown. In either case, the γ pattern (2) of the second-layer DRAM 1 indicates a case where the target mark TM is erroneously detected with respect to the γ pattern (1) of the first-layer DRAM 1. The correction of the rotation amount is calculated based on the detection of four target marks TM in the associative alignment method, and is calculated based on the detection of two target marks TM in the other two alignment methods. Fig. 99
As shown in (B), when there is no rotation amount correction, and when there is rotation amount correction, the associative alignment method has higher alignment accuracy than the other pellet alignment methods and the multipoint wafer alignment method. Can be obtained.

Thus, high alignment accuracy can be obtained by employing the associative alignment method.

(Embodiment 12) Embodiment 12 is directed to
In the DRAM 1 of the first embodiment, the reliability at the connection portion between the transition metal film embedded in the connection hole of the interlayer insulating film by the selective CVD method and the wiring extending on the interlayer insulating film is improved. This is the twelfth embodiment of the present invention.

A DRAM 1 according to a twelfth embodiment of the present invention
100 is shown in FIG.

The DRAM 1 of the twelfth embodiment is similar to that of FIG.
0, the contact holes 5 formed in the interlayer insulating film 51 are formed.
A transition metal film 54 is embedded in each of 1D and 51S, and a wiring 52 extending over the interlayer insulating film 51 is formed in the transition metal film 54.
Is connected.

In the memory cell array 11E, since the memory cell M composed of the memory cell selecting MISFET Qs and the information storage capacitor C having a stacked structure is arranged, the step shape is larger than that of the peripheral circuit region. Become. Therefore, the thickness of the interlayer insulating film 51 in the region of the memory cell array 11E is smaller than that in the region of the peripheral circuit. As shown in FIGS. 100 and 101 (a cross-sectional view of a main part in a predetermined manufacturing process), the depth of the connection hole 51S formed in the region of the memory cell array 11E of the interlayer insulating film 51 is formed shallow, and the region of the peripheral circuit is formed. Connection hole 51 formed in
D is formed deeply.

As the transition metal film 54, a W film deposited by, for example, a selective CVD method is used as in the first embodiment.
In the twelfth embodiment, the wiring 52 uses an aluminum alloy film. Further, the wiring 52 may be formed of a transition metal film such as a W film deposited by a sputtering method or a composite film mainly including the same.

As shown in FIGS. 100 and 101, the transition metal film 54 is formed to such a thickness that the connection hole 51S having a shallow depth in the region of the memory cell array 11E is buried. That is, the transition metal film 54 is configured so as not to protrude from the connection hole 51S based on the connection hole 51S having a shallow depth. When the transition metal film 54 protrudes greatly from the connection hole 51S, the surface of the wiring 52 in the upper layer protrudes, resulting in a variation in the thickness of the photoresist film used for processing the wiring 52 and diffraction during exposure. Due to the phenomenon, the size of the etching mask changes from the set value,
The processing accuracy of the wiring 52 decreases. The connection hole 51
Since the surface of the transition metal film 54 which protrudes greatly from S cannot be covered with the upper wiring 52, the transition metal film 54 is etched more than necessary in the etching step for processing the wiring 52. The transition metal film 54 embedded in the connection hole 51D having a deep depth in the region of the peripheral circuit is formed as shown in FIG.
As shown in FIG. 5, the thickness of the connection hole 51D is such that the aspect ratio does not exceed 1. When the aspect ratio exceeds 1, the step coverage of the wiring 52 in the upper layer decreases, and the wiring 52 frequently breaks at the connection hole 51D.

As described above, the interlayer insulating film 51 is formed on the base surface having the (48-29) step shape, and the region of the interlayer insulating film 51 having a high step shape on the base surface (region of the memory cell array 11E). A shallow connection hole 51S, and a deep connection hole 51D in a low step region (peripheral circuit region), and are connected to the transition metal film 54 embedded in each of the connection hole 51S and the connection hole 51D. As described above, in the DRAM 1 in which the wiring 52 extends on the interlayer insulating film 51, a transition metal film 54 buried in each of the shallow connection hole 51S and the deep connection hole 51D is deposited by a selective CVD method. A film 54 is deposited with a thickness approximately equal to the depth of the shallow connection hole 51S. With this configuration, the transition metal film 54 buried in each of the shallow connection hole 51S and the deep connection hole 51D is formed with the same thickness as the depth of the shallow connection hole 51S, and the shallow connection hole 51S and the deep connection hole 51D are formed. Since the transition metal film 54 does not protrude from each of the above, the processing accuracy of the wiring 52 can be improved and the reliability of the wiring can be improved.

(Embodiment 13) Embodiment 13
This is a thirteenth embodiment of the present invention in which the reliability of the wiring 52 mainly composed of a transition metal film is improved in the DRAM 1 of the first embodiment.

A DRAM 1 according to the thirteenth embodiment of the present invention
102 is shown in FIG.

[0397] As shown in FIG.
In the DRAM 1, a wiring 52 extends on an interlayer insulating film 51. The wiring 52 is formed of a composite film in which a transition metal film 52B of substantially the same metal material is laminated on the transition metal film 52A.

The transition metal film 52A under the wiring 52 is formed of, for example, a W film deposited by a sputtering method.
It is formed with a film thickness of about 120 [nm]. The lower transition metal film 52A has high adhesiveness to the underlying interlayer insulating film (silicon oxide based insulating film) 51. If the thickness of the lower transition metal film 52A is too large, the transition metal film 52A has an overhang shape at the upper part of the step formed by the connection hole 51C, and nests are generated, and the step coverage of the upper transition metal film 52A is increased. Is formed at the above-mentioned thin film thickness. The lower transition metal film 52A is formed as shown in FIG.
As shown in FIG. 03, the relationship between the target voltage and the film stress at the time of sputtering causes separation from the surface of the interlayer insulating film 51, so that film stress does not occur (stress is zero or within an allowable range near the target). Deposit using voltage. Also,
The lower transition metal film 52A has properties substantially equal to the etching rate of the upper transition metal film 52B. The lower transition metal film 52A has higher corrosion resistance than the TiN film and the like, and has a small work function difference from Si, so that the contact resistance value can be reduced.

The transition metal film 52B above the wiring 52
Is formed of a W film deposited by the CVD method.
It is formed with a film thickness of about 0 to 350 [nm]. The upper transition metal film 52 </ b> A reduces the substantial resistance value of the wiring 52 and is configured as a main component of the wiring 52. Since the upper transition metal film 52B is deposited by the CVD method,
Since the step coverage in the step portion of the base is high and the disconnection failure can be reduced, the reliability as the wiring can be improved. The upper transition metal film 52B
Are made of the same metal film material, and therefore have high adhesion to the underlying transition metal film 52A.

As described above, in the DRAM 1 in which the wiring 52 is formed by the (51-30) transition metal film 52B deposited on the underlying interlayer insulating film 51 by the CVD method, the transition metal of the underlying interlayer insulating film 51 and the wiring 52 is formed. A transition metal film 52A substantially the same as the transition metal film 52B deposited by the sputtering method is provided between the transition metal film 52A and the film 52B. With this configuration, the lower transition metal film 52A deposited by the sputtering method has high adhesiveness to the underlying interlayer insulating film 51 and the upper transition metal film 52B of the wiring 52, respectively. The adhesiveness with the wiring 52 can be improved, and the lower transition metal film 52A deposited by the sputtering method is formed of a transition metal film of substantially the same type as the upper transition metal film 52B. Irregularities are prevented from being formed on the processed side wall of the wiring 52, and the processing accuracy of the wiring 52 can be improved.

As shown in FIG. 102, when the lower transition metal film 52A of the wiring 52 is directly connected to the n + type semiconductor region 32 or the p + type semiconductor region 39, the lower transition metal film 52A The heat treatment after the deposition is performed at a temperature lower than a temperature at which W and Si do not undergo an alloying reaction. Specifically, the heat treatment is performed at about 600 ° C. or less. Thus, the wiring 52
By limiting the heat treatment temperature of the lower transition metal film 52A, it is possible to suppress an increase in the resistance value of the connection portion due to the above-described alloying reaction between W and Si, and to prevent an alloy spike phenomenon.

(Embodiment 14) Embodiment 14
In the DRAM 1 according to the first embodiment, the fourteenth embodiment of the present invention has improved reliability at a connection portion between a memory cell M and each element and a wiring.

DRAM 1 according to Embodiment 14 of the present invention
104 is shown in FIG.

The DRAM 1 according to the fourteenth embodiment has the structure shown in FIG.
As shown in FIG. 4, in the memory cell array 11E, an intermediate conductive film 130 is interposed between one n-type semiconductor region 29 of the memory cell selecting MISFET Qs of the memory cell M and the complementary data line (DL) 50. . This intermediate conductive film 130 is formed in the connection hole 1 formed in the interlayer insulating film 131.
One part is connected to the n-type semiconductor region 29 through 31A and the connection hole 34A, and the other part is extended on the sidewall spacer 31 and the interlayer insulating film 131. The connection hole 34A is formed within the connection hole 131A formed in the interlayer insulating film 131 in the memory cell selecting MISFET.
The opening is defined by the sidewall spacer 31 formed on the side wall of the gate electrode 27 of Qs. Since this connection hole 34A is formed in self-alignment with gate electrode 27, as a result, intermediate conductive film 130 is formed.
Is connected to the gate electrode 27 in a self-aligned manner. That is, the n-type semiconductor region 29 of the memory cell selecting MISFET Qs and the complementary data line 50 are connected in a self-aligned manner to the gate electrode 27 of the memory cell selecting MISFET Qs via the intermediate conductive film 130.

The intermediate conductive film 130 is formed above the gate electrode 27 (including the word line 27) of the memory cell selecting MISFET Qs and is lower than the lower electrode layer 35 of the stacked information storage capacitor C. Formed in the lower layer. That is, since the lower electrode layer 35 of the information storage capacitor C having the stacked structure is formed with a large film thickness in order to increase the charge storage amount, the intermediate conductive film 130 is formed in the lower layer in order to improve processing accuracy. It is formed separately from and below the electrode layer 35. The intermediate conductive film 130 is, for example, CV
Formed of a polycrystalline silicon film deposited by the method D;
It is formed with a thin film thickness of about 0 [nm]. An n-type impurity for reducing the resistance value is introduced into the polycrystalline silicon film.

Since the intermediate conductive film 130 can alleviate the particularly steep step at the connection portion between the memory cell M and the complementary data line 50, the disconnection failure of the complementary data line 50 can be reduced. it can.

The intermediate conductive film 130 is also formed on peripheral circuit elements in the same manufacturing process. Although not limited to this, in Embodiment 14, n-channel MISF
ETQn n especially in an area where layout rules are strict
It is provided between the + type semiconductor region 32 and the wiring 52. Normally, peripheral circuits have looser layout rules than the memory cell array 11E. As shown in FIG. 104, even in the case where the wiring 52 runs over the element isolation insulating film 23 in the peripheral circuit region, the intermediate conductive film 130
Can be reliably connected between the n + type semiconductor region 32 and the wiring 52, so that the area of the n + type semiconductor region 32 can be reduced, and as a result, the integration degree of the DRAM 1 can be improved. Also, the n-channel MISFE of the peripheral circuit
Even when each of the TQn and the p-channel MISFET Qp is connected by a wiring 52 formed of a material such as a transition metal film which is liable to cause mutual diffusion of impurities, the intermediate conductive film 130 can prevent the mutual diffusion. Can be reduced.

Next, the DRAM 1 according to the fourteenth embodiment will be described.
The method of forming will be briefly described with reference to FIGS. 105 and 106 (cross-sectional views of main parts shown in respective manufacturing steps).

First, similarly to the method of forming the DRAM 1 of the first embodiment, the memory cell selecting MI of the memory cell M is selected.
SFET Qs, n-channel MISFET Qn of peripheral circuit
To form each.

Next, the memory cell selecting MISFET
An interlayer insulating film 131 is deposited on the entire surface of the substrate so as to cover each of the Qs and n-channel MISFETs Qn. The interlayer insulating film 131 is formed with a thickness of about 40 to 60 [nm] using, for example, a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitrogen oxide gas as a source gas.

Next, the memory cell selection M of the memory cell M
One n-type semiconductor region 29 of ISFET Qs has a predetermined n
In each region of the n + type semiconductor region 32 of the channel MISFET Qn, the connection hole 13 is formed in the interlayer insulating film 131.
1A and the connection hole 34A are formed.

Next, as shown in FIG. 105, the n-type semiconductor regions 29, n + through the connection holes 131A and 34A.
Conductive film 130 connected to each of type semiconductor regions 32
To form

Next, as shown in FIG. 106, an interlayer insulating film 33 is formed on the entire surface of the substrate including the intermediate conductive film. Thereafter, by performing the same steps as those of the method of forming the DRAM 1 of the first embodiment, such as the stacked information storage capacitor C and the p-channel MISFET Qp, the DRAM 1 of the fourteenth embodiment is completed.

As described above, at the intersection of the (53-31) complementary data line 50 and the word line 27, the MISFET Qs for memory cell selection, the lower electrode layer 35, the dielectric film 36, and the upper electrode layer 37 are respectively provided. In the DRAM 1 in which a memory cell M formed of a series circuit of a stacked structure and an information storage capacitor C having a stacked structure is arranged, the complementary data line 50 and one n-type semiconductor region of the memory cell selecting MISFET Qs are arranged. 29, a part is formed in the one n-type semiconductor region 29 in a self-aligned manner, and another part is drawn out on the gate electrode 27 of the memory cell selecting MISFET Qs. An intermediate conductive film 130 formed as a layer separate from the lower electrode layer 35 of the capacitor C is provided below the lower electrode layer 35 of the capacitor C. According to this configuration, since the intermediate conductive film 130 is interposed, a portion corresponding to a mask alignment margin in a manufacturing process between one n-type semiconductor region 29 of the memory cell selecting MISFET Qs and the complementary data line 50 is provided. In addition, the area of the memory cell M can be reduced and the degree of integration can be improved, and the distance between the intermediate conductive film 130 and the lower electrode layer 35 of the stacked information storage capacitor C is eliminated.
Independently, the area of the lower electrode layer 35 can be increased, so that the amount of charge stored in the information storage capacitor C having a stacked structure can be increased, the area of the memory cell M can be reduced, and the degree of integration can be improved. .

The (54-32) intermediate conductive film 130 has a smaller thickness than the lower electrode layer 35 of the information storage capacitor C having the stacked structure. With this configuration, the information storage capacitor C having the stacked structure is
The thickness of the lower electrode layer 35 can be increased and the area can be increased in the height direction.
The area can be reduced and the degree of integration can be improved,
Since the intermediate conductive film 130 is formed to be thin, the processing can be simplified.

(55-33) The memory cell M is provided between the n + -type semiconductor region 32 of the n-channel MISFET Qn constituting the peripheral circuit and the wiring 52 connected thereto.
Is provided with an intermediate conductive film 130 formed of the same conductive layer as the intermediate conductive film 130 provided on the substrate. With this configuration, DRA
Since the intermediate conductive film 130 of the peripheral circuit can be formed in the step of forming the intermediate conductive film 130 formed in the memory cell M of M1, the number of manufacturing steps of the DRAM 1 can be reduced.

As described above, the invention made by the present inventors is described below.
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device using a DRAM as one unit, such as a microcomputer (one-chip microcomputer).

The present invention is not limited to the above-described DRAM, but can be applied to a semiconductor integrated circuit device having another storage function such as an SRAM and a ROM.

Further, the present invention can be applied to a multilayer wiring technology for a printed wiring board or the like.

[0418]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

[0419] According to the present invention, the silicon oxide film under the passivation film can be deposited at a low temperature that does not melt the wiring and at a high step coverage, and the step formed by the wiring layer has a flat shape. Therefore, it is possible to form a silicon nitride film having excellent moisture resistance as an upper layer of the passivation film without forming a cavity based on the step shape. As a result, no cavities are generated in the silicon nitride film above the passivation film, so that cracks in the silicon nitride film and moisture do not accumulate in the cavities, thereby improving the moisture resistance of the passivation film. it can.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a DRAM according to a first embodiment of the present invention;

FIG. 2 is a partial sectional perspective view of a resin-sealed semiconductor device for sealing the DRAM.

FIG. 3 is a chip layout diagram of the DRAM.

FIG. 4 is an equivalent circuit diagram of a main part of a memory cell array of the DRAM.

FIG. 5 is a plan view of a main part of a memory cell array of the DRAM.

FIG. 6 is a plan view of a principal part in a predetermined manufacturing process of the memory cell array of the DRAM.

FIG. 7 is a plan view of a principal part in a predetermined manufacturing process of the memory cell array of the DRAM.

FIG. 8 is a diagram showing a relationship between a target voltage and a specific resistance value at the time of sputtering a film used in the DRAM.

FIG. 9 is a diagram showing a relationship between an X-ray incident angle of the film and an X-ray diffraction spectrum.

FIG. 10 is a diagram showing a relationship between an X-ray incident angle of the film and an X-ray diffraction spectrum.

FIG. 11 is a schematic plan view showing a boundary region between the memory cell array and a peripheral circuit.

FIG. 12 is an enlarged plan view of a main part of the boundary region.

FIG. 13 is a schematic plan view showing a boundary region between the memory cell array and a peripheral circuit.

FIG. 14 is an enlarged plan view of a main part of the boundary region.

FIG. 15 is a cross-sectional view of a principal part at another position of the DRAM.

FIG. 16 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 17 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 18 is a fragmentary cross-sectional view of the DRAM during each manufacturing step.

FIG. 19 is a cross-sectional view of a principal part showing each manufacturing step of the DRAM.

FIG. 20 is a cross-sectional view of a principal part showing each manufacturing step of the DRAM.

FIG. 21 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 22 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 23 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 24 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 25 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 26 is a cross-sectional view of a principal part shown in each manufacturing process of the D2AM.

FIG. 27 is a cross-sectional view of a principal part showing each manufacturing step of the DRAM.

FIG. 28 is a cross-sectional view of a principal part shown in each manufacturing process of the DRAM.

FIG. 29 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 30 is a cross-sectional view of a principal part showing each manufacturing step of the DRAM.

FIG. 31 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 32 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 33 is a cross-sectional view of a principal part showing each manufacturing step of the DRAM.

FIG. 34 is a cross-sectional view of a principal part showing each manufacturing step of the DRAM.

FIG. 35 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 36 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 37 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 38 is a cross-sectional view of a principal part shown in each manufacturing process of the DRAM.

FIG. 39 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 40 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 41 is a cross-sectional view of a principal part shown in each manufacturing process of the D2AM.

FIG. 42 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 43 is a cross-sectional view of a principal part shown in each manufacturing process of the DRAM.

FIG. 44 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 45 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 46 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 47 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 48 is a fragmentary cross-sectional view showing the DRAM at each manufacturing step;

FIG. 49 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 50 is a cross-sectional view of a main part of the fuse element of the DRAM.

FIG. 51 is a cross-sectional view of a main part showing each manufacturing step of the fuse element.

FIG. 52 is a cross-sectional view of a main part showing each manufacturing step of the fuse element.

FIG. 53 is a cross-sectional view of a main part showing each manufacturing step of the fuse element.

FIG. 54 is a diagram showing a relationship between a temperature of a film used in the DRAM and a vapor pressure.

FIG. 55 is a view showing etching characteristics used in the DRAM.

FIG. 56 is a cross-sectional view of a principal part of the DRAM according to the second embodiment of the present invention;

FIG. 57 is a cross-sectional view of a principal part of the DRAM according to the second embodiment of the present invention;

FIG. 58 is a cross-sectional view of a principal part of the DRAM according to the second embodiment of the present invention;

FIG. 59 is a cross-sectional view of a principal part of the DRAM according to the third embodiment of the present invention;

FIG. 60 is a cross-sectional view of a principal part of the DRAM according to the third embodiment of the present invention;

FIG. 61A is a diagram showing the relationship between the deposition time of a film used in the DRAM and the gas flow rate, and FIG. 61B is a diagram showing the relationship between the deposition time of the film and the amount of reaction by-products generated; FIG.

FIG. 62 is a schematic configuration diagram of a CVD apparatus according to Embodiment IV of the present invention.

FIG. 64 is a schematic configuration diagram of a main part of the CVD apparatus.

FIG. 63 is a schematic configuration diagram of main parts of the CVD apparatus.

FIG. 65 is a time chart showing opening and closing operations of a gas valve of the CVD apparatus according to Embodiment V of the present invention.

FIG. 66 is a time chart showing a gas flow rate of the CVD apparatus.

FIG. 67 is a schematic structural view of the CVD apparatus.

FIG. 68 is an essential part cross sectional view showing the manufacturing process of the DRAM according to the sixth embodiment of the present invention;

FIG. 69 is an essential part cross sectional view showing the manufacturing process of the DRAM according to the sixth embodiment of the present invention;

FIG. 70 is a fragmentary cross-sectional view for each manufacturing step of the DRAM that is the sixth embodiment of the present invention;

FIG. 71 is an essential part cross sectional view showing each manufacturing step of the DRAM which is Embodiment 6 of the present invention;

FIG. 72 is an essential part plan view in a predetermined manufacturing step of the DRAM according to Embodiment 7 of the present invention;

FIG. 73 is a cross-sectional view of a principal part shown in each manufacturing process of the DRAM.

FIG. 74 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 75 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 76 is a cross-sectional view of a main part showing each manufacturing step of the DRAM.

FIG. 77 is a plan view of a principal part in another example of the DRAM in a predetermined manufacturing process;

FIG. 78 is a cross-sectional view of a principal part shown in each manufacturing process of another example of the DRAM.

FIG. 79 is a cross-sectional view of a principal part shown in each manufacturing process of another example of the DRAM;

FIG. 80 is a fragmentary cross-sectional view showing the manufacturing steps of another example of the DRAM in each manufacturing step;

FIG. 81 is a fragmentary cross-sectional view showing the manufacturing steps of another example of the DRAM;

FIG. 82 is a cross-sectional view of a principal part shown in each manufacturing process of another example of the DRAM;

FIG. 83 is a fragmentary cross-sectional view showing the manufacturing steps of another example of the DRAM in each manufacturing step;

FIG. 84 is an essential part cross sectional view showing the manufacturing process of another example of the DRAM in each step;

FIG. 85 is a cross-sectional view of a principal part illustrating another manufacturing example of the DRAM in each manufacturing step;

86 is a fragmentary cross-sectional view showing a step of each manufacturing step of another example of the DRAM; FIG.

FIG. 87 is a fragmentary cross-sectional view showing the manufacturing steps of another example of the DRAM in each manufacturing step;

FIG. 88 is a cross-sectional view of a principal part illustrating another manufacturing step of the DRAM in each manufacturing step;

FIG. 89 is an alignment tree diagram of the DRAM according to the eighth embodiment of the present invention.

FIG. 90 is an essential part cross sectional view of a target mark portion of a DRAM according to a ninth embodiment of the present invention;

FIG. 91 is a conceptual diagram of the photolithography technique used in the DRAM manufacturing process according to the tenth embodiment of the present invention.

FIG. 92 is a process flowchart of the photolithography technique.

FIG. 93 is a structural diagram of a substance used in a photolithography technique.

FIG. 94 is a view showing characteristics of the substance.

FIG. 95 is a view for explaining effects when the substance is used.

FIG. 96 is a schematic plan view showing a configuration of a semiconductor wafer according to Embodiment 11 of the present invention;

FIG. 97 is an enlarged plan view of the semiconductor wafer.

FIG. 98 is an enlarged plan view of the semiconductor wafer shown in FIG. 97;

FIG. 99 is a diagram for describing an effect when the associative alignment method is applied.

FIG. 100 is a DRAM 1 according to a twelfth embodiment of the present invention.
It is principal part sectional drawing of.

FIG. 101 is a cross-sectional view of a principal part in a predetermined manufacturing process of the DRAM;

FIG. 102 is a cross-sectional view of a principal part of a DRAM according to a thirteenth embodiment of the present invention;

FIG. 103 is a diagram showing a relationship between a target voltage and a stress at the time of sputtering a film used in the DRAM.

FIG. 104 is a DRAM 1 according to a fourteenth embodiment of the present invention.
It is principal part sectional drawing of.

FIG. 105 is a cross-sectional view of a principal part shown for each manufacturing step of the DRAM.

FIG. 106 is a cross-sectional view of a principal part shown in each manufacturing step of the DRAM.

[Explanation of symbols]

In the figure, 1 ... DRAM, Qs ... MISF for memory cell selection
ET, C: Stacked information storage capacitor, Q
n, Qp... MISFET.

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Makoto Ogasawara 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Fumio Otsuka 2326 Imai, Ome-shi, Tokyo Device, Hitachi Ltd. Inside the Development Center (72) Inventor Kazunori Torii 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Nobuo Owada 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (72) Inventor Mitsuaki Horiuchi 2326 Imai, Device Development Center, Hitachi Ltd. (72) Invention Company Go Tamaru 2326 Imai, Ome-shi, Tokyo Stock Inside the Device Development Center, Inc. (72) Inventor Hideo Aoki 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the Device Development Center, Ltd. (72) Nobuhiro Otsuka 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the Device Development Center (72) Inventor Seiichiro Shirai 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the Device Development Center (72) Inventor Masakazu Sagawa 2326 Imai, Ome-shi, Tokyo Device Development Center, Hitachi, Ltd. (72) Inventor Yoshihiro Ikeda 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Toru Kaga 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Inventor Masatoshi Tsuneoka 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. Inside the Device Development Center (72) Inventor Shuji Ogishi 2326 Imai, Ome-shi, Tokyo Japan Hitachi, Ltd. Inside the Device Development Center (72) Inventor Osamu 2326 Imai, Ome-shi, Tokyo Device Development, Hitachi Ltd. Inside the center (72) Inventor Hiromitsu Enonami 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Atsushi Wakahara 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72 Inventor Hiroyuki Akimori 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Shinichi Suzuki 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Keisuke Funatsu 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Yoshinao Kawasaki 794, Higashi-Toyoi, Kudamatsu, Yamaguchi Prefecture Hitachi, Ltd. On-site (72) Inventor Tsunehiko Tsubone 794 Higashi-Toyoi, Kudamatsu-shi, Yamaguchi Prefecture Inside the Kasado Plant, Hitachi, Ltd. Inside Eye Engineering Co., Ltd. (72) Inventor Ken Tsugane 2326 Imai, Ome-shi, Tokyo Inside Hitachi, Ltd. Device Development Center (56) References JP-A-61-184847 (JP, A) JP-A Sho 63-246829 (JP, A) JP-A-63-213934 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/3205 H01L 21/8242

Claims (3)

(57) [Claims] A plurality of wires as claimed in claim 1] it is disposed on the semiconductor substrate, using the CVD method using tetraethoxysilane as a source gas, a first insulating film formed previously Sharing, ABS line, the first insulating film The second is formed by plasma CVD
In a semiconductor integrated circuit device having an insulating film, a thickness of the wiring is larger than a minimum arrangement interval of the wiring.
And the first insulating film has a minimum spacing of 2 between the wirings.
A semiconductor integrated circuit device having a thickness of at least 1 /. 2. The semiconductor integrated circuit device according to claim 1, wherein the second insulating film is a nitride film. 3. The memory cell selecting MIS according to claim 1, wherein the memory cell selecting MIS is formed on the semiconductor substrate.
FET and the memory cell selecting MISFET are connected in series.
Information formed above the memory cell selecting MISFET.
Information storage capacitor and the memory cell selecting MISFET.
Are formed on the semiconductor substrate at predetermined intervals via an insulating film.
A plurality of first word lines regularly arranged, and a plurality of first word lines arranged at regular intervals on the first word lines via an insulating film.
And extending in the same direction as the first word line,
A plurality of first word lines electrically connected to the first word line.
And the plurality of wirings are the second word lines.
Semiconductor integrated circuit device.