JPH08241968A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a semiconductor integrated circuit device which enhances the junction breakdown strength of a substrate to an element and which reduces a leakage current amount at the junction part of the substrate to the element by a method wherein an active region is not arranged in the boundary region between a first channel stopper region and a second channel stopper region. CONSTITUTION: In a DRAM, a memory cell and an n-channel MISFET in a peripheral circuit are arranged respectively on main faces inside respective different active regions in a p-type well region which is prescribed by a p-type channel stopper region formed on the main face of an inactive region in the p-type well region. Here, a p-type channel stopper region 25A which surrounds the circumference of the memory cell and an n-channel stopper region 24 in the peripheral circuit are constituted independently in separate manufacturing processes. Then, an active region Act such as the memory cell, the n-channel MISFET or the like in the peripheral circuit are not arranged in the boundary region between the p-type channel stopper region 25A and the n-type channel region 24.

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to semiconductor technology, in particular, DRAM (D ynamic R andom A ccess M emor
The present invention relates to a semiconductor integrated circuit device having y) and a technique effectively applied to a forming technique thereof.

[0002]

2. Description of the Related Art A memory cell for holding 1-bit information of a DRAM is composed of a series circuit of a memory cell selecting MISFET and an information storing capacitive element. The memory cell selecting MISFET of the memory cell is formed on the main surface of the active region of the semiconductor substrate (or well region). The active region of the semiconductor substrate is provided in a region defined around the element isolation insulating film (field insulating film) and the channel stopper region formed in the inactive region of the semiconductor substrate. The gate electrode of the memory cell selecting MISFET is connected to a word line extending in the row direction.
One semiconductor region of the memory cell selection MISFET is connected to the complementary data line. The other semiconductor region is connected to one electrode of the information storage capacitive element.
A predetermined potential is applied to the other electrode of the information storage capacitive element.

DRAMs of this type are integrated to increase the capacity, and the size of memory cells tends to be reduced.
When the size of the memory cell is reduced, the size of the information storage capacitive element is also reduced, so that the amount of charge accumulated as information is reduced. The decrease in the amount of accumulated charge decreases the α-ray soft error withstand voltage. For this reason, particularly in a DRAM having a large capacity of 1 [Mbit] or more, improvement of this α-ray soft error withstand voltage is one of the important technical problems.

Based on such technical problems, DRAM
Stacked structure for the information storage capacitor of the memory cell
(STC structure) tends to be adopted. The information storage capacitor of this stacked structure includes a lower electrode layer, a dielectric film,
Each of the upper electrode layers is sequentially laminated and configured. The lower electrode layer is partially connected to the other semiconductor region of the memory cell selection MISFET, and the other region is extended to above the gate electrode. The upper electrode layer is formed on the surface of the lower electrode layer with a dielectric film interposed. The upper electrode layer is integrally formed with the upper electrode layer of the information storage capacitor of the stacked structure of another adjacent memory cell and is used as a common plate electrode.

A DRAM in which memory cells are composed of stacked information storage capacitors is described in, for example, Japanese Patent Application No. 62-235906.

[0006]

DISCLOSURE OF THE INVENTION The present inventor has proposed 16 [Mbi
The following problems were discovered during the development of a DRAM having a large capacity of t].

In a DRAM, isolation between memory cells is currently performed by an insulating film for element isolation and a channel stopper region. The element isolation insulating film is formed by oxidizing the main surface of the non-active region of the semiconductor substrate using an oxidation resistant mask (silicon nitride film) formed on the main surface of the active region of the semiconductor substrate. . On the other hand, the channel stopper area is
It is formed of impurities such as B introduced into the main surface of the active region (only the memory cell array) and the non-active region of the semiconductor substrate. The impurities are introduced by an ion implantation method with high energy such that they pass through the insulating film for separating elements after forming the insulating film for separating elements. That is,
Impurities introduced into the main surface portion of the inactive region of the semiconductor substrate below the insulating film for element isolation are formed as the channel stopper region. The impurities introduced into the main surface portion of the active region of the semiconductor substrate are introduced into a deeper region than the impurities introduced into the main surface portion of the non-active region, so that the memory cell is not adversely affected. This method of forming the channel stopper region using the high-energy ion implantation method has a feature that the inter-channel effect of the memory cell selecting MISFET can be reduced. That is, according to the above-described forming method, the channel stopper region can be formed in a self-aligning manner with respect to the inter-element isolation insulating film, so that the diffusion amount of the impurities forming the channel stopper region on the active region side can be reduced. it can.

However, the DRAM under development by the present inventor
Has a large capacity of 16 [Mbit], and it is difficult to sufficiently secure the memory cell area and the isolation area between the memory cells. In other words, the insulating film for element isolation is the amount of oxidation in the lateral direction.
Since the (bird's beak) is large, the area of the insulating film for element isolation increases more than necessary. On the contrary, the increase in the area of the inter-element isolation insulating film reduces the memory cell area more than necessary.
Therefore, when the film thickness of the element isolation insulating film is reduced and the lateral oxidation amount is reduced, impurities for forming a channel stopper region are introduced into a shallow region of the main surface portion of the active region of the semiconductor substrate. Impurities introduced into the main surface of the active region of the semiconductor substrate increase the impurity concentration on the surface,
The threshold voltage of the memory cell selecting MISFET of the memory cell is changed. Therefore, the area of the memory cells cannot be secured and the isolation area between the memory cells cannot be reduced, so that there has been a problem that the DRAM cannot be highly integrated.

The objects of the present invention are as follows.

(1) To provide a technique capable of improving the degree of integration in a semiconductor integrated circuit device having a memory function.

(2) In the semiconductor integrated circuit device,
It is to provide a technique capable of improving electrical reliability.

(3) In the semiconductor integrated circuit device,
It is to provide a technique capable of improving the soft error withstand voltage.

(4) In the semiconductor integrated circuit device,
It is to provide a technique capable of reducing the number of manufacturing steps.

(5) In the semiconductor integrated circuit device,
It is to provide a technique capable of improving the processing accuracy in manufacturing.

(6) In the semiconductor integrated circuit device,
It is to provide a technique capable of improving the driving capability of a semiconductor element.

(7) In the semiconductor integrated circuit device,
It is to provide a technique capable of improving the manufacturing yield.

(8) In the semiconductor integrated circuit device,
It is to provide a technique capable of increasing the operating speed.

(9) In the semiconductor integrated circuit device,
An object of the present invention is to provide a technique capable of preventing disconnection failure of wiring.

(10) It is an object of the present invention to provide a technique capable of improving the moisture resistance of the semiconductor integrated circuit device.

(11) In a semiconductor integrated circuit device having a redundant fuse element, it is an object of the present invention to provide a technique capable of simplifying the step of forming the redundant fuse element.

(12) It is an object of the present invention to provide a technique capable of improving the film quality of the film used in the semiconductor integrated circuit device.

(13) To provide the manufacturing apparatus according to (12).

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0024]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) A semiconductor substrate including a well region of a first conductivity type having a first region and a second region adjacent thereto, and a first substrate formed on the main surface of the semiconductor substrate of the second region.
An insulating film and a second layer formed in the first region at a predetermined interval.
Memory cell selection including first and second semiconductor regions of conductivity type and a gate electrode formed on a second insulating film located between the first and second semiconductor regions on the main surface of the semiconductor substrate And a first MISFET formed on the main surface of the semiconductor substrate in the second region and located under the first insulating film.
A conductive third semiconductor region, a first electrode connected to the second semiconductor region and containing a second conductive impurity extending over the gate electrode, and a dielectric formed on the first electrode. An information storage capacitive element including a body film and a second electrode formed on the dielectric film, and a first conductivity type formed in the first region below the first and second semiconductor regions. And a thickness of the first insulating film is larger than that of the second insulating film, and the second semiconductor region is self-aligned with the first insulating film. And the third semiconductor region is formed by introducing an impurity of a first conductivity type into the second region through the first insulating film, and the fourth semiconductor region is formed by: By introducing the impurity of the first conductivity type into the first region, the third semiconductor The semiconductor integrated circuit device characterized by being formed by-pass the same step.

(2) Furthermore, the impurity concentration of the third and fourth semiconductor regions is higher than the impurity concentration of the well region.

(3) Further, the second semiconductor region has a first portion having a predetermined concentration and a second portion having a higher concentration than the first portion.
The second portion is formed by diffusing the impurities contained in the first electrode into the semiconductor substrate.

(4) Further, the memory cell selecting MIS
A memory cell array in which a plurality of memory cells including FETs and information storage capacitors are arranged in a matrix, a plurality of data lines extending in a row direction in the memory cell array, and a column direction in the memory cell array. A plurality of existing word lines, the data line is connected to the first semiconductor region, and the word line is connected to a gate electrode of the memory cell selecting MISFET.

(5) On a semiconductor substrate having a first conductivity type well region, a memory cell selecting MISFET including a source / drain region and a gate electrode, a first electrode,
In a semiconductor integrated circuit device in which a plurality of memory cells in which a dielectric film and an information storage capacitive element including a second electrode are connected in series are formed, a first mask serving as an oxidation resistant mask is formed on a first region of the main surface of the semiconductor substrate. A step of forming a first insulating film, a step of forming a second insulating film in the second region of the semiconductor substrate using the first insulating film as a mask, and an energy sufficient to pass through the second insulating film. And a step of ion-implanting the first impurity of the first conductivity type into the first and second regions of the main surface of the semiconductor substrate, and forming a film in the first region of the main surface of the semiconductor substrate, rather than the second insulating film. Forming a third insulating film having a small thickness, and selecting the memory cell M on the third insulating film.
In order to form a gate electrode of the ISFET and to form one of the source and drain regions, the second conductive type is self-aligned with the gate electrode and the second insulating film and is of a second conductivity type on the main surface of the semiconductor substrate. Ion implanting a second impurity, and extending a first electrode containing a second conductivity type impurity onto the gate electrode so as to be electrically connected to one of the source and drain regions. A method of manufacturing a semiconductor integrated circuit device, comprising: a forming step; and a step of forming the dielectric film and the second electrode on the first electrode.

(6) A method of manufacturing a semiconductor integrated circuit device, further comprising a step of removing the first insulating film from the main surface of the semiconductor substrate before the step of ion-implanting the first impurity.

(7) Further, a step of forming a fourth insulating film on the main surface of the semiconductor substrate between the step of ion-implanting the second impurity and the step of forming the first electrode, and the fourth insulating film. Forming a side wall on the side wall of the gate electrode by anisotropically etching, and forming on the side wall a fifth insulating film having an opening so that one of the source and drain regions is exposed. Forming process.

(8) Furthermore, the impurity contained in the first electrode is phosphorus, and the impurity contained in the first electrode diffuses into the semiconductor substrate to form one of the source and drain regions. .

(Operation) According to the above-mentioned means, the first
When each of the channel stopper region and the second channel stopper region overlaps with each other in the boundary region, the impurity concentration of the region becomes high. However, since no active region is arranged in the boundary region, the junction breakdown voltage between the substrate and the element is high. Can be improved. In addition, when the first channel stopper region and the second channel stopper region are separated from each other in the boundary region, a large inversion layer corresponding to the area thereof is likely to occur in the boundary region, and an active region is formed in the boundary region. If present, the area of the element formed in this active region apparently increases by the addition of the inversion layer, and the leak current amount increases at the junction between the substrate and the element, but the active region is arranged in the boundary region. Since this is not done, it is possible to reduce the amount of leak current at the junction.

According to the above-mentioned means, the first MISF is
In ET, the gate length dimension is increased to improve the hot carrier withstand voltage, so that the deterioration of the threshold voltage over time is reduced,
The electric characteristics can be improved, and the second M
The ISFET can achieve low power consumption by using a low voltage while securing a hot carrier withstand voltage by using a low voltage. Moreover, the first MISFET has a long gate length dimension and the second MISFET has a low voltage. Since the hot carrier withstand voltage is improved by each use, the LDD
The length of the low impurity concentration semiconductor region forming the structure in the gate length direction can be independently controlled.
The lengths of the low impurity concentration semiconductor regions of the FET and the second MISFET in the gate length direction can be made substantially the same.

According to the above-mentioned means, the first MISF is
Since all the forming steps of the ET and the second MISFET can be used in common, and especially the respective side wall spacers can be formed in the same manufacturing step, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced.

MI for memory cell selection of the memory cell M
As shown in FIGS. 1, 5 and 6 (plan views of main parts in a predetermined manufacturing process), the SFET Qs has a p-type well region 22.
The main surface of the. Actually, the memory cell selecting MISFET Qs is formed on the main surface portion of the p − type well region 22 which is covered with the p type semiconductor region 25B and has a slightly higher impurity concentration. The memory cell selecting MISFET Qs is formed in a region defined by the element isolation insulating film 23 and the p-type channel stopper region 25A. The memory cell selecting MISFET Qs is mainly composed of a p-type well region 22, a gate insulating film 26, a gate electrode 27, and a pair of n-type semiconductor regions 29 which are a source region and a drain region.

The p-type well region 22 is used as a channel forming region. The gate insulating film 26 is formed of a silicon oxide film formed by oxidizing the main surface of the p − type well region 22. Further, when the dielectric strength is secured as the gate insulating film 26 is made thinner, the gate insulating film 26 may be formed of a composite film in which a silicon oxide film and a silicon nitride film are sequentially laminated.

The gate electrode 27 is provided on the gate insulating film 26. The gate electrode 27 is, for example, CVD.
Formed of a polycrystalline silicon film deposited by the
It is formed with a film thickness of about [nm]. This polycrystalline silicon film is introduced with an n-type impurity (P or As) that reduces the resistance value. The gate electrode 27 is composed of a single layer of a transition metal (high melting point metal Mo, Ti, Ta, W) film or a transition metal silicide (high melting point metal silicide MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film. May be. Further, the gate electrode 27 may be composed of a composite film in which the transition metal film or the transition metal silicide film is laminated on the polycrystalline silicon film.

As shown in FIGS. 5 and 6, the gate electrode 27 is formed integrally with the word line (WL) 27 extending in the column direction. That is, the gate electrode 27 and the word line 27
Are formed of the same conductive layer. The word line 27 is configured to connect the gate electrodes 27 of the memory cell selecting MISFETs Qs of the plurality of memory cells M arranged in the column direction.

As shown in FIG. 6, MI for memory cell selection
The gate length dimension of the gate electrode 27 of the SFET Qs is configured to be longer than the width dimension of the word line 27. For example,
The gate length of the gate electrode 27 is 0.7 [μm], while the width of the word line 27 is 0.5 [μm]. That is, the memory cell selecting MISFET Qs is configured to secure the effective gate length (effective channel length) dimension and reduce the short channel effect. On the other hand, the word lines 27 are configured to minimize the distance between the word lines 27 and reduce the area of the memory cells M to improve the degree of integration. As will be described later, the word line 27 has the resistance value reduced by the shunt word line (WL) 55.
Even if the width dimension is reduced, the operation speeds of the information writing operation and the information reading operation are not reduced. In this embodiment, the DRAM 1 employs a so-called 0.5 [μm] manufacturing process in which the minimum processing dimension is 0.5 [μm].

The n-type semiconductor region 29 is formed with a lower impurity concentration than the n + -type semiconductor region (32) of the MISFET Qn which constitutes the peripheral circuit. Specifically, the n-type semiconductor region 29 is formed by an ion implantation method with a low impurity concentration of less than 1 × 10 ¹⁴ [atoms / cm ² ]. That is, the n-type semiconductor region 29 is formed so as to reduce the occurrence of crystal defects due to the introduction of impurities and to sufficiently recover the crystal defects by heat treatment after the introduction of impurities. Therefore, the n-type semiconductor region 29 is the p-type well region 2
Since the amount of leak current is small at the pn junction with 2,
It is possible to stably hold the electric charge that becomes the information stored in the information storage capacitive element C.

The n-type semiconductor region 29 is the gate electrode 2
7 is formed in self alignment with the channel formation region side
Since it is composed of low impurity concentration, LDD (Lightly
DopedDrain) structure MISFETQ for memory cell selection
compose s.

Further, the memory cell selecting MISFET
The n-type semiconductor region 29 on one side of Qs (the connection side of the complementary data line 50) is a polycrystalline silicon film below the complementary data line (50) in the region defined by the connection hole (40A) described later. The n-type impurities introduced into (50A) are diffused to have a slightly higher impurity concentration. This n-type semiconductor region 2
The n-type impurity introduced into 9 can ohmic-connect each of the n-type semiconductor region 29 and the complementary data line (50), so that the resistance value of the connection portion can be reduced. Further, the n-type impurity causes mask misalignment between the n-type semiconductor region 29 and the connection hole (40A) in a manufacturing process, and the connection hole (40A) is superposed on the element isolation insulating film 23. , Even if the main surface of the p-type well region 22 is exposed in the connection hole (40A), the complementary data line
In order not to short-circuit the (50) and the p-type well region 22, n
A type semiconductor region is formed.

Further, MISFETQs for memory cell selection
The n-type semiconductor region 29 on the other side (connection side of the information storage capacitive element C) is in the region defined by the connection hole (34),
The n-type impurities introduced into the lower electrode layer (35) of the information storage capacitive element C, which will be described later, are diffused to have a slightly higher impurity concentration. The n-type impurities introduced into the n-type semiconductor region 29 are the n-type semiconductor region 29 and the lower electrode layer (35).
Since each of them can be ohmic-connected, the resistance value of the connection portion can be reduced. In addition, the n-type impurity can increase the impurity concentration of the n-type semiconductor region 29 and increase the pn junction capacitance formed by the n-type semiconductor region 29 and the p-type well region 22. The amount of charge stored in the capacitor C can be increased.

An insulating film 28 is provided on the upper layer of the gate electrode 27 of the memory cell selecting MISFET Qs, and sidewall spacers 31 are provided on the side walls of the gate electrode 27 and the insulating film 28, respectively. The insulating film 28 is mainly configured to electrically isolate the gate electrode 27 and each electrode (especially 35) of the information storage capacitive element C formed thereon. The sidewall spacer 31 is provided in the formation region of the memory cell M and is a MIS for memory cell selection.
It is formed in self-alignment with the gate electrode 27 of the FET Qs so as to connect the other n-type semiconductor region 29 and the lower electrode layer 35 of the information storage capacitor C, respectively. Further, the sidewall spacers 31 are configured to make the CMOS an LDD structure in the peripheral circuit formation region. The insulating film 28 and the sidewall spacer 3
Each of No. 1 will be described later with respect to its manufacturing method, but CVD using inorganic silane gas and nitric oxide gas as source gases
It is formed of a silicon oxide film deposited by the method. This silicon oxide film has a higher step coverage in the step portion of the base and a smaller shrinkage of the film than a silicon oxide film deposited by a CVD method using an organic silane gas as a source gas. That is, since the insulating film 28 and the sidewall spacers 31 formed by this method can reduce the peeling between the insulating film 28 and the sidewall spacers 31 due to the shrinkage of the film, the gate electrode 27 and other conductive layers such as the lower electrode layer. A short circuit with 35 can be prevented.

Information storage capacitor C of the memory cell M
As shown in FIG. 1, FIG. 5 and FIG. 7 (plan view of the main part in a predetermined manufacturing process), mainly, a lower electrode layer 35, a dielectric film 36, and an upper electrode layer 37 are sequentially laminated. Is configured. The information storage capacitor C is a so-called stacked structure.
(Stacked type: STC).

A part (center portion) of the lower electrode layer 35 of the information storage capacitor C having the stacked structure is connected to the other n-type semiconductor region 29 of the memory cell selecting MISFET Qs. This connection is made through each of the connection hole 33A formed in the interlayer insulating film 33 and the connection hole 34 defined by the sidewall spacers 31 and 33B. The opening size in the row direction of the connection hole 34 is MI for memory cell selection.
The gate electrode 27 of the SFET Qs, the distance between the word line 27 adjacent to the gate electrode 27, and the sidewall spacer 3
It is specified by the respective film thicknesses of 1 and 33B. Connection hole 33
The difference between the opening size A and the opening size of the connection hole 34 is larger than at least the mask alignment margin in the manufacturing process. The other portion (peripheral portion) of the lower electrode layer 35 is extended to the upper portions of the gate electrode 27 and the word line 27, respectively.

The interlayer insulating film 33 is the insulating film 2 below it.
8. The sidewall spacers 31 are formed of the same insulating film. That is, it is formed of a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitric oxide gas as source gases.

The lower electrode layer 35 is formed of, for example, a polycrystalline silicon film deposited by a CVD method, and an n-type impurity (As or P) for reducing the resistance value is introduced into this polycrystalline silicon film at a high concentration. ing. The lower electrode layer 35 is configured to increase the area of the side wall of the surface thereof to increase the charge storage amount of the information storage capacitive element C having the stacked structure. The lower electrode layer 35 is formed to have a film thickness equal to or larger than a half of the opening size of the connection hole 34 in the gate length direction so as to flatten the surface. For example,
The lower electrode layer 35 is formed with a relatively thick film thickness of about 400 to 600 [nm]. The planar shape of the lower electrode layer 35 is, as shown in FIGS.
0) extends in a rectangular shape that is long in the row direction.

The dielectric film 36 is basically a silicon nitride film 36A deposited by the CVD method on the upper layer (on the surface) of the lower electrode layer (polycrystalline silicon film) 35, and this silicon nitride film 36A is oxidized at high pressure. It has a two-layer structure in which the silicon oxide film 36B is laminated. In practice, the dielectric film 36 is the lower electrode layer 3
The surface of the polycrystalline silicon film which is No. 5 is a natural silicon oxide film (5 [n
Since it has a very thin film thickness of less than [m] and is not shown), it has a three-layer structure in which a native silicon oxide film, a silicon nitride film 36A, and a silicon oxide film 36B are sequentially laminated. The silicon nitride film 36A of the dielectric film 36 is formed by CVD.
Since it is deposited by the method, it can be formed under process conditions independent of the underlying layer, without being affected by the crystalline state or step shape of the underlying polycrystalline silicon film (lower electrode layer 35). That is, the silicon nitride film 36A has a higher withstand voltage and a smaller number of defects per unit area than a silicon oxide film formed by oxidizing the surface of the polycrystalline silicon film, and therefore has a very small leak current. Moreover, the silicon nitride film 36A is characterized by having a higher dielectric constant than the silicon oxide film. Since the silicon oxide film 36B can be formed of a very good quality film, the characteristics of the silicon nitride film 36A can be further improved. Further, as will be described later in detail, the silicon oxide film 36B is formed by high pressure oxidation.
Since it is formed by (1.5 to 10 [toll]), it can be formed in a shorter oxidation time, that is, a heat treatment time than in atmospheric pressure oxidation.

The dielectric film 36 is provided along the upper surface and the side wall of the lower electrode layer 35, and the side wall portion of the lower electrode layer 35 is utilized to increase the area in the height direction. The increase in the area of the dielectric film 36 can improve the charge storage amount of the information storage capacitive element C having the stacked structure. The planar shape of the dielectric film 36 is defined by the planar shape of the upper electrode layer 37, and is substantially the same as the upper electrode layer 37.

The upper electrode layer 37 is provided above the lower electrode layer 35 with the dielectric film 36 interposed therebetween. The upper electrode layer 37 is the upper electrode layer 3 of the information storage capacitive element C of the stacked structure of another adjacent memory cell M.
It is configured integrally with 7. A low power supply voltage 1/2 Vcc is applied to the upper electrode layer 37. The upper electrode layer 37 is formed of, for example, a polycrystalline silicon film deposited by the CVD method, and an n-type impurity that reduces the resistance value is introduced into this polycrystalline silicon film. The upper electrode layer 37 is, for example, the lower electrode layer 35.
The film thickness is smaller than that of The upper electrode layer 3
An insulating film 38 is provided on the surface of 7. Insulation film 38
Will be described later, but is formed when removing the etching residue remaining in the step portion of the underlying surface when the upper electrode layer 37 is processed.

The dielectric film 36 of the information storage capacitor C having the stacked structure is formed on the interlayer insulating film 33 in the region other than the lower electrode layer 35. Interlayer insulation film 3
3 is a silicon oxide film deposited by the CVD method using the inorganic silane gas and the nitric oxide gas as the source gas as described above. In other words, the silicon nitride film 36A, which is the lower layer of the dielectric film 36, has less shrinkage than that of the interlayer insulating film 3
Since it is in contact with the information storage capacitor 3, the information storage capacitor C having the stacked structure is configured to prevent the dielectric film 36 from being damaged due to the stress.

The memory cell M is connected to another one memory cell M adjacent in the row direction as shown in FIGS. 1, 5, 6 and 7. That is, the two memory cells M adjacent in the row direction have their respective memory cell selection MISFEs selected.
One of the n-type semiconductor regions 29 of the TQs is integrally formed, and is formed in an inverted pattern centering on that part. This 2
A plurality of memory cells M are arranged in the column direction, and the two memory cells M and the other two memory cells M adjacent to each other in the column direction are arranged with a shift of ½ pitch in the row direction. .

MISF for memory cell selection of memory cell M
1 and 5 in one n-type semiconductor region 29 of the ETQs.
A complementary data line (DL) 50 is connected as shown in FIG. The complementary data line 50 is connected to the n-type semiconductor region 29 through the connection hole 40A formed in each of the interlayer insulating films 33 and 40.
It is connected to the.

The interlayer insulating film 40 is formed of, for example, a silicon oxide film deposited by a CVD method using inorganic silane gas and nitric oxide gas as source gases. The information storage capacitor C having the stacked structure includes the lower electrode layer 35 and the dielectric film 3.
6. Since the upper electrode layers 37 are sequentially superposed and the lower electrode layer 35 is formed to have a large film thickness, the step shape becomes large. Therefore, the surface of the interlayer insulating film 40 is flattened. That is, the interlayer insulating film 40 is formed on the lower electrode layer 35.
Since the step shape of the surface grows by an amount corresponding to the thickness of the lower electrode layer 35, the lower electrode layer 35 adjacent to the lower electrode layer 35 is adjacent to the lower electrode layer 35.
The surface of the interlayer insulating film 40 is flattened by burying the gap between and. The lower electrode layer 3 of the information storage capacitor C of the stacked structure of the adjacent memory cells M
A region having the smallest interval among the 5 areas forms a large step shape having an aspect ratio of 1 or more. In this embodiment, the minimum distance between the lower electrode layers 35 is about 0.5 [μm]. A dielectric film 36 and an upper electrode layer 37 are interposed between the lower electrode layers 35. Therefore, the interlayer insulating film 40 is formed to have a film thickness of ½ or more of the minimum distance between the dielectric film 36 and the lower electrode layer 35 with the upper electrode layer 37 interposed. Moreover,
The interlayer insulating film 40 is formed to have a film thickness that can secure the dielectric strength and reduce the parasitic capacitance. The interlayer insulating film 40 is, for example, 250
It is formed with a film thickness of about 350 [nm].

The complementary data line 50 is formed of the polycrystalline silicon film 5.
0A and a transition metal silicide film 50B are sequentially laminated to form a two-layer composite film. The lower-layer polycrystalline silicon film 50A is deposited by the CVD method and is, for example, 100 to 15
It is formed with a film thickness of about 0 [nm]. An n-type impurity such as P that reduces the resistance value is introduced into the polycrystalline silicon film 50A. Since the lower polycrystalline silicon film 50A has good step coverage in the step portion of the base, it is possible to reduce disconnection defects of the complementary data lines 50.
The upper transition metal silicide film 50B is deposited by the CVD method (or the sputtering method), and is, for example, 100 to 200 [nm].
It is formed with a film thickness of about the same. The upper transition metal silicide film 50B can reduce the resistance value of the complementary data line 50 and can increase the operation speed of each of the information writing operation and the information reading operation. Further, since the upper layer transition metal silicide film 50B has good step coverage in the step portion of the underlying layer, it is possible to reduce disconnection defects of the complementary data line 50. Each of the lower polycrystalline silicon film 50A and the upper transition metal silicide film 50B of the complementary data line 50 has heat resistance and oxidation resistance. The complementary data line 50 is formed with a wiring width of, for example, about 0.6 [μm].

Thus, (claim 23-means 14), the memory cell selecting MISFET Qs in which the complementary data line 50 is connected to one of the n-type semiconductor regions 29, and the lower electrode layer 35 formed above the MISFET Qs. Dielectric film 36, upper electrode layer 3
A DRA in which a memory cell M is configured by a series circuit with a stacked structure information storage capacitive element C in which 7 are sequentially stacked.
In M1, the polycrystalline silicon film 50A and the transition metal silicide film 50B deposited by the CVD method are sequentially formed on the upper electrode layer 37 of the information storage capacitor C having the stacked structure with the interlayer insulating film 40 interposed therebetween. The complementary data line 50 formed of the laminated composite film is formed, and the interlayer insulating film 40 between the upper electrode layer 37 and the complementary data line 50 is formed.
Of the film thickness of the information storage capacitor C of the stacked structure of the memory cell M and the lower electrode layer 35 of the information storage capacitor C of the stacked structure of another memory cell M that is adjacent to the memory cell M at the minimum distance. Is thicker than a half of the interval between the upper electrode layer 37 and. With this configuration, since the transition metal silicide film 50B in the upper layer of the complementary data line 50 causes mutual diffusion of impurities, a flow is performed by using a BPSG film or a PSG film as the interlayer insulating film 40, and the complementary data line is formed. Although it is not possible to promote the flattening of the underlying surface of 50, the film thickness of the interlayer insulating film 40 is controlled based on the size of the interval between the lower electrode layers 35 adjacent to each other at the minimum interval, and Is filled with the interlayer insulating film 40, and the surface of the interlayer insulating film 40 can be flattened.
It is possible to prevent the short circuit between the complementary data lines 50 due to the etching residue remaining in the step portion of the interlayer insulating film 40 between the lower electrode layers 35 during the processing of 0, and improve the electrical reliability.

A column select signal line (YSL) 5 is formed on the complementary data line 50 with an interlayer insulating film 51 interposed therebetween.
2 are configured.

The interlayer insulating film 51 is, for example, a silicon oxide film 51A deposited by the CVD method and BPSG deposited by the CVD method.
It is composed of a composite film having a two-layer structure in which the films 51B are sequentially laminated. The lower silicon oxide film 51A is an upper BPSG film.
It is provided to prevent B and P added to the film 51B from leaking to the lower layer. The lower silicon oxide film 51A is formed of, for example, a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitric oxide gas as source gases.
The lower silicon oxide film 51A is, for example, 100 to 200 [nm].
It is formed with a film thickness of about the same. Upper BPSG film 51B
Has been flowed to flatten its surface.
The BPSG film 51B is formed with a film thickness of, for example, about 250 to 350 [nm].

Since the column select signal line 52 is deposited on the surface of the underlying interlayer insulating film 51, it is formed of, for example, a transition metal film deposited by sputtering. This transition metal film is formed of, for example, a W film. The column select signal line 52 is formed with a film thickness of, for example, about 350 to 450 [nm]. Since the column select signal line 52 is formed in an upper layer different from that of the complementary data line 50, it is not defined by the wiring pitch of the complementary data line 50, and the connection between the complementary data line 50 and the memory cell M is established. No need to avoid parts. That is, the column select signal line 52 is wider than the wiring width dimension of the complementary data line 50 and can extend substantially linearly, so that the resistance value can be reduced. The column select signal line 52 is formed with a wiring width dimension of, for example, about 2.0 [μm].

A shunt word line (WL) is formed on the column select signal line 52 with an interlayer insulating film 53 interposed therebetween.
55 is configured. Although not shown, the shunt word line 55 is connected to the word line (WL) 27 in a predetermined region corresponding to every tens to hundreds of memory cells M. The word line 27 is divided into a plurality of parts in the extending direction in the memory cell array 11E, and the shunt word line 55 is divided into the plurality of divided word lines 27.
It is connected to the. The shunt word line 55 is configured to reduce the resistance value of the word line 27 and increase the selection speed of the memory cell M in each of the information writing operation and the information reading operation.

As shown in FIG. 1, the interlayer insulating film 53 is a silicon oxide film (deposition type insulating film) 53A, a silicon oxide film (coating type insulating film) 53B, a silicon oxide film (deposition type insulating film) 53C.
It has a three-layer structure formed by a composite film in which each of the above is sequentially laminated. Silicon oxide film 53 under the interlayer insulating film 53
A, the upper silicon oxide film 53C is deposited by conformal plasma CVD (hereinafter, C-CVD) method using tetraepoxysilane (TEOS: Si (OC ₂ H ₅ ) ₄ ) gas as a source gas. Each of the lower silicon oxide film 53A and the upper silicon oxide film 53C deposited by the C-CVD method can be deposited at a low temperature (about 400 [° C.] or less) and has high step coverage. Lower silicon oxide film 53
A, the upper silicon oxide film 53C is, for example, 250 to 3 respectively.
It is formed with a film thickness of about 50 [nm]. Interlayer insulating film 5
Silicon oxide film 53B of the third intermediate layer is SOG (S pin O n G las
It is formed of a silicon oxide film which is applied by the method s) and then baked. The intermediate silicon oxide film 53B is formed for the purpose of flattening the surface of the interlayer insulating film 53. The middle-layer silicon oxide film 53B is formed so as to be applied, baked, and then etched on the entire surface so as to be embedded only in the recessed portion of the stepped portion. In particular, the intermediate silicon oxide film 53B is removed by etching so that it will not remain on the surface of the inner wall of the connection hole 53D formed in the interlayer insulating film 53, which will be described later. That is, the intermediate silicon oxide film 53B is configured to reduce the corrosion of the aluminum film of the shunt word line 55 or its alloy film due to the moisture contained therein. The intermediate silicon oxide film 53B is applied with a film thickness of, for example, about 100 [nm].

The shunt word line 55 is composed of a composite film formed by sequentially laminating a transition metal nitride film (or transition metal silicide film) 55A and an aluminum alloy film (or aluminum film) 55B. .

When the lower transition metal nitride film 55A is formed by adding Cu to the upper aluminum alloy film 55B,
For example, a TiN film having a barrier property is used. The lower transition metal nitride film 55A is formed of, for example, a TiN film when Si is added to the upper aluminum alloy film 55B. In this case, a transition metal silicide film such as MoSi ₂ is used. The lower transition metal nitride film 55A is deposited by, for example, a sputtering method, and has a thickness of 100 [n
The film thickness is about m]. When a TiN film is used as the lower-layer transition metal nitride film 55A, a TiN film having a (200) crystal orientation is used, which will be described in detail later.

The upper aluminum alloy film 55B is formed by adding Cu and Si to aluminum. Cu is added to reduce the migration phenomenon.
About 5% by weight is added. Si is added to reduce the alloy spike phenomenon, for example, about 1.5 [wt%]. Aluminum alloy film 50B
Is deposited by, for example, a sputtering method, and is 600 to 800 [n
The film thickness is about m].

The shunt word line 55 is, for example, 0.1.
The wiring width is about 7 [μm].

As described above, the memory cell array 11E of the DRAM 1 of the present embodiment has a multilayer wiring structure of a total of 6 layers in which the 2-layer wiring structure is provided on the 4-layer gate wiring structure.

The four-layer gate wiring structure has the gate electrode 27 (or word line 2) of the MISFETQs for memory cell selection.
7), it is composed of the lower electrode layer 35, the upper electrode layer 37 and the complementary data line 50 of the stacked structure information storage capacitor C. The two-layer wiring structure is composed of column select signal lines 52 and shunt word lines 55.

CM constituting the peripheral circuit of the DRAM 1
The OS is configured as shown on the right side of FIG. C
The MOS n-channel MISFET Qn is formed on the main surface portion of the p − type well region 22 in a region surrounded by the element isolation insulating film 23 and the p type channel stopper region 24. The n-channel MISFET Qn is
The p-type well region 22, the gate insulating film 26, the gate electrode 27, a pair of n-type semiconductor regions 29 serving as a source region and a drain region, and a pair of n + -type semiconductor regions 32 are mainly formed.

The p-type channel stopper region 24 surrounding the n-channel MISFET Qn is the memory cell M.
Of the p-type channel stopper region 25A surrounding the memory cell selecting MISFET Qs. In the p-type channel stopper region 24, a p-type impurity is introduced using the same mask as the mask for forming the inter-element isolation insulating film 23, and the p-type impurity is heat-treated for forming the inter-element isolation insulating film 23. It is formed by activating with. This p-type channel stopper region 24
Is formed in the same manufacturing process as the element isolation insulating film 23, the diffusion amount of the p-type impurity to the active region side is slightly large, but the n-channel MISFET Qn has a larger size than the memory cell selecting MISFET Qs. Since it is formed, the diffusion amount of the p-type impurity is relatively small. Therefore, the n-channel MISFET Qn is less affected by the sandwiched channel effect. On the contrary, the p-type channel stopper region 2
Since the p-type impurity forming 4 is introduced only into the main surface portion of the inactive region of the p-type well region 22, the impurity concentration of the main surface of the active region of the p-type well region 22 can be lowered. That is, since the threshold voltage of the n-channel MISFET Qn can be lowered, the substrate effect can be reduced and the driving ability can be enhanced. In particular, when the n-channel MISFET Qn is used as the output stage circuit, the output signal level can be sufficiently secured.

Each of the p-type well region 22, the gate insulating film 26, the gate electrode 27, and the n-type semiconductor region 29 is formed in the same manufacturing process as the memory cell selecting MISFET Qs, and has substantially the same function. Have That is, the n-channel MISFET Qn has an LDD structure.

The high impurity concentration n + type semiconductor region 32 is configured to reduce the specific resistance value of each of the source region and the drain region. The n + type semiconductor region 32 is defined and formed by the sidewall spacer 31 formed on the side wall of the gate electrode 26 in a self-aligned manner, and is formed in a self-aligned manner with respect to the gate electrode 27. The sidewall spacer 31 serves as an n-type semiconductor region 2 forming the LDD structure.
The length of 9 in the gate length direction is specified.
The sidewall spacer 31 is an n-channel MISFE.
Since it is formed as a single layer in the formation region of TQn,
The dimension of the n-type semiconductor region 29 in the gate length direction can be shortened. Since the n-type semiconductor region 29 has a low impurity concentration, it has a high resistance value.
Since the length of 9 is short, the n-channel MISFET Qn can improve the transfer conductance.

Of the n-channel MISFETQn, the n-channel MISFETQn used in the input / output stage circuit is
Since a single power supply voltage Vcc (5 [V]) is used to interface with an external device, the device is driven by the power supply voltage Vcc. This n
The channel MISFET Qn has, for example, a gate length of 8 [μ
m] to reduce the electric field strength near the drain region. On the other hand, an n-channel MISFET Qn used in an internal circuit such as a direct peripheral circuit or an indirect peripheral circuit has a low power supply voltage Vcc (about 3.3 [V]) to reduce power consumption.
Is driven by. This n-channel MISFET Qn has a gate length of, for example, 0.8 to 1.4 in order to achieve high integration.
The field intensity in the vicinity of the drain region is relaxed by the introduction of the low power supply voltage Vcc. The n-channel MISFET Q of each of the input / output stage circuit and the internal circuit
n has substantially the same structure only by changing the size of the gate length and changing the power supply used. That is,
N channel MISFE for each of the input / output stage circuit and the internal circuit
The TQn can be composed of the gate insulating film 26, the gate electrode 27, the n-type semiconductor region 29, and the n + -type semiconductor region 32. Furthermore, each n-channel MISFET Qn
The sidewall spacers 31 can be formed to have substantially the same size in the gate length direction.

Thus, the (11-6) n-channel MISFETQ of the LDD structure used as the input / output stage circuit.
n, in the DRAM 1 having the n-channel MISFET Qn of the LDD structure used as an internal circuit,
The operating voltage of the n-channel MISFET Qs of the input / output stage circuit is set higher than the operating voltage of the n-channel MISFET Qn of the internal circuit, and the gate length dimension of the n-channel MISFET Qn of the input / output stage circuit is set to the n-channel of the internal circuit. The length in the gate length direction of the n-type semiconductor region 29 having a low impurity concentration, which is longer than the gate length of the MISFET Qn and forms the LDD structure of the n-channel MISFET of each of the input / output stage circuit and the internal circuit, is substantially the same. The same size. With this configuration, in the n-channel MISFET Qn of the input / output stage circuit, the length of the gate length is increased to improve the hot carrier withstand voltage, so that the deterioration of the threshold voltage over time is reduced and the electrical characteristics are improved. And the n-channel MISFE of the internal circuit
TQn can achieve low power consumption by using the low power supply voltage Vcc while securing the hot carrier breakdown voltage by using the low power supply voltage Vcc, and further, n of the input / output stage circuit can be achieved.
The channel MISFETQn has a long gate length, and the n-channel MISFETQn in the internal circuit has a low power supply voltage Vcc.
Since the hot carrier withstand voltage is improved by using each of them, the length in the gate length direction of the low impurity concentration n-type semiconductor region 29 forming the LDD structure can be independently controlled, and the input / output stage circuit , Making the lengths of the low impurity concentration n-type semiconductor regions 29 of the respective n-channel MISFETs Qn of the internal circuits in the gate length direction (or the lengths of the sidewall spacers 31 in the gate length direction) substantially the same. You can That is, the DRAM 1 can reduce power consumption and improve the hot carrier breakdown voltage, and can reduce the number of manufacturing steps for forming the n-channel MISFET Qn, which will be described later.

An interlayer insulating film 40 and an interlayer insulating film 51 are formed in the n + type semiconductor region 32 of the n-channel MISFET Qn.
The wiring 52 is connected through the connection hole 51C formed in. The wiring 52 is formed in the lower wiring layer of the two-layer wiring structure which is the same conductive layer as the column select signal line 52.

CMOS p-channel MISFET Qp
Is formed on the main surface portion of the n − type well region 21 in the region surrounded by the element isolation insulating film 23. The p-channel MISFET Qp mainly includes the n − type well region 21, the gate insulating film 26, the gate electrode 27, and the pair of p type semiconductor regions 3 which are the source region and the drain region.
0 and a pair of p + type semiconductor regions 39.

The n--type well region 21 and the gate insulating film 26
Each of the gate electrode 27 and the gate electrode 27 is a memory cell selection M.
The ISFET Qs and the n-channel MISFET Qn have substantially the same functions.

The p-type semiconductor region 30 having a low impurity concentration is LD
A p-channel MISFET Qp having a D structure is constructed. The high impurity concentration p + type semiconductor region 39 is formed in self-alignment with the side wall spacers 31 and 33C formed in the side wall of the gate electrode 27 in self-alignment. That is, the high impurity concentration p + type semiconductor region 39 of the p-channel MISFET Qp is formed to have a two-layer structure in which the sidewall spacer 33C is laminated on the sidewall of the sidewall spacer 31. The sidewall spacers 31 and 33C are n-channel MISFETs.
Compared with the sidewall spacer 31 of Qn, the dimension in the gate length direction is made longer by the amount corresponding to the sidewall spacer 33C. That is, since the sidewall spacers 31 and 33C can increase the dimension in the gate length direction and reduce the diffusion amount of the p-type impurity of the p + -type semiconductor region 39 toward the channel formation region side, the effective channel length. Is ensured and the short channel effect of the p channel MISFET Qp can be reduced. n
Since the diffusion coefficient of p-type impurities is larger than that of type impurities,
The p-channel MISFET Qp has the above-mentioned structure.

As described above, the n-channel MISFET Qn having the (15-8) LDD structure and the p-channel MI having the LDD structure are provided.
In the DRAM 1 having each SFETQp, the side wall spacers 31 and 33C formed in self-alignment with the side walls of the gate electrode 27 of the p-channel MISFETQp in the gate length direction are the same as the gate electrode 27 of the n-channel MISFETQn. The side wall spacers 31 formed on the side walls of the above in a self-aligned manner are longer than the dimension in the gate length direction. With this configuration, the dimension of the sidewall spacer 31 of the n-channel MISFET Qn in the gate length direction is shortened,
Low impurity concentration n-type semiconductor region 2 forming LDD structure
Since the length of 9 in the gate length direction can be shortened,
It is possible to improve the transfer conductance of the n-channel MISFET Qn and increase the operating speed, and increase the dimension of the sidewall spacers 31 and 33C of the p-channel MISFET Qp in the gate length direction to obtain a high impurity concentration p + type semiconductor. Since the wraparound of the region 39 to the channel formation region side can be reduced, the short channel effect of the p-channel MISFET Qp can be reduced, and high integration can be achieved.

A wiring 52 is formed in the p + type semiconductor region 39 of the p channel MISFET Qp through the connection hole 51C.
Is connected.

As shown on the right side of FIG. 1, the wiring 52 is connected to the wiring 55 in the upper layer with the transition metal film 54 buried in the connection hole 53D formed in the interlayer insulating film 53 being interposed. . The wiring 55 extending on the interlayer insulating film 53 is formed in the upper wiring layer of the two-layer wiring structure which is the same conductive layer as the shunt word line 55. The connection hole 5
The transition metal film 54 embedded in 3D is formed by selective CVD, for example.
Formed by the W film selectively deposited on the surface of the wiring 52 exposed from the inside of the connection hole 53D by the method. The transition metal film 54 is formed in order to improve step coverage in the step shape formed by the connection hole 53D of the wiring 55.

The wiring 55 (including the shunt word line 55) is formed of a composite film in which the transition metal nitride film 55A and the aluminum alloy film 55B are sequentially laminated as described above. The wiring 55 is mainly the upper aluminum alloy film 5
The signal transmission speed is regulated by 5B. Transition metal nitride film (transition metal silicide film) 55A under the wiring 55
When Si is added to the upper aluminum alloy film 55B, the upper aluminum alloy film 55B and the interlayer insulating film including the connection portion between the wiring 55 and the transition metal film 54 embedded in the connection hole 53D are included. It is provided in the whole area between 53. That is, in the wiring 55, the underlying material of the upper aluminum alloy film 55B is made uniform in each of the connection hole 53D portion and the interlayer insulating film 53 portion. Further, the transition metal film 55A in the lower layer of the wiring 55 has a higher migration withstand voltage than the aluminum alloy film 55B in the upper layer. That is, even when the upper layer aluminum alloy film 55B is disconnected due to the migration phenomenon, a signal can be transmitted by the lower transition metal film 55A, so that the disconnection failure of the wiring 55 can be reduced.

As described above, the transition metal film 54 buried by the selective CVD method in the connection hole 53D formed in the (29-16) underlying interlayer insulating film 53 and extending on the interlayer insulating film 53. In the DRAM 1 that connects the respective aluminum alloy films 55B to which Si is added, the aluminum alloy film 55B including the transition metal film 54 and the aluminum alloy film 55B embedded in the connection hole 53 and the underlying interlayer A transition metal nitride film (or a transition metal silicide film) 55A is provided between the insulating film 53 and the insulating film 53. With this configuration, the base of the aluminum alloy film 55B is made uniform on the transition metal film 54 embedded in the connection hole 53D and on the interlayer insulating film 53, and Si added to the aluminum alloy film 55B is removed. Since it is possible to reduce precipitation at the interface between the transition metal film 54 and the aluminum alloy film 55B buried in the connection hole 53D, it is possible to reduce the resistance value at the interface. The transition metal nitride film 55A provided under the aluminum alloy film 55B is
Even if the aluminum alloy film 55B is broken due to, for example, a migration phenomenon, the aluminum alloy films 55B can be connected to each other with this broken portion interposed.
The disconnection failure of the wiring 55 can be reduced.

The wiring 55 (including the shunt word line 55) has at least the aluminum alloy film 55 when Cu is added to the upper aluminum alloy film 55B.
A transition metal nitride film 55A is provided at a connection portion (interface portion) between B and the transition metal film 54 embedded in the connection hole 53D. This transition metal nitride film 55A has a barrier property as described above. That is, the wiring 55 is configured to prevent an alloying reaction due to mutual diffusion between aluminum of the upper aluminum alloy film 55B and W of the transition metal film 54 buried in the connection hole 53D.

As described above, the transition metal film 54 embedded by the selective CVD method in the connection hole 53D formed in the (31-17) underlying interlayer insulating film 53 and extending on the interlayer insulating film 53. In the DRAM 1 that connects the respective Cu-added aluminum alloy films 55B, the transition metal film 54 and the aluminum alloy film 55B buried in the connection holes 53D.
A transition metal nitride film 55A having a barrier property is provided between and. With this configuration, at the interface between the transition metal film 54 and the aluminum alloy film 55B buried in the connection hole 53D, the alloying reaction due to the mutual diffusion of the transition metal and aluminum is prevented, and the resistance value of the interface is reduced It can be reduced.

A transition metal nitride film 55 under the wiring 55.
As described above, A having a crystal orientation of (200) is positively used. Figure 8 shows the target voltage during sputtering
The relationship between [KW] and specific resistance value [μΩ-cm] is shown. data
Each of (A) and (B) shows the distance from the center of the semiconductor wafer of the TiN film deposited by the sputtering method on the surface of the semiconductor wafer. The data (A) shows that the distance from the center of the semiconductor wafer is 0 [μm], that is, Ti at the center of the semiconductor wafer.
The characteristics of the N film are shown. Data (B) represents the characteristics of the TiN film at the position where the distance from the center of the semiconductor wafer is 50 [μm].

As shown in FIG. 8, the data (B), that is, the distance from the center of the semiconductor wafer, the lower the specific resistance value of the TiN film. The X-ray diffraction spectrum of the TiN film is shown in FIG. 9 (X-ray incidence angle and X-ray diffraction angle) in the region C having a high specific resistance value shown in FIG. Figure showing the relationship with strength). In addition, in the region where the specific resistance value is lower than D, for example, in the region where it is about 400 [μΩ-cm] or less, X is added to the TiN film.
The result of the line diffraction spectrum is shown in FIG. 10 (a diagram showing the relationship between the X-ray incident angle and the X-ray diffraction intensity). FIG. 9
As shown in, the TiN film has a mixture of (111) crystal orientations and (200) crystal orientations in a region where the specific resistance value is high. On the other hand, as shown in FIG. 10, the TiN film has a single crystal orientation of (200). That is, Ti having a (200) crystal orientation
The N film includes (111) alone or (111) and (200).
8 compared with a TiN film having a crystal orientation in which
As shown in (1), since the specific resistance value is low, there are physical properties that the film density is high. Therefore, the TiN film having the (200) crystal orientation is excellent in heat resistance (barrier property) and can reduce the precipitation of Si.

As described above, (33-18) the transition metal nitride film 55A as the lower layer of the wiring 55, particularly between the transition metal film 54 embedded in at least the connection hole 53D and the upper aluminum alloy film 55B. The transition metal nitride film 55A is composed of a TiN film whose crystal orientation is (200). With this configuration, the TiN film having the (200) crystal orientation is a TiN film having the (111) crystal orientation or the (11) crystal orientation.
TiN with mixed crystal orientation of 1) and (200)
Since it is possible to reduce the amount of Si deposited as compared with the film,
The resistance value at the interface (54-55B interface) can be further reduced, and the specific resistance value is smaller than that of the TiN film having the other crystal orientation, so that the resistance value at the interface can be further reduced. Moreover, since the film density is high, the barrier property can be further improved.

As shown in FIGS. 1 and 15 (a cross-sectional view of a main part showing a cross-sectional structure at a position different from the cross-sectional structure shown in FIG. 1), in the peripheral circuit region of the DRAM 1, of the two-layer wiring structure, The wiring 52 of the lower layer is made of a transition metal film as described above because the wiring width dimension is reduced due to high integration and the migration withstand voltage cannot be secured by the aluminum film or the aluminum alloy film. As the peripheral circuit, particularly the direct peripheral circuit is a memory cell M of the memory cell array 11E.
N-channel MISFETQ corresponding to the array pitch of
Since the n and p channel MISFETs Qp are arranged, the layout rule of the wiring 52 is strict.

In the peripheral circuit region, when the n + type semiconductor region 32 of the n-channel MISFET Qn and the p + type semiconductor region 39 of the p-channel MISFET Qp are connected, a transition metal silicide film or a laminated film thereof (for example, complementary data) When wiring is formed with the same conductive layer as the line 50, mutual diffusion of impurities occurs. Therefore, the wiring 52 does not use the same conductive layer as the complementary data line 50 used in the memory cell array 11E, but uses the above-described transition metal film in which mutual diffusion of the impurities does not occur.

As described above, (26-15) each of the complementary data line, the shunt word line, and the column select signal line is provided on the memory cell array 11E, and two layers are formed in the peripheral circuit region of the memory cell array 11E. DR with wiring layer
In AM1, the complementary data line 50 on the memory cell array 11E is formed by the polycrystalline silicon film 5 deposited by the CVD method.
0A and a transition metal silicide film 50B are sequentially laminated to form a composite film, and the column select signal line 52 is
A word line 55 for shunt is formed on the complementary data line 50 by a transition metal film deposited by a sputtering method.
Is formed of an aluminum alloy film 55B (including a transition metal nitride film 55A) deposited by a sputtering method on the upper layer of the column select signal line 52, and the shunt word line 5
The same conductive layer (55) as 5 and the column select signal line 52 thereunder and the same conductive layer (52) are buried in the connection hole 53D formed in the interlayer insulating film 53 between them by the selective CVD method. Connected via the embedded transition metal film 54, the lower wiring 52 of the two wiring layers in the area of the peripheral circuit is formed of the same conductive layer as the column select signal line 52, Of the wiring layers, the upper wiring 55 is formed of the same conductive layer as the shunt word line 55,
The lower layer wiring 52 and the upper layer wiring 55 of the layer wiring layer are connected to each other with the transition metal film 54 buried in the connection hole 53D interposed by the selective CVD method. With this configuration, the following effects can be obtained.

(1) The complementary data line 50 on the memory cell array 11E has excellent heat resistance and oxidation resistance,
In addition, since the step coverage of the lower layer polycrystalline silicon film 50A deposited by the CVD method is high, disconnection defects can be reduced. Further, since the transition metal silicide film 50B of the upper layer is deposited by the CVD method on the complementary data line 50, the step coverage can be further improved and the disconnection defect can be reduced.

(2) The column select signal line 52 is
Since it can be formed in the upper layer of the complementary data line 50 and can be extended in a substantially straight line shape without avoiding the connection portion (connection hole 40A) between the complementary data line 50 and the memory cell M,
The signal transmission speed can be increased to increase the speed of each of the information writing operation and the information reading operation, and since the complementary data line 50 is formed in a different layer, the wiring interval of the complementary data line 50 in the lower layer can be increased. The degree of integration can be improved by reducing the size.

(3) Since the resistance value of the shunt word line 55 is lower than that of the complementary data line 50 and the column select signal line 52 in the lower layer, the resistance value of the shunt word line 55 is reduced to write information. The speed of each of the operation and the information reading operation can be increased.

(4) The same conductive layer 52 as the column select signal line 52 and the same conductive layer as the shunt word line 55.
The transition metal film 54 connecting each of the (55) compensates the step coverage at the connection part of the same conductive layer (55) as the upper shunt word line 55 and reduces the disconnection failure of the conductive layer (55). In addition, the underlying conductive layer (52) is made of the same kind of transition metal film (52), so that the stress between the underlying conductive layer (52) and the underlying transition metal film (52) can be reduced.

(5) Wiring 5 in the lower layer of the peripheral circuit region
2. In particular, since the direct peripheral circuits (sense amplifier circuit and decoder circuit) of the memory cell array 11E are transition metal films, the migration withstand voltage is high, and the width of the wiring 52 is reduced (reduced according to the arrangement pitch of the memory cells M). Therefore, the degree of integration can be improved.

As shown in FIG. 1, a passivation film 56 is provided on the upper layer of the shunt word line 55 and the wiring 55 of the DRAM 1. Passivation film 5
6 is a composite film in which a silicon oxide film 56A and a silicon nitride film 56B are sequentially laminated.

The lower silicon oxide film 56A is configured to flatten its surface, that is, the underlying surface of the upper silicon nitride film 56B. Since the lower silicon oxide film 56A has the aluminum alloy film 55B formed on the upper layers of the lower shunt word line 55 and the wiring 55, the lower silicon oxide film 56A is deposited at a low temperature that does not melt the aluminum alloy film 55B. That is, the lower silicon oxide film 56A is deposited by the C-CVD method using tetraepoxysilane gas as a source gas, for example. Since the lower silicon oxide film 56A has good step coverage in the stepped portion of the underlying surface, in order to flatten the surface, the shunt word lines 55 or the wiring 55 are required.
Between the shunt word lines 55 or the wiring 55 in a region having an aspect ratio of 1 or more, which is a ratio between the space and the film thickness.
It is formed with a film thickness of ½ or more. The region having an aspect ratio of 1 or more corresponds to the minimum wiring interval or a dimension close thereto, and the step coverage of the upper silicon nitride film 56 does not pose a problem in the region having an aspect ratio of 1 or less. Since the shunt word lines 55 are formed with a wiring interval of about 0.7 [μm], the lower silicon oxide film 56A is formed with a thickness of about 350 to 500 [nm].

The silicon nitride film 56B, which is the upper layer of the passivation film 56, is formed to improve the moisture resistance. The upper silicon nitride film 56B is formed, for example, by plasma C
It is deposited by the VD method and is formed with a film thickness of about 1000 to 1200 [nm]. The upper silicon nitride film 56B is
Since the surface of the lower silicon oxide film 56A is flattened, it is possible to prevent the formation of cavities and the like due to the growth of the overhang shape in the step portion of the base.

As described above, in the DRAM 1 in which the passivation film 56 is provided on the wiring 55 mainly composed of the (34-19) aluminum alloy film 55B, the passivation film 56 is C-using tetraepoxysilane gas as a source gas. A silicon oxide film 56A deposited by the CVD method,
The silicon nitride film 56B deposited by the plasma CVD method is sequentially laminated to form a composite film, and the silicon oxide film 56A under the passivation film 56 has an aspect ratio of the interval between the wirings 55 and the film thickness of the wiring 55. Is formed to have a film thickness of ½ or more of the interval between the wirings 55 in the region of 1 or more. With this structure, the passivation film 56 is formed.
The lower silicon oxide film 56A can be deposited at a low temperature that does not melt the aluminum alloy film 55B of the wiring 55 and with high step coverage, and the step shape formed by the wiring 55 can be flattened. Therefore, it is possible to form the silicon nitride film 56B having an excellent moisture resistance as the upper layer of the passivation film 56 without forming a cavity based on the step shape. As a result, no cavities are formed in the silicon nitride film 56B, which is the upper layer of the passivation film 56, so that the silicon nitride film 56 is not cracked or moisture is not accumulated in the cavities. Can be improved.

Memory cell array (MA) of the DRAM 1
The boundary area between 11E and the peripheral circuit is configured as shown in FIG. 11 (schematic plan view) and FIG. 12 (enlarged plan view of the main part of FIG. 11). That is, the p-type channel stopper region 25A formed in the inactive region of the memory cell array 11E,
The p-type channel stopper regions 24 formed in the inactive region of the peripheral circuit are not overlapped with each other in the boundary region. The p-type channel stopper region 25A of the memory cell array 11E and the p-type channel stopper region 24 of the peripheral circuit
Since each of them is formed by a separate manufacturing process, the impurity concentration of the non-active region, which is the boundary region, is lowered without being polymerized in the boundary region. This is because the n-type semiconductor region 29 and the n + -type semiconductor region 3 are formed in the active region.
It is possible to increase the pn junction breakdown voltage between each of No. 2 and the main surface of the boundary region of the p − type well region 22. However,
Since the impurity concentration of the main surface of the inactive region of the boundary region of the p − type well region 22 is low, the threshold voltage of the parasitic MOS is lowered, and the n type inversion layer is likely to occur. This n-type inversion layer is formed in a large area surrounding the memory cell array 11E, and when an active region is present so as to cross the boundary region or in the vicinity thereof, the area of the active region corresponds to the area of the n-type inversion layer. To increase. This apparently increases the pn junction area and increases the leak current amount at the pn junction. Therefore, as shown in FIG. 12, the active region Ac is
t For example, the n-channel MISFET Qn of the peripheral circuit is separated from the boundary region (does not cross the boundary region).
This distance is at least the mask misalignment amount in the manufacturing process, and the n-type semiconductor region 29 and the n + -type semiconductor region 32.
The dimensions are determined in consideration of the diffusion amount of each n-type impurity.

Also, the memory cell array (MA) 11E
The boundary area between the peripheral circuit and the peripheral circuit is shown in FIG. 13 (schematic plan view) and FIG.
4 (main part enlarged plan view of FIG. 13). That is, the p-type channel stopper region 25A of the memory cell array 11E and the p-type channel stopper region 24 of the peripheral circuit are overlapped at the boundary region. This superposition is performed at least by the amount corresponding to the mask alignment margin in the manufacturing process. When the p-type channel stopper regions 24 and 25A are overlapped with each other, the impurity concentration of the boundary region of the inactive region becomes high. When the impurity concentration of the main surface portion of the inactive region of the p − type well region 22 becomes high,
Although the threshold voltage of the parasitic MOS can be increased to improve the isolation capability, on the contrary, the pn junction breakdown voltage between the n-type semiconductor region 29 and the n + -type semiconductor region 32 formed in the boundary region and the active region, respectively. Deteriorates.

Therefore, as shown in FIG. 14, the active region Act, for example, the n-channel MISFET Qn of the peripheral circuit is formed.
Separate from the border region. This separation is at least the mask misalignment amount in the manufacturing process and the diffusion amount of each p-type impurity in the p-type channel stopper regions 24 and 25A and each n-type impurity in the n-type semiconductor region 29 and the n + -type semiconductor region 32. The dimensions should be taken into consideration.

A guard ring region (not shown) for preventing minority carriers generated from the normal substrate potential generating circuit (V _BB generator circuit) 1703 from entering the memory cell array 11E is arranged in the boundary region. The guard ring region is arranged around the memory cell array 11E and is constituted by the n-type semiconductor region 29 or the n + -type semiconductor region 32. The guard ring region is provided inside the memory cell array 11E (separated from the boundary region) inside the boundary regions of the p-type channel stopper regions 25A and 24. Above the guard ring region, a step reducing layer formed of the same conductive layer as the lower electrode layer 35, the upper electrode layer 37, or both layers of the information storage capacitor C of the stacked structure of the memory cell M is provided. Has been. This step reducing layer is used for the memory cell array 11E.
It is configured to reduce the shape of the step between the peripheral circuit and the peripheral circuit, improve the processing accuracy of the upper layer wiring such as the column select signal line 52 and the shunt word line 55, and reduce the disconnection defect.

Thus, the (8-5) p-type well region 2
The p-type well region 2 defined around the p-type channel stopper region formed on the main surface of the second non-active region.
The memory cells M and the n-channel MISFETs Qn of the peripheral circuits are respectively arranged on the main surfaces in the two different active regions.
In the DRAM 1, p surrounding the memory cell M
The p-type channel stopper region 25A and the p-type channel stopper region 24 surrounding the n-channel MISFET Qn of the peripheral circuit are independently configured in different manufacturing steps, and the p-type channel stopper region 25A and the p-type channel stopper region 24 are formed. In each boundary area of the memory cells M,
The active region Act such as the n-channel MISFETQn of the peripheral circuit is not arranged. With this configuration, the p-type channel stopper region 25A and the p-type channel stopper region 2 are formed.
When the four regions are separated from each other in the boundary region, a large n-type inversion layer corresponding to the area thereof is likely to be generated in the boundary region, and when the active region Act is present in the boundary region, it is formed in the active region Act. The area of the n-type semiconductor region 29 and the n + -type semiconductor region 32 apparently increases by the amount of the n-type inversion layer added, and the junction between the p-type well region 22 and the n-type semiconductor region 29 or the n + -type semiconductor region 32. Although the amount of leakage current increases in the active region Act in the boundary region.
Is not provided, the amount of leak current can be reduced at the junction. Further, when the p-type channel stopper region 25A and the p-type channel stopper region 24 overlap each other in the boundary region, the impurity concentration of the region increases, but the active region Act is not arranged in the boundary region. , Pn junction breakdown voltage between the p− type well region 22 and the n type semiconductor region 29 or the n + type semiconductor region 32 can be improved.

Next, a specific method for manufacturing the DRAM 1 described above will be briefly described with reference to FIGS.

First, a p-type semiconductor substrate 20 made of single crystal silicon is prepared.

(Well Forming Step) Next, a silicon oxide film 60 and a silicon nitride film 61 are formed on the main surface of the p − type semiconductor substrate 20.
Are sequentially laminated. The silicon oxide film 60 is about 900-
It is formed by a steam oxidation method at a high temperature of about 1000 [° C.] and has a film thickness of, for example, about 40 to 50 [nm]. This silicon oxide film 60 is used as a buffer layer. The silicon nitride film 61 is used as an impurity introduction mask and an oxidation resistant mask, respectively. The silicon nitride film 61 is deposited by, for example, a CVD method and is formed to have a film thickness of about 40 to 60 [nm].

Next, the silicon nitride film 61 in the n-type well region (21) forming region is removed to form a mask. mask
The formation of (61) is performed using a photolithography technique (a photoresist mask forming technique) and an etching technique.

Next, as shown in FIG. 16, the mask
Using (61), an n-type impurity 21n is introduced into the main surface portion of the p − type semiconductor substrate 20 through the silicon oxide film 60. As the n-type impurity 21n, for example, P with an impurity concentration of about 10 ¹³ [atoms / cm ² ] is used and is introduced by an ion implantation method with an energy of about 120 to 130 [KeV].

Next, using the mask (61), as shown in FIG. 17, a silicon oxide film 60 exposed from the mask is grown to form a silicon oxide film 60A thicker than that.
The silicon oxide film 60A is formed only in the n-type well region (21) forming region and is used as a mask for removing the mask (61) and an impurity introduction mask. Silicon oxide film 60
A is formed by a steam oxidation method at a high temperature of about 900 to 1000 [° C.], and finally 110 to 130, for example.
It is formed to have a film thickness of about [nm]. By the heat treatment process of forming the silicon oxide film 60A, the introduced n-type impurity 21n is slightly diffused.

Next, the mask (61) is selectively removed with, for example, hot phosphoric acid.

Then, as shown in FIG. 18, the silicon oxide film 60A is used as an impurity introduction mask, and the silicon oxide film 6 is formed.
A p-type impurity 22p is introduced into the main surface portion of the p-type semiconductor substrate 20 which has passed 0. The p-type impurity 22p is, for example, 1
B (or BF ₂ ) having an impurity concentration of about 0 ¹² to 10 ¹³ [atoms / cm ² ] is used, and ion implantation is performed with an energy of about 20 to 30 [KeV]. Since the p-type impurity 22p is formed so that the silicon oxide film 60A is thick, it is not introduced into the formation region of the n-type well region (21).

Next, each of the n-type impurity 21n and the p-type impurity 22p is stretched and diffused to form an n-type well region 21 and a p-type well region 22, as shown in FIG. The n-type well region 21 and the p-type well region 22 are formed by heat treatment in an atmosphere of a high temperature of about 1100 to 1300 [° C]. As a result, p-
The type well region 22 is formed in self-alignment with the n − type well region 21.

(Separation Region Forming Step) Next, each of the silicon oxide films 60 and 60A is removed, and the n--type well region 2 is formed.
1. Each main surface of the p-type well region 22 is exposed.

Next, as shown in FIG. 20, a silicon oxide film 62, a silicon nitride film 63, and a polycrystalline silicon film 6 are formed on the main surfaces of the n-type well region 21 and the p-type well region 22, respectively.
Each of 4 is sequentially laminated. The lower silicon oxide film 62 is used as a buffer layer.

The silicon oxide film 62 is, for example, about 900-
It is formed by a steam oxidation method at a high temperature of about 1000 [° C.] and has a film thickness of about 15 to 25 [nm]. The intermediate silicon nitride film 63 is mainly used as an oxidation resistant mask.
This silicon nitride film 63 is deposited by, for example, a CVD method,
It is formed with a film thickness of about 0 to 250 [nm]. The upper polycrystalline silicon film 64 is mainly used as an etching mask for the lower silicon nitride film 63, a trench depth determination mask, and a sidewall spacer length control mask. The polycrystalline silicon film 64 is deposited by, for example, a CVD method and is formed to have a film thickness of about 80 to 120 [nm].

Next, as shown in FIG. 21, the upper polycrystalline silicon film 64 on the main surface of each inactive region of the n-type well region 21 and the p-type well region 22 is removed to remove the active region. A mask is formed from the remaining polycrystalline silicon film 64. The mask 64 is formed by using photolithography and etching techniques. After forming the mask (64), the etching mask (photoresist film) formed by the photolithography technique is removed.

Next, as shown in FIG. 22, the mask
Using (64) as an etching mask, the silicon nitride film 63 exposed in the inactive region is removed, and a mask (63) is formed under the mask (64). The patterning of the mask (63) prevents contaminants from the photoresist film from being trapped in the main surfaces of the n-type well region 21 and the p-type well region 22 and in the silicon oxide film 62. Therefore, the mask (64) is used without using a photoresist film for patterning the mask (64).

Next, as shown in FIG. 23, the mask
(64) A silicon nitride film 65 and a silicon oxide film 66 are sequentially laminated on the entire surface of the substrate including the upper surface. The lower silicon nitride film 65 is
It is mainly used as an oxidation resistant mask and is formed with a film thickness smaller than that of the mask (63). This silicon nitride film 65
Is deposited by, for example, a CVD method and is formed to have a film thickness of about 15 to 25 [nm]. The upper silicon oxide film 66 is mainly used as an etching mask. This silicon oxide film 66 is
For example, it is deposited by a CVD method using an inorganic silane gas (SiH ₄ or SiH ₂ Cl ₂ ) and a nitric oxide gas (N ₂ O) as a source gas to have a film thickness of about 150 to 250 [nm].

Next, as shown in FIG. 24, anisotropic etching is performed by the amount corresponding to the film thickness deposited on each of the silicon oxide film 66 and the silicon nitride film 65, and the mask (63) and
Mask on each sidewall of (64) self-aligned with it
Form each of (65) and (66). This mask (65),
Each of (66) is formed as a so-called sidewall spacer.

Next, as shown in FIG. 25, the mask
Using each of (64) and (66) as an etching mask,
A shallow groove 67 is formed in the main surface of each inactive region of the n-type well region 21 and the p-type well region 22. The shallow groove 67 is
The depth of the lower surface of the element isolation insulating film (23) formed in a later step is formed deeper than the junction depth of the n-type semiconductor regions (29) and (32), for example, and the element isolation capability is increased. Is formed to increase the The depth of the shallow groove 67 is equal to that of the mask.
It is controlled by the film thickness of (64). That is, the shallow groove 67 is formed and the mask (64) is removed, and the mask (6
The reaction gas component of 4) is detected, and the etching for forming the shallow groove 67 is stopped at or near the time when the reaction gas component of the mask (64) is exhausted. The shallow groove 67 is, for example, RI.
It is formed by anisotropic etching such as E, and is about 80 to 120 [n
It is formed with a depth of about m].

Thus, (claim 3) a mask (6) formed of a material having an etching rate substantially equal to that of each of the n-type well region 21 and the p-type well region 22.
4) is used to mask the main surfaces of the inactive regions of the n-type well region 21 and the p-type well region 22 with the mask (64).
The shallow groove 67 is formed by etching by the amount corresponding to the film thickness.

With this structure, since the depth of the shallow groove 67 can be controlled by the film thickness of the mask (64), the controllability of the depth of the shallow groove 67 can be improved.

Next, the n-type well region 21 and the p-type well region 2 exposed by forming the shallow groove 67 are exposed.
A silicon oxide film 62A is formed on the main surface of each of the two inactive regions. This silicon oxide film 62A is used as a buffer layer when introducing impurities. The silicon oxide film 62A is formed by, for example, a thermal oxidation method and has a film thickness of about 8 to 12 [nm].

Then, as shown in FIG. 26, in the peripheral circuit formation region, the p-type impurity 2 is formed through the silicon oxide film 62A on the main surface portion of the inactive region of the p-type well region 22.
Introduce 4p. Each of the masks (63) and (66) and a photoresist mask (not shown) is used as an impurity introduction mask for introducing the p-type impurity 24p. p-type impurity 2
For 4p, for example, BF ₂ having an impurity concentration of about 10 ¹³ [atoms / cm ² ] is used, and ion implantation is performed with an energy of about 50 to 70 [KeV]. The p-type impurity 24p is introduced in the peripheral circuit forming region in a self-aligned manner with respect to the active region.

Next, each of the masks (63) and (65) is mainly used as an oxidation resistant mask, and the n--type well region 21 and
An element isolation insulating film (field insulating film) 23 is formed on the silicon oxide film 62A portion of the main surface of each inactive region of the p − type well region 22. At this time, the silicon oxide film 66 is removed with a hydrofluoric acid-based etching solution before forming the inter-element isolation insulating film 23. The insulating film 23 for element isolation is, for example, 1
Trace amount of oxygen at a very high temperature of about 050 to 1150 [℃]
(About 1% or less) in a nitrogen gas atmosphere containing about 30 ~
It can be formed by performing a heat treatment for 40 [minutes] and then oxidizing it for about 30 to 50 [minutes] by a steam oxidation method. The insulating film 23 for separating elements is, for example, 400 to 600.
It is formed with a film thickness of about [nm].

Since the mask (65) having a thin film thickness is brought into direct contact with the substrate at the end portion on the active region side of the inter-element isolation insulating film 23, it is moved in the lateral direction (active region side) at the initial stage of oxidation. Growth is reduced, and since the thick mask (63) can reduce the lateral growth even if oxidation progresses,
Birds beaks can be reduced. On the other hand, the thin mask 65 can be lifted up on the bird's beak as the oxidation progresses to relieve the stress and reduce the occurrence of defects. That is, the element isolation insulating film 23 is
It has few bird's beaks and can be formed with a large film thickness. Therefore, the insulating film 23 for element isolation can be formed with a size that is approximately equal to the size of the mask (63) for forming it, so that the isolation area between elements is reduced and the effective area of the active region is increased. be able to.

By the heat treatment for forming the inter-element isolation insulating film 23, the p-
P-type impurities 24 introduced in the main surface of the well region 22
p is expanded and diffused, and the p-type channel stopper region 24 is formed.
Is formed. The heat treatment diffuses the p-type impurities 24p in the lateral direction (active region side) as well, but since the n-channel MISFETQn of the peripheral circuit is larger than the size of the memory cell selecting MISFETQs of the memory cell M, The lateral diffusion amount of the impurities 24p is relatively small.
That is, the n-channel MISFET Qn is less affected by the sandwiched channel effect.

Next, the masks (63) and (65) and the silicon oxide film 62 are removed, and the n--type well region 21 and p--
The main surface of each active region of the mold well region 22 is exposed. Thereafter, as shown in FIG. 27, the exposed n-
A silicon oxide film 68 is formed on the main surfaces of the type well region 21 and the p-type well region 22, respectively. The silicon oxide film 68 is a silicon film formed on the end portion of the inter-element isolation insulating film 23 by each of the silicon nitride films (masks) 63 and 65 that are used mainly when forming the inter-element isolation insulating film 23. In order to oxidize the so-called white ribbon of so-called nitride. The silicon oxide film 68 is formed by a steam oxidation method at a high temperature of about 900 to 1000 [° C.], for example, and has a film thickness of about 40 to 100 [nm].

Next, as shown in FIG. 28, in the formation region of the memory cell array 11E, the p--type well region 22 is formed.
A p-type channel stopper region 25A and a p-type semiconductor region 25B are formed on the main surface of the. The p-type channel stopper region 25A is formed in the inactive region below the element isolation insulating film 23. The p-type semiconductor region 25B is formed in the active region where the memory cell M is formed. Each of the p-type channel stopper region 25A and the p-type semiconductor region 25B is
For example, it is formed by introducing B having an impurity concentration of about 10 ¹² to 10 ¹³ [atoms / cm ² ] by a high energy ion implantation method of about 200 to 300 [KeV]. In the main surface portion of the non-active region of the p − type well region 22, the p
The type impurities are introduced through the element isolation insulating film 23.
In the main surface portion of the active region, the p-type impurity is introduced at a deep position in the main surface portion of the p − type well region 22 by an amount corresponding to the film thickness of the element isolation insulating film 23. Each of the p-type channel stopper region 25A and the p-type semiconductor region 25B formed by this method is formed in self-alignment with the element isolation insulating film 23.

As described above, (1-1) p-type well region 2
DRAM 1 in which MISFETQs for memory cell selection are formed on the main surface in an active region surrounded by two inactive regions
In the step of forming a first mask in which the masks (63) and (64) are sequentially laminated on the main surface of the active region of the p-type well region 22, and the side wall of the first mask is formed on the first mask. Self-aligned mask of the first mask
Forming a second mask in which masks (65) and (66) each having a smaller film thickness than that of (63) are sequentially laminated;
The p-type well region 2 is formed by using a mask and a second mask.
The main surface of the second non-active region is subjected to etching treatment, and the p
A step of forming a shallow groove 67 in the non-active region of the − type well region 22 and a thermal oxidation process using the first mask and the second mask to form a main surface of the non-active region of the p − type well region 22. A step of forming an inter-element isolation insulating film (field insulating film) 23 on the upper surface of the p-type well region 22 and removing the first mask and the second mask; P-type impurities are introduced into the main surface of
And a step of forming the p-type channel stopper region 25A in the main surface portion of the p-type well region 22 below the element isolation insulating film 23. With this configuration, the lateral oxidation amount of the element isolation insulating film 23 can be reduced, so that the size of the element isolation insulating film 23 can be reduced and the film thickness thereof can be increased. By using the shallow groove 67, the position of the lower surface of the insulating film 23 for element isolation is deeper than the main surface of the active region of the p-type well region 22, and the separation dimension between the memory cell selecting MISFETs Qs is p-. Since it is possible to earn in the depth direction of the type well region 22, it is possible to enhance the isolation capability between the memory cell selecting MISFETs Qs, and to form the element isolation insulating film 23 to be thick.
The p-type impurity introduced into the main surface portion of the active region of the p-type well region 22 when the p-type impurity forming the p-type channel stopper region 25A is introduced is removed.
Since it can be introduced into a deeper position, the fluctuation of the threshold voltage of the memory cell selecting MISFET Qs due to the introduction of the p-type impurity can be reduced.

(4-2) Insulating film 2 for separating elements
The step of forming No. 3 is performed by a high temperature oxidation method in the range of about 1050 to 1150 [° C.]. With this structure, when forming the inter-element isolation insulating film 23, the fluidity of the silicon oxide film based on the high temperature oxidation method is promoted, and the inter-element isolation insulating film 23, the n-type well region 21, and the p-type are formed. Since the stress generated between the well region 22 and the main surface of each non-active region can be reduced, the main surface of each non-active region of the n-type well region 21 and the p-type well region 22 can be reduced. Shallow groove 6 formed on
It is possible to reduce the occurrence of crystal defects in the corner portions of No. 7.

The shallow trench 67 formed on the main surface of each of the inactive regions of the n-type well region 21 and the p-type well region 22 is used when crystal defects cannot be recovered or when it is not particularly necessary. Need not be formed. In this case, the mask
(64) is eliminated, and the film thickness of the mask (65) is set to 200 to 300.
[nm] may be used.

(5-3) The memory cell selection MISFET Qs forming the memory cell M and the n-channel MISFET Qn forming the peripheral circuit are respectively isolated by the insulating films 23 and p for element isolation in the p-type well region 22. In the DRAM 1 formed on the main surface of the active region in the region surrounded by the inactive region formed of the type channel stopper region,
MISF for selecting memory cells in the p-type well region 22
A p-type channel stopper region formed by introducing a p-type impurity into the main surface of the active region forming the ETQs and the non-active region surrounding the active region by passing the insulating film 23 for element isolation. 25A, and the p-type impurity 2 is formed on the main surface of the inactive region surrounding the active region of the p-type well region 22 forming the n-channel MISFET Qn.
5p is introduced to provide the p-type channel stopper region 24. With this configuration, the p-type channel stopper region 2
The threshold voltage of the parasitic MOS is increased at 5 A, and the memory cell M
And MISFETQs for selecting memory cells forming the same
Secures the separation ability between the memory cell M and the surrounding memory cell M,
Further, the p-type channel stopper region 25A is formed in self-alignment with the inter-element isolation insulating film 23, and the p-type impurity forming the p-type channel stopper region 25A has a small diffusion amount to the active region side. Therefore, the inter-channel effect of the memory cell selecting MISFET Qs can be reduced, and the p-type impurity 24p forming the p-type channel stopper region 24 is introduced only in the inactive region, so that the n-channel MISFET Qn can be formed. Since it is not introduced into the active region to be formed, it is possible to reduce the influence of the substrate effect and reduce the fluctuation of the threshold voltage of the n-channel MISFET Qn.

As described above, the n-channel MI
SFETQn is a memory cell selection MIS of the memory cell M
Since the size of the n-channel MISFET Qn is larger than that of the FET Qs, the diffusion amount of the p-type impurity 24p forming the p-type channel stopper region 24p toward the active region side is relatively small, and the inter-channel effect is almost generated. Absent.

Further, the n-channel MISFETQn
Does not introduce the p-type impurity 24p forming the p-type channel stopper region 24 into the active region, and the impurity concentration on the surface of the active region can be reduced, so that the threshold voltage is reduced and the drivability is improved. Can be increased. In particular,
The n-channel MISFET Qn can secure a sufficient output signal level when used as an output stage circuit.

(7-4) MISFETQs for memory cell selection of the memory cell M, n-channel MISFET
Each Qn is provided in the main surface portion of the p-type well region 22 having a higher impurity concentration than that of the p-type semiconductor substrate 20.
With this structure, the memory cell selecting MISFETQs and the n-channel MISFETQ of the p-type well region 22 are formed.
Since the impurity concentration of each channel forming region of n can be increased, the short channel effect can be reduced, and
The p-type well region 22 and the p-type semiconductor substrate 20
Since the potential barrier regions can be formed by the respective differences in the impurity concentrations, the α-ray soft error withstand voltage of the memory cell M can be particularly improved.

Further, the n-channel MISFET Qn
In the case where a direct peripheral circuit such as the column address decoder circuit (YDEC) 12 and the sense amplifier circuit (SA) 13 is formed, the α ray soft error withstand voltage can be similarly improved.

(Gate Insulating Film Forming Step) Next, the n-
A silicon oxide film 68A is formed on the main surfaces of the active regions of the type well region 21 and the p-type well region 22, respectively. The silicon oxide film 68A is formed again after removing the silicon oxide film 68. The silicon oxide film 68A may have a film thickness of about 15 to 24 [nm].

Next, as shown in FIG. 29, in the formation region of the peripheral circuit, the active regions defined by the element isolation insulating films 23 of the n-type well region 21 and the p-type well region 22, respectively. A p-type impurity 69p for adjusting the threshold voltage is introduced into the main surface portion of. The p-type impurity 69p is, for example, 10
Using B with an impurity concentration of about ¹² [atoms / cm ² ], 20 to 20
It is introduced by an ion implantation method with an energy of about 30 [KeV]. This p-type impurity 69p is mainly used for n-channel MISFE.
It is introduced to adjust the threshold voltage of each of TQn and Qp. Further, the p-type impurity 69p may be introduced into the respective main surface portions of the n-type well region 21 and the p-type well region 22 by separate steps.

Next, the silicon oxide film 68A is selectively removed to expose the main surfaces of the p-type well region 22 and the n-type well region 21, respectively.

Next, the exposed p-type well region 22,
The gate insulating film 2 is formed on each main surface of the n--type well region 21.
6 is formed. The gate insulating film 26 is 800 to 1000
It is formed by a steam oxidation method at a high temperature of about [° C],
It is formed with a film thickness of about 8 [nm].

(Gate Wiring Forming Step 1) Next, a polycrystalline silicon film is formed on the entire surface of the substrate including the gate insulating film 26 and the element isolation insulating film 23. The polycrystalline silicon film is CVD
Method, and a film thickness of about 200 to 300 [nm] is formed. An n-type impurity such as P that reduces the resistance value is introduced into the polycrystalline silicon film by a thermal diffusion method. After this,
A silicon oxide film (not shown) is formed on the surface of the polycrystalline silicon film by a thermal oxidation method. This polycrystalline silicon film is formed by the first-layer gate wiring forming process in the manufacturing process.

Next, an interlayer insulating film 28 is formed on the entire surface of the polycrystalline silicon film. The interlayer insulating film 28 is formed by a CVD method using inorganic silane gas and nitric oxide gas as source gases. The interlayer insulating film 28 is, for example, 240 to 350 [nm]
It is formed with a film thickness of about.

Next, as shown in FIG. 30, the interlayer insulating film 28 and the polycrystalline silicon film are sequentially etched using an etching mask (not shown) to form a gate electrode 27 and a word line (WL) 27. . In addition, the gate electrode 27,
An interlayer insulating film 28 is left on each of the word lines 27. The etching is anisotropic etching.

(Low Concentration Semiconductor Region Forming Step) Next, in order to reduce contamination due to the introduction of impurities, a silicon oxide film (no reference numeral is formed) is formed on the entire surface of the substrate. This silicon oxide film is a p-type well region 2 exposed by the etching.
2, formed on the respective main surfaces of the n-type well region 21 and on the side walls of the gate electrode 27 and the word line 27. The silicon oxide film is formed in an oxygen gas atmosphere at a high temperature of, for example, about 850 to 950 [° C.] and has a film thickness of about 10 to 20 [nm].

Next, using the inter-element isolation insulating film 23 and the interlayer insulating film 28 (and the gate electrode 27) as an impurity introduction mask, the memory cell array 11E and the n-channel MISF are formed.
In each of the ETQn forming regions, an n-type impurity 29n is introduced into the main surface portion of the p-type well region 22. The n-type impurity 29n is introduced in self alignment with the gate electrode 27. The n-type impurity 29n is, for example, 10 ¹³ [atoms / cm ² ].
Use P (or As) with an impurity concentration of about 30 to 50
It is introduced by an ion implantation method with an energy of about [KeV]. Although not shown, when the n-type impurity 29n is introduced, the formation region of the p-channel MISFET Qp is covered with an impurity introduction mask (for example, a photoresist film).

Next, as shown in FIG. 31, a p-channel MISFET is formed by using the inter-element isolation insulating film 23 and the interlayer insulating film 28 (and the gate electrode 27) as an impurity introduction mask.
In the formation region of Qp, p-type impurity 30p is introduced into the main surface portion of n-type well region 21. The p-type impurity 30p is self-aligned with the gate electrode 27. As the p-type impurity 30p, for example, B (or BF ₂ ) having an impurity concentration of about 10 ¹² [atoms / cm ² ] is used and is introduced by an ion implantation method with energy of about 20 to 30 [KeV]. Although not shown, when the p-type impurity 30p is introduced, the formation regions of the memory cell array 11E and the n-channel MISFET Qn are covered with an impurity introduction mask (photoresist film).

(High Concentration Semiconductor Region Forming Step 1) Next,
Sidewall spacers 3 are formed on the respective side walls of the gate electrode 27, the word line 27, and the interlayer insulating film 28 above them.
1 is formed. The sidewall spacers 31 can be formed by depositing a silicon oxide film and performing anisotropic etching such as RIE by an amount corresponding to the thickness of the deposited silicon oxide film. The silicon oxide film of the side wall spacer 31 has the same film quality as the interlayer insulating film 28, and is a CV having an inorganic silane gas and a nitric oxide gas as source gases.
It is formed by the D method. This silicon oxide film is, for example, 130-18
It is formed with a film thickness of about 0 [nm]. The length of the sidewall spacer 31 in the gate length direction (channel length direction) is about 15
It is formed at about 0 [nm].

Next, the n-channel MISFET of the peripheral circuit
In the Qn formation region, an n-type impurity 32n is introduced as shown in FIG. When introducing the n-type impurity 32n, the sidewall spacers 31 are mainly used as an impurity introduction mask. In addition, n-channel MISFETQ
A region other than the region where n is formed, that is, the memory cell array 1
Each of the 1E and p-channel MISFETQp forming regions is covered with an impurity introduction mask (photoresist film) (not shown) when the n-type impurity 32n is introduced. As the n-type impurity 32n, for example, As (or P) having an impurity concentration of about 10 ¹⁵ [atoms / cm ² ] is used, and 70 to 90 [Ke
It is introduced by an ion implantation method with an energy of about V].

Then, as shown in FIG. 33, heat treatment is performed to stretch and diffuse each of the n-type impurity 29n, the n-type impurity 32n, and the p-type impurity 30p, and the n-type semiconductor region 29, n +. Type semiconductor region 32, p type semiconductor region 30
To form each. The heat treatment is, for example, 900-100
It is performed at a high temperature of about 0 [° C.] for about 20 to 40 [minutes]. N
By forming the type semiconductor region 29, the memory cell M
The LDD structure memory cell selecting MISFET Qs is completed. Further, by forming the n-type semiconductor region 29 and the n + -type semiconductor region 32, the n-channel MISFET Qn having the LDD structure is completed. This n-channel MISF
The ETQn is used in the peripheral circuit (for low voltage) and the input / output stage circuit (for high voltage) of the DRAM 1. Also, p channel M
Although the p-type semiconductor region 30 forming the LDD structure of the ISFET Qp is completed, the p + -type semiconductor region 39 is formed after the memory cell M is completed, so that the p-channel MISFET is formed.
Qp is completed in a later process.

Thus, the n-channel MIS of the high voltage LDD structure used as the (13-7) input / output stage circuit.
FET Qn, LD for low voltage used as peripheral circuit
D having n-channel MISFET Qn of D structure
In the RAM 1, the high-voltage n-channel MISFET is formed on the main surface of the different active regions of the p-type well region 22.
Qn, the step of forming the gate insulating film 26 and the gate electrode 27 of each of the low-voltage n-channel MISFET Qn in the same manufacturing step, and the n-channel for high voltage n on the main surface portion of each active region of the p-type well region 22. Channel MISFETQ
n, a step of forming a low impurity concentration n-type semiconductor region 29 forming an LDD structure in self-alignment with each gate electrode 27 of the low-voltage n-channel MISFET Qn, and the high-voltage n-channel MISFETQ
forming side wall spacers 31 on the side walls of the gate electrodes 27 of the n-channel MISFET Qn for low voltage and the p-type well region 22.
N-channel MISFETQ for high voltage in the active region of
and n-type semiconductor regions 32 of high impurity concentration are formed in self-alignment with the side wall spacers 31 on the respective main surface portions of the n and low voltage n-channel MISFETs Qn. With this configuration, the high-voltage n-channel MI
Since the SFETQn and the low-voltage n-channel MISFETQn are all used in the same forming process, and especially the respective side wall spacers 31 can be formed in the same manufacturing process, the number of manufacturing processes of the DRAM 1 can be reduced.

(Interlayer Insulating Film Forming Step 1) Next, an interlayer insulating film 33 is formed on the entire surface of the substrate including the interlayer insulating film 28, the sidewall spacers 31 and the like. The interlayer insulating film 33 is used as an etching stopper layer when processing the respective electrode layers of the information storage capacitive element C having the stacked structure. The interlayer insulating film 33 is composed of the lower electrode layer (35) of the information storage capacitor C having a stacked structure, the gate electrode 27 of the memory cell selecting MISFET Qs, and the word line 2.
It is formed to electrically separate each of the seven.
Further, the interlayer insulating film 33 is configured to increase the film thickness of the sidewall spacer 31 of the p-channel MISFET Qp. The interlayer insulating film 33 is mainly formed to have a film thickness that allows for the amount of abrasion due to over-etching when processing the upper conductive layer, the amount of abrasion during the cleaning process, and the like. Interlayer insulation film 33
Is formed of a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitric oxide gas as source gases. That is, the interlayer insulating film 33 is the dielectric film (36) of the information storage capacitor C having the stacked structure or the underlying interlayer insulating film 28.
It is possible to reduce the stress generated between and due to the difference in linear expansion coefficient. The interlayer insulating film 33 is, for example, 130-1.
It is formed with a film thickness of about 80 [nm].

Next, as shown in FIG. 34, the memory cell M
The other n-type semiconductor region of the memory cell selecting MISFET Qs in the formation region (the lower electrode layer 3 of the information storage capacitor C)
The interlayer insulating film 33 on the side 29 to which 5 is connected) is removed to form connection holes 33A and 35, respectively. The connection hole 35 is formed in the side wall spacer 31 when the side wall spacer 31 and the interlayer insulating film 33 are etched.
Is formed in the region defined by each of the sidewall spacers 33B deposited on the sidewalls of the.

(Gate Wiring Forming Step 2) Next, as shown in FIG. 35, the lower electrode layer 35 of the information storage capacitive element C of the stacked structure of the memory cell M is formed on the entire surface of the substrate including the interlayer insulating film 33. A polycrystalline silicon film to be formed is deposited. Part of this polycrystalline silicon film is connected to the n-type semiconductor region 29 through each of the connection holes 33A and 35. This polycrystalline silicon film is formed of a polycrystalline silicon film deposited by the CVD method and has a film thickness of about 150 to 240 [nm]. This polycrystalline silicon film is formed by the gate wiring forming process of the second layer in the manufacturing process. An n-type impurity such as P that reduces the resistance value after deposition is introduced into the polycrystalline silicon film by a thermal diffusion method. A large amount of this n-type impurity is diffused into the n-type semiconductor region 29 through the connection hole 35,
The n-type impurity is introduced at a low impurity concentration so that the n-type impurity does not diffuse to the channel formation region side of the memory cell selection MISFET Qs.

Next, as shown in FIG. 36, a polycrystalline silicon film is further deposited on the polycrystalline silicon film. This upper polycrystal silicon film is deposited by the CVD method, and 240 to 350
It is formed with a film thickness of about [nm]. An n-type impurity such as P that reduces the resistance value after deposition is introduced into the upper polycrystalline silicon film by a thermal diffusion method. This n-type impurity is introduced at a high impurity concentration in order to improve the charge storage amount of the information storage capacitive element C having the stacked structure.

Then, as shown in FIG. 37, the lower layer electrode layer 35 is formed by processing the polycrystalline silicon film having the two-layer structure into a predetermined shape by using the photolithography technique and the anisotropic etching technique. The photolithography technique includes an etching mask (photoresist film) forming step and an etching mask removing step. The process of removing the etching mask is performed by, for example, Freon gas (CHF ₃ ) and oxygen gas (O ₂ ).
It is performed by a downstream plasma process using a mixed gas of. This process has an effect of reducing damage to each element of the DRAM 1.

As described above, (19-11) the DRAM in which the memory cell M is constructed by the series circuit of the MISFETQs for selecting a memory cell and the information storage capacitive element C of the stacked structure.
1, n of one of the memory cell selecting MISFETs Qs of the information storing capacitive element C of the stacked structure.
The lower electrode layer 35 on the side connected to the type semiconductor region 29,
It is composed of a composite film in which a polycrystalline silicon film introduced with an n-type impurity that reduces the resistance value to a low concentration and a polycrystalline silicon film introduced with the n-type impurity in a high concentration are sequentially laminated. With this configuration, the film thickness of the lower electrode layer 35 of the information storage capacitor C of the stacked structure of the memory cell M is increased, and the thickness of this film thickness is increased, so that the area of the side wall of the lower electrode layer 35 is increased in the height direction. Therefore, it is possible to increase the charge storage amount, reduce the area of the memory cell M, and improve the integration degree.
Since the impurity concentration on the surface of the upper polycrystalline silicon film of the lower electrode layer 35 is high, the charge storage amount can be increased and the degree of integration can be similarly improved.
Since the impurity concentration of the polycrystalline silicon film of No. 5 can be lowered and the diffusion amount of the n-type impurity toward the one n-type semiconductor region 29 side of the memory cell selection MISFET Qs can be reduced, the short MISFET Qs for memory cell selection. The channel effect can be reduced, the area of the memory cell M can be reduced, and the degree of integration can be further improved. In the present invention, the lower electrode layer 35 may be formed by depositing a polycrystalline silicon film with three or more layers and introducing an n-type impurity into each polycrystalline silicon film.

Further, (21-12) MI for memory cell selection
SFETQs and a stacked structure information storage capacitor C
In the DRAM 1 in which the memory cell M is formed by a series circuit of the memory cell M and the memory cell selection M in the p-type well region 22,
A step of depositing a first-layer polycrystalline silicon film over the entire surface of the interlayer insulating film 33 including the ISFET Qs, and then introducing an n-type impurity for reducing the resistance value into the first-layer polycrystalline silicon film; A step of depositing a second-layer polycrystalline silicon film over the entire surface of the first-layer polycrystalline silicon film, and then introducing an n-type impurity for reducing the resistance value into the second-layer polycrystalline silicon film. Then, predetermined patterning is sequentially applied to each of the second-layer polycrystalline silicon film and the first-layer polycrystalline silicon film by anisotropic etching to obtain the stacked-structure information storage capacitive element C.
And the step of forming the lower electrode layer 35. With this configuration, even if the film thickness of the lower electrode layer 35 of the information storage capacitive element C having the stacked structure is increased, the amount of impurities introduced therein is secured and made uniform to some extent. Can be increased and the etching rate can be increased. The improvement in the anisotropy of the anisotropic etching can reduce the size of the lower electrode layer 35, so that the area of the memory cell M can be reduced and the integration degree of the DRAM 1 can be improved.

(Dielectric Film Forming Step) Next, as shown in FIG. 38, a dielectric film 36 is formed on the entire surface of the substrate including the lower electrode layer 35 of the information storage capacitor C of the stacked structure of the memory cell M. Form. As described above, the dielectric film 36 is basically formed of a two-layer structure in which the silicon nitride film 36A and the silicon oxide film 36B are sequentially stacked. The lower silicon nitride film 36A is deposited by, for example, a CVD method,
It is formed with a film thickness of about [nm]. When forming the silicon nitride film 36A, entrapment of oxygen is suppressed as much as possible. When the silicon nitride film 36A is formed on the lower electrode layer 35 (polycrystalline silicon film) at a normal production level, an extremely small amount of oxygen is entrapped, so that the lower electrode layer 35 and the silicon nitride film 3 are formed.
A native silicon oxide film (not shown) is formed between 6A and 6A.

A silicon oxide film 36 as an upper layer of the dielectric film 36.
B is formed by subjecting the lower silicon nitride film 36A to a high-pressure oxidation method to have a film thickness of about 1 to 3 [nm]. When the silicon oxide film 36B is formed, the film thickness of the lower silicon nitride film 36A is slightly reduced. The silicon oxide film 36B is basically 1.5-1.
It is formed in an oxygen gas atmosphere at a high pressure of 0 [toll] and a high temperature of about 800 to 1000 [° C.]. In this embodiment, the silicon oxide film 36B has a high pressure of 3 to 3.8 [toll] and an oxygen flow rate (source gas) of 2 [l / min] and a hydrogen flow rate (source gas) of 3 to 3 during oxidation. It is formed as 8 [l / min]. The silicon oxide film 36B formed by the high pressure oxidation method has a normal pressure.
The desired film thickness can be formed in a shorter time than the silicon oxide film formed by (1 [toll]). In other words, the high-pressure oxidation method can shorten the heat treatment time at high temperature,
The pn junction depth of the source region and the drain region of the memory cell selecting MISFET Qs or the like can be made shallow.
The native silicon oxide film can be thinned by reducing the entrainment of oxygen. Although the number of manufacturing steps increases, the native silicon oxide film may be nitrided to form the dielectric film 36 with a two-layer structure.

(Gate Wiring Forming Step 3) Next, a polycrystalline silicon film is deposited on the entire surface of the substrate including the dielectric film 36.
The polycrystalline silicon film is deposited by the CVD method,
It is formed with a film thickness of about [nm]. This polycrystalline silicon film is formed by the gate wiring forming process of the third layer in the manufacturing process. After that, an n-type impurity such as P for reducing the resistance value is introduced into the polycrystalline silicon film by a thermal diffusion method.

Next, MISFETQs for memory cell selection
An etching mask is formed on the polycrystalline silicon film over the entire surface of the memory cell array 11E except for the connection region between one of the n-type semiconductor regions 29 and the complementary data line (50). The etching mask is formed of, for example, a photoresist film using a photolithography technique. After this,
As shown in FIG. 9, the polycrystalline silicon film and the dielectric film 36 are sequentially anisotropically etched using the etching mask to form an upper electrode layer 37. By forming the upper electrode layer 37, the information storage capacitive element C having a stacked structure is substantially completed, and as a result, the memory cell M of the DRAM 1 is completed. After completion of the memory cell M, the etching mask is removed.

Next, as shown in FIG. 40, a thermal oxidation process is performed to form an insulating film (silicon oxide film) 38 on the surface of the upper electrode layer 37. The step of forming the insulating film 38 is performed by patterning the upper electrode layer 37, and
This is a step of oxidizing the etching residue (polycrystalline silicon film) remaining on the surface of the interlayer insulating film 33. The stacked information storage capacitor C is a memory cell selection MISFE.
Two lower electrode layers 35 and an upper electrode layer 3 on top of TQs
Since 7 is deposited, the step shape is large, particularly the step shape of the connecting portion between the complementary data line (50) and the memory cell M is large, and etching residue is likely to occur. This etching residue short-circuits the complementary data line (50) and the upper electrode layer 37.

As described above, (22-13) one n-type semiconductor region 29 is connected to the complementary data line (50), the memory cell selecting MISFET Qs, the lower electrode layer 35 formed on the upper layer, Information storage capacitor C having a stacked structure in which a body film 36 and an upper electrode layer 37 are sequentially stacked.
In the DRAM 1 in which the memory cell M is formed by a series circuit with the above, a polycrystalline silicon film is deposited on the dielectric film 36 of the memory cell M by the CVD method, and a predetermined pattern is formed on the polycrystalline silicon film by anisotropic etching. And a step of forming an insulating film 38 (silicon oxide film) by a thermal oxidation method on the surface of the upper electrode layer 37. With this configuration, the etching residue of the polycrystalline silicon film remaining on the stepped portion of the underlying surface after the patterning of the polycrystalline silicon film can be oxidized by the thermal oxidation step performed thereafter, so that the upper electrode layer 37 is formed. And a complementary data line (50) can be prevented from being short-circuited, and the manufacturing yield can be improved.

(Highly Concentrated Semiconductor Region Forming Step 2) Next,
In the formation region of the p-channel MISFET Qp of the peripheral circuit, the interlayer insulating film 33 formed in the above process is anisotropically etched to form the sidewall spacer 33C as shown in FIG. The sidewall spacers 33C are formed on the sidewalls of the sidewall spacers 31 and are self-aligned with the gate electrodes 27. The sidewall spacer 33C is formed so as to increase the dimension of the sidewall spacer 31 of the p-channel MISFET Qp in the gate length direction. The total dimension of the sidewall spacers 31 and 33C in the gate length direction is about 200 [nm] as described above.

Next, the n-channel MISFET is formed on the upper electrode layer 37 of the information storage capacitor C having the stacked structure.
An insulating film (not shown) is formed on the entire surface of the substrate including Qn and the p-channel MISFET Qp forming region. This insulating film is mainly used as a contamination prevention film when introducing impurities. This insulating film is formed of, for example, a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitric oxide gas as a source gas, and has a thin film thickness of about 10 nm.

Next, the p-channel MISFET of the peripheral circuit
In the Qp forming region, p-type impurity 39p is introduced as shown in FIG. When introducing the p-type impurity 39p, the sidewall spacers 31 and 33C are mainly used as an impurity introduction mask. Also, p-channel MISF
Regions other than the formation region of the ETQp, that is, the formation regions of the memory cell array 11E and the n-channel MISFET Qn are covered with an impurity introduction mask (photoresist film) not shown when introducing the p-type impurity 39p. As the p-type impurity 39p, for example, BF ₂ (or B) having an impurity concentration of about 10 ¹⁵ [atoms / cm ² ] is used, and 50 to 70 [KeV].
It is introduced by an ion implantation method with a certain level of energy.

After that, heat treatment is performed to expand and diffuse the above-mentioned p-type impurity 39p to form a p + -type semiconductor region 39. The heat treatment is performed at a high temperature of about 900 to 1000 [° C.] for about 20 to 40 [min]. By forming the p + type semiconductor region 39, the p-channel MISFET Qp having the LDD structure is completed. This p-channel MI
The SFET Qp is subjected to a heat treatment (for example, the dielectric film 36) for increasing the size of the sidewall spacer 31 in the gate length direction with the sidewall spacer 33C and forming the stacked information storage capacitive element C of the memory cell M. Later formed. That is, p channel MISFE
TQp can reduce the diffusion of the p + type semiconductor region 39 toward the channel formation region side and reduce the short channel effect.

As described above, (17-9) the memory cell M composed of the series circuit of the memory cell selection MISFET Qs and the information storage capacitor C of the stacked structure, and the complementary MISFET of the LDD structure which constitutes the peripheral circuit. In the DRAM 1, each of which includes a memory cell selection MISFET of the memory cell M and an n channel M of the peripheral circuit.
The steps of sequentially forming the gate insulating film 26 and the gate electrode 27 of the ISFET Qn and the p-channel MISFET Qp, respectively, and the memory cell selection MISFET Qs and the n-channel MI in self-alignment with the gate electrode 27.
L of each of SFETQn and p-channel MISFETQp
Low impurity concentration n-type semiconductor region 2 forming a DD structure
9, the step of forming each of the p-type semiconductor regions 30, the memory cell selecting MISFET Qs, and the n-channel MIS
The step of forming the side wall spacer 31 on the side wall of the gate electrode 27 of each of the FET Qn and the p channel MISFET Qp, and the n + type semiconductor region 32 of the high impurity concentration of the n channel MISFET Qn by self-alignment with the side wall spacer 31. And a stacked element information storage capacitive element C of the memory cell M.
And a sidewall spacer 3 on the sidewall of the gate electrode 27 of the p-channel MISFET Qp.
1 to form the side wall spacer 33C in self-alignment with the gate electrode 27, and the p + type semiconductor region of the high impurity concentration of the p-channel MISFET Qp in self-alignment with the side wall spacer 33C. Forming 39. With this configuration, the n-channel MISFET Qn defines the dimension in the gate length direction of the low-impurity-concentration n-type semiconductor region 29 forming the LDD structure with the single-layer sidewall spacer 31. The dimension of 29 in the gate length direction can be shortened, and the p-channel MIS
The FET Qp has a plurality of layers of sidewall spacers 31,
33C defines the amount of the high-impurity-concentration p + -type semiconductor region 39 sneaking into the channel formation region side, and the high-impurity-concentration is applied after the heat treatment for forming the stacked information storage capacitor C of the memory cell M. Since the p + type semiconductor region 39 is formed,
It is possible to further reduce the amount of sneak into the channel formation region side.

(18-10) The n-channel MIS
After the step of forming the high impurity concentration n + type semiconductor region 32 of the FET Qn and before the step of forming the stacked information storage capacitor element C of the memory cell M, a step of forming an interlayer insulating film 33 is provided. After forming the interlayer insulating film 33, the sidewall spacers 33C are formed using the interlayer insulating film 33. With this configuration, part of the process of forming the sidewall spacer 33C
Since the (film deposition step) can be combined with the step of forming the interlayer insulating film 33, the DR film can be combined with this step.
The number of manufacturing steps of AM1 can be reduced.

(Interlayer insulating film forming step 2) Next, the DR
An interlayer insulating film 40 is laminated on the entire surface of the substrate including each element of AM1. The interlayer insulating film 40 is formed of, for example, a silicon oxide film deposited by a CVD method using an inorganic silane gas and a nitric oxide gas as source gases. The interlayer insulating film 40 is formed with a film thickness of about 250 to 350 [nm], for example.

Next, as shown in FIG. 43, the memory cell M
A connection hole 40A is formed in the interlayer insulating film 40 at a connection portion between the complementary data line 50 and the complementary data line 50. This connection hole 4
0A is formed by anisotropic etching, for example.

(Gate Wiring Forming Step 4) Next, as shown in FIG. 44, it is connected to one of the n-type semiconductor regions 29 of the memory cell selecting MISFET Qs through the connection hole 40A and extends over the interlayer insulating film 40. Complementary data line (DL)
Form 50. The complementary data line 50 is formed in the gate wiring forming process of the fourth layer in the manufacturing process. The complementary data line 50 has a two-layer structure in which a polycrystalline silicon film 50A and a transition metal silicide film 50B are sequentially stacked. The lower polycrystalline silicon film 50A is deposited by the CVD method,
For example, it is formed with a film thickness of about 80 to 120 [nm]. An n-type impurity such as P is introduced into the polycrystalline silicon film 50A by thermal oxidation after deposition. Since the polycrystalline silicon film 50A deposited by the CVD method has a high step coverage in the step-shaped portion of the connection hole 40A, disconnection defects of the complementary data line 50 can be reduced.

Further, in the connection portion between the memory cell M and the complementary data line 50, due to the mask misalignment in the manufacturing process of the connection hole 40A and the element isolation insulating film 23, the element isolation insulating film 23 is formed. When a part of the connection hole 40A is formed above, the n-type impurity is diffused from the polycrystalline silicon film 50A to the main surface portion of the p-type well region 22 to connect the n-type semiconductor region 29 and the complementary data line 50. Therefore, short circuit between the complementary data line 50 and the p-type well region 22 can be prevented. The upper transition metal silicide film 50B is formed of, for example, a WSi ₂ film deposited by a CVD method and has a film thickness of about 100 to 200 [nm]. The upper layer transition metal silicide film 50B is formed mainly for reducing the resistance value of the complementary data line 50B and increasing the speed of each of the information writing operation and the information reading operation. The upper transition metal silicide film 50B is CV
Since the deposition is performed by the D method, the disconnection failure of the complementary data line 50 can be further reduced.

The complementary data line 50 is formed by depositing the lower polycrystalline silicon film 50A and the upper transition metal silicide film 50B, and then patterning them into a predetermined shape by, for example, anisotropic etching. There is.

(Interlayer insulating film forming step 3) Next, an interlayer insulating film 51 is formed on the entire surface of the substrate including the above-mentioned complementary data lines 50. The interlayer insulating film 51 is made of silicon oxide film 51A and BPSG.
The film 51B has a two-layer structure in which the films 51B are sequentially stacked. The lower silicon oxide film 51A is deposited by, for example, a CVD method using an inorganic silane gas and a nitric oxide gas as source gases, and is formed to have a film thickness of about 100 to 200 [nm]. The lower silicon oxide film 51A is formed to prevent leakage of impurities (P and B) from the upper BPSG film 51B. The upper BPSG film 51B is deposited by, for example, a CVD method and has a film thickness of about 250 to 350 [nm]. The BPSG film 51 is subjected to a flow at a temperature of about 800 [° C.] or higher in a nitrogen gas atmosphere to have its surface flattened.

Next, as shown in FIG. 45, a connection hole 51C is formed in the interlayer insulating film 51. The connection hole 51C is D
On the n + type semiconductor region 32, the p + type semiconductor region 39, the wiring 50 not shown, and the upper electrode layer 3 of each element of the RAM 1.
7 is formed by removing the upper interlayer insulating film 51 such as above. The connection hole 51C is formed by anisotropic etching, for example.

Further, in the formation region of the p-channel MISFET Qp, the p + type semiconductor region 39 has a large diffusion coefficient of the p type impurity, so that the impurity concentration on the surface becomes thinner than that of the n + type semiconductor region 32. Further, in the p + type semiconductor region 32, a region having a high impurity concentration on the surface is etched by over-etching when forming the connection hole 51C, and the impurity concentration on the surface is further lowered. Also,
Since the wiring 52 connected to the p + type semiconductor region 39 is formed of a transition metal film (W film), the work function difference becomes larger than that of the n + type semiconductor region 32. Therefore, the p-channel MISFET Qp is formed on the surface of the p + type semiconductor region 39 in the region defined by the connection hole 51C.
A type impurity may be introduced to increase the impurity concentration on the surface of the p + type semiconductor region 39. With this structure, the p + type semiconductor region 39 of the p channel MISFET Qp and the wiring (52)
The connection resistance value with can be reduced.

(Wiring Forming Step 1) Next, as shown in FIG. 46, the n + type semiconductor region 3 is formed through the connection hole 51C.
2, a wiring (including a column select signal line) 52 on the interlayer insulating film 51 so as to be connected to the p + type semiconductor region 39 and the like.
To form. The wiring 52 is formed of a transition metal film such as a W film deposited by a sputtering method, and is, for example, 350 to 450 [nm].
It is formed with a film thickness of about. The wiring 52 can be formed by depositing on the entire surface of the interlayer insulating film 51 and then patterning it into a predetermined shape by, for example, anisotropic etching.

(Interlayer Insulating Film Forming Step 4) Next, as shown in FIG. 47, an interlayer insulating film 53 is formed on the entire surface of the substrate including the wiring 52. The interlayer insulating film 53 includes a silicon oxide film (deposition type insulating film) 53A and a silicon oxide film (coating type insulating film) 53.
B, a silicon oxide film (deposition type insulating film) 53C are sequentially laminated to form a three-layer structure. Lower layer silicon oxide film 5
3A is deposited by a C-CVD method using tetraepoxysilane gas as a source gas, and is formed with a film thickness of about 250 to 350 [nm]. The intermediate silicon oxide film 53B is the interlayer insulating film 5
It is formed to flatten the surface of No. 3. The silicon oxide film 53B is applied several times (2 to 5 times) by the SOG method (applied to a total film thickness of about 100 to 150 [nm]), and then baked (about 450 [° C.]). It is formed by retreating the surface by etching.

Due to the receding by the etching, the silicon oxide film 53B is formed only in the concave portion of the step shape on the surface of the lower silicon oxide film 53A. Further, the middle layer of the interlayer insulating film 53 may be formed of an organic film such as a polyimide resin film instead of the silicon oxide film 53B. The upper silicon oxide film 53C is deposited by, for example, a C-CVD method using tetraepoxysilane gas as a source gas in order to increase the strength of the interlayer insulating film 53 as a whole, and is 250 to 350 [nm].
It is formed with a film thickness of about.

Next, the predetermined wiring 53 of the interlayer insulating film is removed to form a connection hole 53D. The connection hole 53D is formed by anisotropic etching, for example.

Next, the transition metal film 54 is laminated (embedded) on the surface of the wiring 52 exposed in the connection hole 53D. The transition metal film 54 is formed of, for example, a W film deposited by the selective CVD method, and has a film thickness of about 600 to 800 [nm].
The reaction generation formula of this W film is as follows.

[0187]

[Equation 1]

(Wiring Forming Step 2) Next, as shown in FIG. 49, the transition metal film 54 embedded in the connection hole 53D.
A wiring (including a shunt word line) 55 is formed on the interlayer insulating film 53 so as to be connected to. The wiring 55 has a two-layer structure in which a transition metal nitride film (or a transition metal film) 55A and an aluminum alloy film 55B are sequentially stacked. The lower transition metal nitride film 55A is formed of, for example, a TiN film deposited by a sputtering method, and has a film thickness of about 130 to 180 [nm]. This transition metal nitride film 55A is
As described above, the connection hole 53D is configured to prevent the precipitation phenomenon of Si and the alloying reaction between W and aluminum. Upper layer aluminum alloy film 55B
Is deposited by, for example, a sputtering method, and is 600 to 800 [nm].
It is formed with a film thickness of about. The wiring 55 can be formed by sequentially stacking the lower layer transition metal silicide film 55A and the upper layer aluminum alloy film 55B, and then patterning them into a predetermined shape by, for example, anisotropic etching.

(Passivation Film Forming Step) Next, as shown in FIG. 1, a passivation film 56 is formed on the entire surface of the substrate including the wiring 55. As described above, the passivation film 56 is formed of a composite film in which the silicon oxide film 56A and the silicon nitride film 56B are sequentially stacked. The lower silicon oxide film 56A is deposited by the C-CVD method using the tetraepoxysilane gas as the source gas as described above. The upper silicon nitride film 56B is deposited by the plasma CVD method.

Although not shown in FIG. 1, a resin film is applied to the upper layer of the passivation film 56.
This resin film is formed in order to improve the α-ray soft error withstand voltage. This resin film is, for example, a polyimide resin film applied by a potting technique (including a resin dropping application process, a baking process, and a patterning process), and is formed to have a film thickness of about 8 to 12 [μm]. There is. The resin film basically has openings at positions corresponding to the external terminals, and is applied to the entire surface of the DRAM 1 except this region.

Further, this resin film may be arranged in a plurality of divided shapes on the surface of the DRAM 1. That is, the resin film is arranged in each of the regions where the α-ray soft error withstand voltage of the DRAM 1 is desired to be secured, for example, the memory cell array 11E and a part (12 and 13) of the direct peripheral circuit. This area is used as a divided area without being placed in a section. By thus dividing the resin film, the stress of the resin film can be reduced, and cracks and the like of the passivation film can be prevented.

(Fuse Opening Step) Further, the DRAM
Defect complementary data line (DL) 50, defective word line 1
A Y-system redundant circuit 1812 and an X-system redundant circuit 1806 for relieving each of the (WL) 27 (or the shunt word line 55) are arranged. This Y-system redundant circuit 1812 is
Defect complementary data line 50 to redundant complementary data line 50
The switching to is performed depending on whether or not the fuse element F is cut. Similarly, the X-system redundancy circuit 1806 operates on the defective word line 2
Switching from 7 to the redundant word line 27 is performed depending on whether or not the fuse element F is cut.

The fuse element F is formed of the same conductive layer as the complementary data line 50 and the wiring 50, as shown in FIG. Since the DRAM 1 of this embodiment adopts the laser cutting method, the fuse element 50
Is cut by laser light. Since the fuse element 50 becomes unstable in cutting when the passivation film 56 having a large film thickness is present, the fuse opening 56C formed in the passivation film 56 is provided above the fuse element 50. Since the etching gas used for opening the fuse opening 56C is also the etching gas for etching the fuse element 50, an appropriate film thickness of the interlayer insulating film 51 and the interlayer insulating film 53 (800) is formed on the fuse element 50.
An insulating film having a thickness of [nm] or less is left. The lower conductive layer of the fuse element 50, for example, the same conductive layer as the upper electrode layer 37 of the information storage capacitive element C having a stacked structure, has a small film thickness and thus has a high resistance value, which is not preferable as the fuse element F. Further, since the same conductive layer as each of the lower electrode layer 35 and the gate electrode 27 has a large number of insulating films above it, the number of steps for forming the fuse opening becomes large and complicated. In addition, the wiring 5 in the upper layer of the fuse element 50
Since the same conductive layers as 2, 55 have a property of reflecting laser light, they are not preferable as the fuse element F.

This fuse element 50 and fuse opening 5
A method of forming 6C will be briefly described with reference to FIGS. 51 to 53 (sectional views of the essential part shown in each manufacturing step).

First, as shown in FIG. 51, the interlayer insulating film 4 is formed.
The complementary data line 50 is formed on the formation region of the fuse element F of 0.
The fuse element 50 is formed in the same manufacturing process as described above.

Next, the interlayer insulating film 51 (51A and 51B)
And then, the wiring 52 is formed as shown in FIG. As shown in FIG. 52, the wiring 52 does not exist on the fuse element 50.

Next, the interlayer insulating film 53 (53A, 53B and 53C) is formed, and thereafter, the wiring 55 is formed as shown in FIG. Wiring 5 is provided on the fuse element 50.
5 does not exist.

Next, a passivation film 56 is formed,
As shown in FIG. 50, a fuse opening 56C is formed in the passivation film 56 on the fuse element 50. Although not described, the fuse opening 56C can be formed in the same manufacturing process as the process of opening the (bonding) portion of the passivation film 56 where the external terminal BP exists.

Thus, the memory cell selection MI is provided at the intersection of the (38-23) complementary data line 50 and the word line 27.
SFETQs and a stacked structure information storage capacitor C
A memory cell M formed by a series circuit of the above and a redundant fuse element for laser cutting 50 for repairing the defective complementary data line 50 or the defective word line 27 of the complementary data line 50 or the word line 27. In the DRAM 1, the complementary data line 50 is composed of a composite film in which a polycrystalline silicon film 50A deposited by a CVD method and a transition metal silicide film 50B are sequentially laminated, and the redundant fuse element 50 for laser cutting is complemented. The same conductive layer as the characteristic data line 50 is used.

With this configuration, the complementary data line 50 is
Is a MISFET Q for selecting a memory cell of the memory cell M
s and the stacked information storage capacitive element C, the number of layers of insulating films in the upper layer of the laser cutting redundant fuse element 50 is reduced, so that the laser cutting redundant fuse element 50 is formed. The opening process of the upper insulating film can be simplified, and the composite film formed of the polycrystalline silicon film 50A and the transition metal silicide film 50B has a laser beam absorptivity formed on the complementary data line 50. Since it is higher than the wirings 52 and 55, respectively, the redundant fuse element 50 for laser cutting can be easily and reliably cut.

The DRAM 1 of this embodiment is completed by carrying out the series of steps of forming the passivation film 56 and the openings therein.

Next, in the manufacturing process of the DRAM 1 described above, the manufacturing process of each main part will be described in detail.

(Step of forming wiring / connection hole) DRA described above
In the method of manufacturing M1, the complementary data line (DL) 50,
Each of the wiring 52, the wiring 55, and the connection holes 40A, 51C, and 53D is basically processed by a photolithography technique using a multilayer resist mask. This multilayer resist mask is a non-photosensitive resin film (organic film such as polyimide resin film),
Intermediate film (inorganic film such as silicon oxide film applied by SOG method),
The photosensitive resin film is formed, for example, in a three-layer structure in which the photosensitive resin films are sequentially laminated.

The multilayer resist mask alleviates the step shape grown by the multilayer structure mainly in the lower layer film and the intermediate film,
It is used for the purpose of improving the processing accuracy of the upper photosensitive resin film and the processing accuracy of the material to be etched. The multilayer resist mask is formed by the following method.

First, a non-photosensitive resin film, an intermediate film, and a photosensitive resin film are sequentially laminated on the surface of a material to be etched (for example, the complementary data line 50, etc.) to form a multilayer resist film.

Next, the photosensitive resin film as the upper layer of the multilayer resist film is processed by ordinary exposure processing and phenomenon processing to form an etching mask.

Next, using the etching mask, the intermediate film of the multilayer resist film and the non-photosensitive resin film are sequentially patterned by anisotropic etching to form a multilayer resist mask. In this patterning, the lower non-photosensitive resin film is oxygen (O ₂ ) gas and halogen (Cl ₂ , Br _2).
Etc.) patterning by anisotropic etching technique using gas. As the etching device, for example, a reactive ion etching (RIE) device, a magnetron type RIE device or a μ wave ECR device is used. The etching pressure is, for example, about 1 to 10 [mtoor], and the high frequency output is 0.25 to 30.
Use about [W / cm ² ]. Further, the halogen gas used in the anisotropic etching does not use solid halogen such as vinyl chloride placed in a vacuum chamber and use halogen gas as an outgas of this vinyl chloride (a halogen compound is simultaneously generated). , To the inside of the vacuum chamber from the outside.

The anisotropic etching gas of oxygen gas and halogen gas produces carboxylic acid when the lower non-photosensitive resin film is etched with oxygen gas, and has a lower vapor pressure when halogen gas is added to this carboxylic acid. Since the acid chloride is generated, the generated gas escapes favorably and the side etching amount of the lower non-photosensitive resin film can be reduced.

Thus, the multilayer resist film is formed in a three-layer structure, and the lower non-photosensitive resin film among them is patterned by anisotropic etching using oxygen gas and halogen gas. With this configuration, since halogen gas is used as the anisotropic etching gas, the side etching amount of the lower non-photosensitive resin film can be reduced and the processing accuracy can be improved. Since halogen compounds (CF ₄ , CCl ₄ ) are not used as the organic compound, it is possible to prevent organic substances from adhering to the patterned side surface of the lower non-photosensitive resin film. The prevention of the adhesion of the organic substances can reduce the removal process and also reduce the contamination of the inner wall of the vacuum chamber of the etching apparatus. Further, it is possible to reduce the contamination attached to the inner wall of the vacuum chamber, and to reduce the reattachment of the organic substances dropped from the inner wall to the surface of the semiconductor wafer during the manufacturing process, thus improving the manufacturing yield. it can.

Since no halogen compound, especially carbon (C), is used as the anisotropic etching gas, the anisotropic etching rate can be increased.

Further, since the anisotropic etching uses the pure halogen gas from the outside of the vacuum chamber without using the halogen gas as the solid outgas, the same effect as described above can be obtained.

(Wiring Forming Step 1) In the manufacturing method of the DRAM 1 described above, the processing accuracy of the wiring 52, that is, the W film can be improved by adopting low temperature anisotropic etching.

Anisotropic etching for processing the wiring 52 is performed in a vacuum chamber such as an RIE device. The inside of the vacuum chamber is usually maintained at a vacuum degree in the range of 10 ² to 10 ³ [torr], and anisotropic etching is performed in this state. As shown in FIG. 54 (a diagram showing the relationship between the temperature and vapor pressure of tungsten hexafluoride WF ₆ ), WF ₆ has a vapor pressure with respect to the degree of vacuum in the vacuum chamber at a low temperature of about −40 [° C.] or less. Becomes 0 [mtorr] or close to it. That is, by performing anisotropic etching in the low temperature region, the wiring 52 is not vaporized because the ions do not collide with the processed side wall, and the ions collide with the bottom surface during processing and are vaporized. The anisotropy of can be improved. As a result, the processing accuracy of the wiring 52 can be improved.

(Connecting Hole Forming Step) In the manufacturing method of the DRAM 1 described above, each of the connecting holes 51C (or 53D) can be formed in a tapered shape by using a magnetron RIE device or a μ wave ECR device.

The connecting hole 51C can control the taper angle (the step difference angle of the connecting hole) by controlling the etching pressure, the etching gas flow rate or the high frequency output among the etching conditions. In order to control the taper angle without impairing the etching performance, it is desirable to control the etching pressure or the etching gas flow rate. The etching rate of anisotropic etching is determined by the product of ion current and average ion energy, and when the ion current is constant, the taper angle is determined by average ion energy. On the other hand, the ion current is proportional to the high frequency output, and when the high frequency output is constant, it tends to be inversely proportional to the voltage Vdc between the semiconductor wafer (electrode) and the plasma.

As shown in the relationship between etching pressure and energy in FIG. 55 (A), anisotropic etching using the RIE apparatus has a narrow stable discharge region with respect to etching pressure and a sharp change in voltage Vdc. Moreover, the change in average ion energy is rapid. That is, the controllability of the taper angle is poor.

On the other hand, as shown in the relationship between etching pressure and energy in FIG. 55 (B), anisotropic etching using a magnetron RIE device (or μ-wave ECR device) is 1-2. Since the amount of ions is large in the order of magnitude, the stable discharge region with respect to the etching pressure becomes wide. Therefore, as shown in FIG. 55 (C) showing the relationship between the ion energy and the etching rate, and FIG. 55 (D) showing the relationship between the ion energy and the taper angle, the controllability of the taper angle becomes high. The etching rate of the step portion is the etching rate determined by the ion energy corresponding to cos θ times the ion energy of the flat portion. This is because the ion current density in the step portion having the taper angle θ corresponds to cos θ times the ion current density in the flat portion. As the taper angle θ approaches 90 degrees, the stepped portion of the connection hole becomes steeper and the taper angle θ becomes 0.
The level difference is alleviated as it approaches.

As described above, by forming the connection hole 51C by anisotropic etching using the magnetron RIE device (or μ-wave ECR device), the stable discharge region with respect to the etching pressure is widened, and the change of the voltage Vdc, the average Since each change in ion energy can be reduced, controllability of the taper angle can be improved without impairing etching performance. That is, as shown in FIG. 55 (D),
The taper angle can be easily formed without varying from 60 to 80 degrees. As a result, since the connecting hole 51C can be formed in a tapered shape, it is possible to reduce disconnection defects of the wiring 52 in the step portion of the connecting hole 51C. It should be noted that the connection hole 53D has no problem because the transition metal film 54 is embedded in the present embodiment, but if it is not embedded, a tapered shape is similarly provided.

(Connecting Hole Forming Step) In the method of manufacturing the DRAM 1 described above, the insulating film such as the connecting holes 51C and 53D is processed by low temperature anisotropic etching.

First, the DRAM 1 (semiconductor wafer before the dicing step) is directly attracted to the lower electrode in the vacuum chamber of the etching apparatus with the electrostatic attraction plate interposed. This lower electrode is constantly cooled, and as a result, the semiconductor wafer is kept at a temperature below room temperature. In this state, the interlayer insulating films 51 and 53 are anisotropically etched to form the connection holes 51C and 53D, respectively.

Anisotropic etching gas (halogen compound C
Since a large amount of HF ₃ ) is deposited on the surface of the semiconductor wafer whose temperature is lower than the inner wall of the etching chamber, the use of low temperature anisotropic etching can reduce the anisotropic etching gas flow rate, The contaminants attached to the inner wall can be reduced.

(Second Embodiment) In the second embodiment, in order to improve the manufacturing yield of the DRAM 1 of the above-described first embodiment, a transition metal film is buried in a connection hole connecting different wiring layers. It is a second embodiment of the present invention in which a single-wafer type is adopted in the step of inserting.

A main part of DRAM 1 according to the second embodiment of the present invention is shown in FIG. 56 (main part sectional view).

As shown in FIG. 56, D of the second embodiment.
The RAM 1 has a wiring 81 formed on the base insulating film 80.
The transition metal film 83 embedded in the connection hole 82A formed in the interlayer insulating film 82 is connected to the. The wiring 81 is formed of an aluminum film or an aluminum alloy film.
The interlayer insulating film 82 is formed of a single layer of a silicon oxide film or a composite film mainly containing it. The transition metal film 83 embedded in the connection hole 82A is formed of a W film deposited by the selective CVD method. Although not shown, a wiring extending on the interlayer insulating film 82 is connected to the transition metal film 83.

The structure shown in FIG. 56 can be formed by the following manufacturing method employing a single wafer method.

First, a connection hole 82A is formed in the interlayer insulating film 82.
Is formed to expose the surface of the wiring 81 in the connection hole 82A. The surface of the wiring 81 is oxidized by being exposed, and alumina (Al ₂ O ₃ ) is generated.

Next, the alumina formed on the surface of the wiring 81 is removed by the sputtering method. As a sputtering method, a fluorine-based (NF ₃ , XeF, CF) is used in an argon (Ar) gas.
₄ or CHF ₃ ) gas mixed sputtering method is used.
The argon gas can remove the alumina generated on the surface of the wiring 81 by the argon ions by sputtering. The fluorine-based gas can accelerate the sputtering rate of the alumina. Further, the fluorine-based gas removes a layer of dangling bonds formed by collision of argon ions on the surface of the interlayer insulating film 82, improves the selectivity of the transition metal film 83, and corrodes the surface of the wiring 81. Never. That is, only the argon gas forms dangling bonds on the surface of the interlayer insulating film 82, and the transition metal film 83
When the halogen compound such as Cl ₂ is mixed with the argon gas, the layer of dangling bonds can be removed, but since the surface of the wiring 81 is corroded,
As described above, the sputtering method is formed by mixing the fluorine gas with the argon gas.

Next, a transition metal film 83 is selectively deposited on the surface of the wiring 81 in the connection hole 82A, and the connection hole 8 is formed.
A transition metal film 83 is embedded in 2A.

As described above, by removing the alumina on the surface of the wiring 81 by the sputtering method using the above-mentioned mixed gas, the wiring 81 and the transition metal film 83 can be satisfactorily connected and the transition The selectivity of the metal film 83 can be secured.

Further, as shown in FIG. 56, the fluorine (F) of the fluorine-based gas used in the sputtering method is used in the wiring 81.
The surface of is sputtered and aluminum particles are tapped out. The aluminum particles adhere to the inner wall of the connection hole 82A,
The cross contamination 81A is generated. Since the cross contamination 81A has a higher deposition rate of the transition metal film 83 than the surface of the interlayer insulating film 82, as a result, the upper portion of the transition metal film 83 is made to protrude beyond the surface of the interlayer insulating film 82. The protrusion of the transition metal film 83 deteriorates the processing accuracy of the upper layer wiring connected thereto.

DRAM 1 shown in FIG. 57 (main part sectional view)
In order to reduce the protrusion of the transition metal film 83, the cross contamination 81A is left as it is, and the tapered portion 82B is provided above the connection hole 82A. The tapered portion 82B can be formed by isotropic etching. The connection hole 82A can be formed by anisotropic etching. That is, the tapered portion 82B removes a part of the upper side of the cross contamination 81A to expose the surface of the interlayer insulating film 82, and the transition metal film 83 of this part is removed.
Of the transition metal film 83 can be prevented and the transition metal film 83 can be prevented from protruding. On the other hand, cross contamination 81
By leaving A, the deposition rate of the transition metal film 83 can be increased, so that the manufacturing time can be shortened.

Further, the DRA shown in FIG. 58 (main part sectional view)
M1 positively generates the cross contamination 81 on the inner wall of the connection hole 82A to further increase the deposition rate of the transition metal film 83.

Although the deposition rate of the transition metal film 83 becomes slightly slower, the cross contamination 81A may be substantially removed to form the connection hole 82A in a completely tapered shape.

By adopting the single-wafer type, the controllability of the film thickness of the transition metal film 83 can be improved as compared with the batch type.

(Third Embodiment) The third embodiment has a different structure from the DRAM 1 of the second embodiment described above, but a transition metal film is embedded in a connection hole connecting a semiconductor substrate and a wiring layer, and The third aspect of the present invention in which a single-wafer type is adopted in this step
It is an embodiment.

FIG. 59 (main part cross-sectional view) shows a main part of DRAM 1 according to the third embodiment of the present invention.

As shown in FIG. 59, D of the third embodiment.
In the RAM 1, the transition metal film 84 embedded in the connection hole 80A formed in the interlayer insulating film 80 is connected to the n + type semiconductor region 32 formed in the main surface portion of the p− type well region 22. The n + type semiconductor region 32 is silicon (Si) as described in the first embodiment. The interlayer insulating film 80 is formed of a single layer of a silicon oxide film or a composite film mainly composed of it. The transition metal film 84 embedded in the connection hole 80A is
A W film 84 deposited by a selective CVD method using a silicon reduction reaction (reaction between Si in the n + type semiconductor region 32 and WF ₆ ).
A, a W film 84B deposited by a selective CVD method using a silane reduction reaction (reaction of SiH ₄ and WF ₆ ) is sequentially laminated to form a composite film. The lower W film 84A is
Since it is a silicon reduction reaction, the adhesiveness between the n + type semiconductor region 32 and the transition metal film 84 can be improved. Since the upper W film 84B is a silane reduction reaction, the amount of reduction of the surface of the n + type semiconductor region 32 can be reduced, and the n + type semiconductor region 32 having a shallow pn junction depth can be formed. The upper portion of the transition metal film 84 is connected to the wiring (for example, aluminum alloy film) 81 extending on the interlayer insulating film 80.

The structure shown in FIG. 59 corresponds to the connection hole 80.
In the step of forming the transition metal film 84 embedded in A,
When the upper W film 84B is deposited after some time has elapsed after the lower W film 84A is formed, the interface between the two is separated.
(The peeling portion is indicated by reference numeral 84C). This peeling occurs because the stress of the upper W film 84B is larger than that of the lower W film 84A. The peeling also occurs when a reaction by-product such as a fluorine-based gas is present.

DRAM 1 shown in FIG. 60 (main part sectional view)
Is a lower W film 84A of the transition metal film 84 and an upper W film of the transition metal film 84.
Each of the films 84B is continuously formed to eliminate peeling at the interface between the two. The method of continuously forming the lower W film 84A and the upper W film 84B of the transition metal film 84 is as follows.

[0240] First, as shown a relationship between deposition time and source gas flow rate of the W film in selective CVD method employing the FIG. 61 (A) two wafer, WF as a source gas into the reaction furnace of the CVD apparatus ₆ To supply. WF ₆ reacts with Si on the surface of the n + type semiconductor region 32 exposed in the connection hole 80A shown in FIG. 60, and starts forming the lower W film 84A. Along with the supply of WF ₆ , the relationship between the deposition time and the amount of reaction byproducts (F ₂ , SiF ₃ , SiF ₄ ) generated is monitored as shown in FIG. 61 (B). The amount of reaction by-products generated is
It can be measured with a gas mass (gas mass analyzer) arranged in an exhaust gas supply pipe from the reaction furnace or a plasma emission monitor arranged in the reaction furnace (chamber).

Next, when the lower W film 84A is formed, Si on the surface of the n + type semiconductor region 32 is not exposed, so that the deposition of the W film is automatically stopped. As shown in each of (A) and (B), silane gas is supplied to the reaction furnace before the end of the silicon reduction reaction due to the decrease in the amount of reaction by-products generated, and the upper W film 84B is started to be deposited. That is, the silicon reduction reaction is switched to the silane reduction reaction, and the lower W film 84A and the upper W film 84B are successively and sequentially formed. The upper W film 84B is deposited with a predetermined film thickness.

As described above, by continuously forming the lower W film 84A and the upper W film 84B of the transition metal film 84, peeling of the interface between the two can be prevented.

Further, by adopting the single-wafer type, the controllability of the film thickness of the transition metal film 84 can be improved as compared with the batch type.

(Fourth Embodiment) In the fourth embodiment, the dielectric film 36 is provided in the information storage capacitive element C of the stacked structure of the memory cell M of the DRAM 1 of the first embodiment.
It is a fourth embodiment of the present invention, which has described a preferred forming method and apparatus for forming.

Embodiment 4 of the present invention, a single-wafer CV
The D device is shown in FIG. 62 (schematic configuration diagram).

As shown in FIG. 62, the single-wafer CVD apparatus mainly comprises a load / unload chamber 90, a transfer chamber 91, a pretreatment chamber 92, a first reaction furnace chamber 93 and a second reaction furnace chamber 94. Has been done. Each of the processing chambers 90 to 94 is connected via a gate valve 96.

The load / unload chamber 90 is constructed so that a cassette 90A accommodating a plurality of semiconductor wafers 100 can be detachably attached. The load / unload chamber 90 is configured to supply the unprocessed semiconductor wafer 100 to the transfer chamber 91 and to store the processed semiconductor wafer 100 from the transfer chamber 91.

The transfer chamber 91 is configured so as to supply the unprocessed semiconductor wafer 100 to each of the processing chambers 92 to 93 and take out the processed semiconductor wafer 100 from each of the processing chambers 92 to 93. There is. As shown in FIG. 63 (schematic configuration diagram of essential parts), the semiconductor wafer 100 is supplied and taken out by a wafer transfer arm & tray 91B which is connected to and driven by the rotation driving device 91A. The transfer chamber 91 is provided in each of the processing chambers 90, 92 to 93.
Similarly to each of the above, it is kept at a high degree of vacuum in which the atmosphere outside the apparatus is shut off and H ₂ O and O ₂ do not exist.

In this transfer chamber 91, the above-mentioned FIG. 62 and FIG.
As shown in FIG. 3, an ultraviolet irradiation lamp 95 is provided. The ultraviolet irradiation lamp 95 has at least 5 to 6 on the surface of the semiconductor wafer 100 transferred to the transfer chamber 91.
It is configured to irradiate ultraviolet rays having an energy of about [eV] or more to break the Si—F bond, which will be described later.

The pretreatment chamber 92 has the pretreatment module 9
2A is provided. This pretreatment module 92A
Mainly includes a hot plate 92a, a temperature controller 92b, an exhaust pipe 92c, a vacuum pump 92d, a radical generating pipe 92e,
The microwave generator 92f, the microwave power source 92g, and the gas controller 92h are included. That is, the pretreatment chamber 9
No. 2 is configured so that the natural silicon oxide film formed on the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100 can be removed by anisotropic etching. This polycrystalline silicon film corresponds to lower electrode layer 35 of information storage capacitor C having the stacked structure in DRAM 1 of the first embodiment described above. The anisotropic etching (dry etching) uses oxygen gas and a halogen compound (CHF ₃ or CF ₄ ).

The first reaction furnace chamber 93 and the second reaction furnace chamber 94
A common (each independent) cleaning module 93A is provided for each of the above. Each of the first reaction furnace chamber 93 and the second reaction furnace chamber 94 is mainly composed of a source gas supply pipe 93a, a source gas blowing plate 93b, a plate cooling pipe 93c, as shown in FIG. Susceptor 9
3d, wafer heater 93e, reactor cooling tube 93
f, an exhaust pipe 93g, a vacuum gate valve 93h, and a vacuum pump 93i. Not limited to this,
The first reaction furnace chamber 93 deposits a silicon nitride film (the lower silicon nitride film 36A of the dielectric film 36), and the second reaction furnace chamber 94 deposits a polycrystalline silicon film (the lower electrode layer 35 or the upper electrode layer 37). It is constructed so that it can be deposited.

When the DRAM 1 is constructed with a large capacity of 16 [Mbit], for example, high controllability of the film thickness of the lower electrode layer 35 and the dielectric film 36 of the information storage capacitive element C having a stacked structure is required. Therefore, a single-wafer CVD apparatus is suitable for manufacturing the DRAM 1. The first reactor chamber 9
3. In each of the second reaction furnace chambers 94, a source gas blowing plate 93b is arranged at a position facing the deposition surface of the semiconductor wafer 100 held by the susceptor 93d, and the source gas blowing plate 93b is evenly arranged on the surface of the semiconductor wafer 100. The film can be deposited with various film thicknesses and film qualities. Each of the first reaction furnace chamber 93 and the second reaction furnace chamber 94 is maintained at a low temperature as a whole by a reaction furnace cooling pipe 93f, and only the semiconductor wafer 100 is heated to a temperature optimum for reaction by a wafer heating heater 93e. ing.

Also, the source gas blowing plate 9
3b is provided with a plate cooling pipe 93c in order to reduce a temperature rise due to radiant heat of the semiconductor wafer 100. The fine particles that are immediately generated in the vicinity of the outlet of the source gas are coarse particles when they reach the surface of the semiconductor wafer 100 and become foreign matter. Therefore, the source gas blowing plate 93b needs to be cooled by the plate cooling pipe 93c. There is.

As described above, the single-wafer-type CVD apparatus is an integrated continuous process in which the pretreatment chamber 92 is provided in the preceding stage of each of the first reaction furnace chamber 93 and the second reaction furnace chamber 94. Is as follows:

First, as shown in FIG. 62, the semiconductor wafer 100 is transferred from the load / unload chamber 90 to the pretreatment chamber 92 with the transfer chamber 91 interposed. Semiconductor wafer 1
A polycrystalline silicon film is deposited on the surface of 00.

Next, in the pretreatment chamber 92, as shown in FIGS. 62 and 63, the natural silicon oxide film formed on the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100 is removed by anisotropic etching. To do. This anisotropic etching is performed using the oxidizing gas and the halogen compound as the etching gas as described above.

Next, the semiconductor wafer 100 from which the native silicon oxide film has been removed in the pretreatment chamber 92 is transferred to the transfer chamber 91, where the surface of the polycrystalline silicon film is irradiated with ultraviolet rays by the ultraviolet irradiation lamp 95. Irradiate. This irradiation of ultraviolet rays has a function of causing fluorine (F) generated by anisotropic etching to adhere to the surface of the polycrystalline silicon film, so that the fluorine is released as radicals from the surface of the polycrystalline silicon film.

Next, the semiconductor wafer 100 is transferred to the transfer chamber 91.
Are sequentially conveyed to the first reaction furnace chamber 93 and the second reaction furnace chamber 94 via the first reaction furnace chamber 93 and the second reaction furnace chamber 9 respectively.
In each of No. 4, a silicon nitride film or the like is deposited on the surface of the polycrystalline silicon film.

Then, the semiconductor wafer 1 which has been processed
00 is a loader unloader chamber 90 with a transfer chamber 91 interposed.
Is stored in.

As described above, in (39-24) the film deposition method for depositing an insulating film or a conductive film on the polycrystalline silicon film (or the surface of the semiconductor wafer 100) deposited on the surface of the semiconductor wafer 100, in a vacuum system Then, the semiconductor wafer 10
0 of the surface of the polycrystalline silicon film is cleaned in the pretreatment chamber 92 to expose the surface of the polycrystalline silicon film, and the surface of the polycrystalline silicon film is formed on the surface of the polycrystalline silicon film in the same vacuum system as the cleaning step. Depositing an insulating film or a conductive film in the first reaction furnace chamber 93 or the second reaction furnace chamber 94. With this configuration, after the natural silicon oxide film formed on the surface of the polycrystalline silicon film is removed by the cleaning process, the insulating film or the conductive film is deposited on the surface of the polycrystalline silicon film without being exposed to the atmosphere. Therefore, the natural silicon oxide film is not interposed between the surface of the polycrystalline silicon film and the insulating film or conductive film. As a result, the thickness of the surface of the polycrystalline silicon film and the insulating film deposited on the surface, for example, the silicon nitride film 36A of the dielectric film 36 can be reduced by a thickness corresponding to the natural silicon oxide film. It is possible to increase the charge storage amount of the information storage capacitive element C having the stacked structure. Further, it is possible to surely establish conduction between the surface of the polycrystalline silicon film and the conductive film deposited on the surface.

Also, the (40-25) semiconductor wafer 100
In the film deposition method of depositing an insulating film on the surface of the polycrystalline silicon film (or the semiconductor wafer 100) on the surface of the semiconductor wafer 100, a halogen compound is used on the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100 in a vacuum system. A step of cleaning by means of isotropic etching to expose the surface of the polycrystalline silicon film; a step of irradiating the exposed surface of the polycrystalline silicon film with ultraviolet rays in the same vacuum system as the cleaning step; And a step of depositing the insulating film (for example, a silicon nitride film) on the surface of the polycrystalline silicon film in the same vacuum system. With this configuration, the radicals of the halogen element attached to the surface of the polycrystalline silicon film when cleaning the surface can be removed by the ultraviolet rays. Therefore, the insulating film deposited on the surface of the polycrystalline silicon film, for example, It is possible to reduce an increase in leak current of the silicon nitride film and a change in etching rate.

(Fifth Embodiment) In the fifth embodiment, the lower electrode layer 3 is provided in the information storage capacitor C of the stacked structure of the memory cell M of the DRAM 1 of the first embodiment.
5 is a fifth embodiment of the present invention, which describes the preferable forming method and the applying apparatus of the fifth embodiment.

Embodiment 5 of the present invention is a single-wafer type CV.
Method D is shown in FIG. 65 (a time chart showing the opening / closing operation of the source gas valve of the CVD apparatus) and FIG. 66 (a time chart showing the flow rate of the source gas).

As described above, the lower electrode layer 35 of the information storage capacitive element C of the stacked structure of the memory cell M of the DRAM 1 of the first embodiment is formed with a thick film thickness in order to increase the charge storage amount. ing. When the thickness of the lower electrode layer 35 is large, it is difficult to introduce the n-type impurity that reduces the resistance value. In the fifth embodiment, a so-called technique for depositing the polycrystalline silicon film into which the n-type impurity is introduced is called so-called. The lower electrode layer 35 is formed by using the doped polysilicon technology.

Normally, a polycrystalline silicon film which is deposited by the CVD method and into which no n-type impurity is introduced has a high step coverage in the step portion of the underlying layer, but when the film thickness becomes thick, the introduction of the n-type impurity after the deposition becomes difficult. difficult. On the other hand, the polycrystalline silicon film having an n-type impurity introduced by the CVD method is
The introduction of the type impurities is easy, but the step coverage is poor at the stepped portion of the base. Therefore, the fifth embodiment
In order to improve the step coverage at the stepped portion of the underlying layer, a polycrystalline silicon film having no n-type impurity introduced and a polycrystalline silicon film having an n-type impurity introduced are alternately laminated. Further, after depositing the respective polycrystalline silicon films, heat treatment is performed to introduce the n-type impurities from the polycrystalline silicon film into which the n-type impurities have been introduced into the polycrystalline silicon film into which the n-type impurities have not been introduced.

FIG. 65 shows the opening / closing operation of the control valve arranged in the source gas supply pipe of the CVD apparatus. As the source gas, an inorganic silane (SiH ₄ or Si ₂ H ₆ ) gas and a phosphine (PH ₃ ) gas are used. The valve that controls the supply of the inorganic silane gas in the source gas is shown in FIG.
As shown in (A), it is opened for a certain time so as to reach a predetermined film thickness. On the other hand, the control valve for supplying the phosphine gas periodically repeats the opening / closing operation when the control valve for the inorganic silane gas is opened, as shown in FIG. 65 (B). FIG. 66 (A) shows the flow rate of the inorganic silane gas whose supply is controlled by the control valve, and FIG. 66 (B) shows the flow rate of the phosphine gas. The intermittent supply of the phosphine gas can also be controlled by raising or lowering the set value of the mass flow controller. Switching of intermittent supply of phosphine gas by the control valve or the mass flow controller can be performed at a high speed of about 1 to 2 seconds.

Further, as shown in FIG. 67 (schematic configuration diagram of single-wafer CVD apparatus), source gas (PH ₃ ) supply pipe 9
A stop valve 93j may be provided near the reaction furnace chamber 93 (or 94) of 3a, and the source gas may be supplied to the reaction furnace chamber 93 and the vacuum pump 93i at high speed by the stop valve 93j. The CVD apparatus shown in FIG. 67 can switch the supply of phosphine gas intermittently in about 0.1 [second].

As described above, a polycrystalline silicon film (for example, the lower electrode layer 3) is formed on the base surface having the (43-26) step shape.
5) In the film deposition method of depositing, a plurality of layers of a polycrystalline silicon film containing an n-type impurity for reducing a resistance value and a polycrystalline silicon film not containing the n-type impurity are alternately formed on the surface of the underlayer. A step of depositing, and a step of subjecting the stacked polycrystalline silicon films to a heat treatment to diffuse the n-type impurities from the polycrystalline silicon film containing the n-type impurities into the polycrystalline silicon film containing no n-type impurities. Equipped with. With this structure, the step coverage of the polycrystalline silicon film containing the n-type impurity can be supplemented by the polycrystalline silicon film containing no n-type impurity in the step-shaped region of the underlying surface. Since the film thickness can be made uniform and the n-type impurities can be diffused from the polycrystalline silicon film containing the n-type impurities to the polycrystalline silicon film not containing the n-type impurities, the plurality of stacked layers are formed. It is possible to secure a thick film thickness while making the impurity concentration of the polycrystalline silicon film uniform.

(44-27) In the film deposition method of depositing a polycrystalline silicon film on a base surface having a step shape, an inorganic silane gas is flown at a constant flow rate in a vacuum system for depositing the polycrystalline silicon film. A polycrystalline silicon film containing no impurities is deposited on the basis of thermal decomposition, and a phosphine gas is caused to flow in the vacuum system by periodically increasing or decreasing the flow rate to periodically deposit n on the deposited polycrystalline silicon film. A type impurity (P) is contained. With this structure, the polycrystalline silicon film containing the n-type impurities and the polycrystalline silicon film containing no n-type impurities can be successively deposited in the same vacuum system, so that the polycrystalline silicon film is deposited. The time can be shortened. That is, the throughput of the DRAM 1 can be improved.

(Sixth Embodiment) The sixth embodiment is a sixth embodiment of the present invention in which the step of setting the threshold voltage of MISFET is reduced in the method for manufacturing DRAM 1 described above.

A method of manufacturing the DRAM 1 according to the sixth embodiment of the present invention will be briefly described with reference to FIGS. 68 to 71 (sectional views of the essential part shown in each manufacturing step).

The sixth embodiment is the same as the D of the first embodiment.
The threshold voltages of the six MISFETs used in RAM1 are set. That is, as the n-channel MISFET, the memory cell selecting MISFETQs of the memory cell M,
N-channel MISFET Q with standard threshold voltage
n, n-channel MISFET Q with low threshold voltage
each of n. The p-channel MISFET includes a p-channel MISFET Qp having a standard threshold voltage, a p-channel MISFET Qp having a low threshold voltage, and a p-channel MISFET Qp having a high threshold voltage.

MISFETQs for selecting the memory cell
N (formed in the region I in the manufacturing method described later) is n
The channel MISFET is set to the highest threshold voltage. That is, MISFE for memory cell selection
In the memory cell array 11E, since the p-type semiconductor region 25B is formed in the main surface portion of the p-type well region 22, the TQs has a high impurity concentration on the surface and a high threshold voltage. Specifically, the memory cell selection MI
When the gate length dimension of the SFET Qs is 0.8 [μm], the threshold voltage is set to 0.8 [V].

The n-channel MISFET Qn (formed in the region III) having the standard threshold voltage is used in most of the peripheral circuits except the sense amplifier circuit (SA) 13, that is, in the region operated with the low power supply voltage Vcc. ing. N-channel MISFETQ having this standard threshold voltage
When the gate length dimension is 0.8 [μm], the threshold voltage of n is set to 0.5 [V].

N-channel M having low threshold voltage
The ISFET Qn (formed in the region II) is mainly used in each of the sense amplifier circuit 13 and the output buffer circuit 1702. The n-channel MISFET Qn having the low threshold voltage has a long gate length dimension in order to reduce variations in the threshold voltage due to variations in processing of the gate electrode 27, particularly variations in the gate length dimension. In the sense amplifier circuit 13, since the sensitivity at the time of information determination decreases as the gate length increases, the n-channel MISFET
The threshold voltage of Qn is set low. Further, in the output buffer circuit 1702, when the gate length dimension becomes long, the driving capability of the next-stage device decreases, so that the n-channel MISFETQ
The threshold voltage of n is set low. The n-channel MISFET Qn having this low threshold voltage is formed with a gate length dimension of 1.4 [μm] and a threshold voltage of 0.5 [V].
Is set to. That is, the n-channel MISFET Qn having a low threshold voltage has a gate length dimension of 0.8 [μ
When converted back to m], the threshold voltage is set to 0.3 [V].

On the other hand, the p-channel MISFET Qp having the standard threshold voltage (formed in the region IV) is used in most of the peripheral circuits except the sense amplifier circuit 13, that is, in the region where it is operated at the low power supply voltage Vcc. There is. P-channel MISFET Qp having this standard threshold voltage
When the gate length dimension is 0.8 [μm], the threshold voltage is set to −0.5 [V].

P channel M having said low threshold voltage
The ISFET Qp (formed in the region V) is used in the sense amplifier circuit 13. Further, the p-channel MISFET Qp having a low threshold voltage is a reference potential of the reference voltage generating circuit of the VCC limiter circuit 1804 and the VDL limiter circuit 1810 (the low power supply voltage Vcc is about 3.
It is used as one p-channel MISFET Qp forming a reference potential −1.0 [V]) for forming 3 [V]. The p-channel MISFET Qp having a low threshold voltage used as the sense amplifier circuit 13 has a gate length dimension of 1.4 [μm] and a threshold voltage of −0.5.
It is set to [V] (threshold voltage is low in absolute value).
That is, a p-channel MISFE having a low threshold voltage
When the gate length dimension of TQp is converted back to 0.8 [μm], the threshold voltage is set to −0.2 [V]. On the other hand, the p-channel MISFET Qp having a low threshold voltage used in the reference voltage generation circuit is formed with a gate length dimension of 8 [μm] and a threshold voltage of −0.6 [V].
Is set to. That is, the p-channel MISFET Qp having a low threshold voltage has a gate length dimension of 0.8 [μ
When converted back to m], the threshold voltage is set to -0.2 [V].

P-channel M with high threshold voltage
ISFET Qp (formed in the region VI) is the other p-channel MIS that forms the reference potential of the reference voltage generating circuit.
Used as FET Qp. P channel MISF having high threshold voltage used in this reference voltage generating circuit
The ETQp has a gate length dimension of 8 [μm] and a threshold voltage of −1.6 [V] (the threshold voltage is high in absolute value). That is, the p-channel MISFET Qp having a high threshold voltage has a gate length dimension of 0.8 [μ
When converted back to m], the threshold voltage is set to -1.2 [V].

Next, each MISFE of this DRAM 1
A method of forming T will be briefly described.

First, as in the method of manufacturing the DRAM 1 of the first embodiment described above, n is formed on the main surface portion of the p--type semiconductor substrate 20.
Each of the − type well region 21 and the p − type well region 22 is formed, and thereafter, the element isolation insulating film 23, the p type channel stopper region 24, the p type channel stopper region 25A,
Each of the p-type semiconductor regions 25B is sequentially formed. This formed state is shown in FIG. As the DRAM 1 is highly integrated, the separation dimension between the p-channel MISFETs Qp is reduced and the separation ability is lowered, so that the impurity concentration of the n-type well region 21 is set to be slightly higher. Specifically, n
The − type well region 21 has, for example, 1 × 10 ^{13 to} 3 × 10 ¹³ [a
The impurity concentration is set to about toms / cm ² ]. The impurity concentration of the n-type well region 21 can set the high threshold voltage (absolute value) of the p-channel MISFET Qp formed in the region VI. On the other hand, the DRAM 1 is highly integrated, and thus has an n-channel MISF having a standard threshold voltage.
Since the gate length dimension of ETQn is reduced, the substrate effect constant is lowered, and the impurity concentration of the p--type well region 22 can be set slightly higher to suppress the short channel effect. Specifically, the p-type well region 22 has, for example, 7 × 1.
The impurity concentration is set to about 0 ^{12 to} 9 × 10 ¹² [atoms / cm ² ]. The impurity concentration of the p-type well region 22 is the region II.
It is possible to set the low threshold voltage of the n-channel MISFET Qn formed in the above. Further, the high threshold voltage of the memory cell selecting MISFET Qs in the region I can be set by the impurity concentration of the p-type well region 22 and the diffusion of the impurity from the p-type semiconductor region 25B.

Next, as shown in FIG. 69, p is added to the region III.
N-channel MISFETQn
Set the standard threshold voltage of. The p-type impurity 22p is
For example, B having an impurity concentration of about 1 × 10 ^{12 to} 2 × 10 ¹² [atoms / cm ² ] is used, and ion implantation is performed with an energy of about 15 to 25 [KeV]. When introducing the p-type impurity 22p, an impurity introduction mask (for example, a photoresist film) 110 shown in FIG. 69 is used.

Next, as shown in FIG. 70, p-type impurity 21p ₁ is introduced into region IV to p-channel MISFET Qp.
Set the standard threshold voltage of. p-type impurity 21p
₁ is, for example, 2.0 × 10 ^{12 to} 2.2 × 10 ¹² [atoms / c
m ² ], and B having an impurity concentration of about 15 to 25 [KeV]
It is introduced by an ion implantation method with a certain level of energy. When introducing this p-type impurity 21p ₁ , an impurity introduction mask (for example, a photoresist film) 111 shown in FIG. 70 is used.

Then, as shown in FIG. 71, a p-type impurity 21p ₂ is introduced into the region V to p-channel MISFET Qp.
Set the low threshold voltage of. This p-type impurity 21p ₂
Is, for example, 2.4 × 10 ^{12 to} 2.6 × 10 ¹² [atoms / cm ² ].
B is used with an impurity concentration of about 15 to 25 [KeV], and the ion implantation method is used. When introducing this p-type impurity 21p ₂ , an impurity introduction mask (for example, a photoresist film) 112 shown in FIG. 70 is used.

The order of introducing the threshold voltage adjusting impurities is not limited to this, and any of them may be introduced first or later.

In this way, the (35-20) complementary MIS
In the DRAM 1 having the FET, the n-channel MIS
P is the impurity concentration that sets the low threshold voltage of FET Qn.
Forming each of the n-type well regions 21 in the main surface portion of a different region of the p-type semiconductor substrate 20 with an impurity concentration that sets a high threshold voltage (absolute value) of the p-type well region 22 and the p-channel MISFET Qp. And a p-type impurity 22p for adjusting the threshold voltage on the main surface of the p-type well region 22.
Is introduced to set the standard threshold voltage of the n-channel MISFET Qn, and the threshold voltage adjusting impurities 21p ₁ (or 21) are added to the main surface of the n − type well region 21.
p ₂ ) and setting the standard (or low in absolute value) threshold voltage of the p-channel MISFET. With this configuration, the low threshold voltage of the n-channel MISFET is set by the impurity concentration of the p-type well region 22, and the high threshold voltage of the p-channel MISFET Qp is set by the impurity concentration of the n-type well region 21. can be set, it is possible to perform four different settings of the threshold voltage twice the threshold voltage adjusting p-type impurity 22p, with the introduction of each of 21p ₁ (or 21p _2), sill It is possible to reduce the number of steps of introducing the value voltage adjusting impurities.

(36-21) Each of the n-type well region 21 and the p-type well region 22 is formed on the main surface of the p-type semiconductor substrate 20 in a self-aligned manner. With this configuration, there is no need for a step of exposing the surface of the p-type semiconductor substrate 20 except for the n-type well region 21 and the p-type well region 22, respectively. Can be reduced.

Further, (37-22) a DRAM 1 having a p-channel MISFET Qp for generating a reference voltage and a p-channel MISFET Qp having a standard threshold voltage.
In, a p-channel MIS for generating the reference voltage
A step of forming the n-type well region 21 at an impurity concentration that sets a high threshold voltage (high in absolute value) of the FET Qp, and threshold voltage adjusting impurities in different regions of the n-type well region 21. 21p ₁ (or 21p ₂ ) is introduced,
The step of setting the standard threshold voltage (or low threshold voltage) of the p-channel MISFET Qp, and the threshold voltage adjusting impurities 2 in different regions of the n − type well region 21.
Introducing 1p ₂ (or 21p ₁ ) and p channel MISFE
Setting a low threshold voltage (or standard threshold voltage) of TQp. With this configuration, the low threshold voltage of the p-channel MISFET Qp that generates the reference voltage can be set by the impurity concentration of the n-type well region 21, and the three types of threshold voltages can be set twice. Since it can be performed by introducing the threshold voltage adjusting impurities 21p ₁ and 21p _{2, respectively} , the number of steps of introducing the threshold voltage adjusting impurities can be reduced.

(Embodiment 7) This embodiment 7 is
It is a seventh embodiment of the present invention in which the charge storage amount of the information storage capacitor C of the stacked structure of the memory cell M is increased in the DRAM 1 of the first embodiment.

DRAM 1 according to the seventh embodiment of the present invention
72 is a plan view of a main part of a memory cell array in a predetermined manufacturing process).

As shown in FIG. 72, in the memory cell M of the DRAM 1 of the seventh embodiment, the groove 35g is provided in the lower electrode layer 35 of the information storage capacitor C having the stacked structure. That is, the information storage capacitor C having a stacked structure
Can increase the surface area in the height direction by the inner wall of the groove 35g of the lower electrode layer 35, so that the charge storage amount can be improved. This groove 35g is used for the word line (W
L) 27 is configured to cross the lower electrode layer 35 in the extending direction.

Next, a method of forming the information storage capacitive element C having the stacked structure of the memory cell M will be briefly described with reference to FIGS. 73 to 76 (main part sectional views showing respective manufacturing steps).

First, similarly to the method of manufacturing the DRAM 1 of the first embodiment, the memory cell M for memory cell selection is selected.
After forming the ISFET Qs, as shown in FIG. 73, the interlayer insulating film 33 is formed.

Then, as shown in FIG. 74, a polycrystalline silicon film 35B is formed on the entire surface of the substrate including the interlayer insulating film 33. The polycrystalline silicon film 35B is formed with a large film thickness as described above, and has n-type impurities for reducing the resistance value introduced therein. The introduction of the n-type impurity employs the method described in the first embodiment, in which the polycrystalline silicon film is divided and deposited in a plurality of layers, and the n-type impurity is introduced by a thermal diffusion method for each deposition. Further, in introducing the n-type impurity, the polycrystalline silicon film in which the n-type impurity is not introduced and the polycrystalline silicon film in which the n-type impurity is introduced described in the fifth embodiment are alternately arranged. A method of stacking and then performing heat treatment is adopted.

Next, as shown in FIG. 75, the polycrystalline silicon film 35B and the interlayer insulating film 33 are formed in the connection portion between the memory cell selecting MISFET Qs and the lower electrode layer 35 of the information storing capacitive element C of the stacked structure. Remove each one in turn,
The groove 35g is formed. The groove 35g is formed by anisotropic etching, for example. By forming this groove 35g,
The surface of the other n-type semiconductor region 29 of the memory cell selecting MISFET Qs is exposed.

Next, the polycrystalline silicon film 3 including the surface of the inner wall of the groove 35g and the exposed surface of the n-type semiconductor region 29.
A polycrystalline silicon film 35C is formed on the entire surface of 5B. The polycrystalline silicon film 35C is formed with a thin film thickness (a film thickness capable of ensuring a step shape) so as not to fill the groove 35g. An n-type impurity is introduced into the polycrystalline silicon film 35C, and this n-type impurity is introduced at a lower impurity concentration than the polycrystalline silicon film 35B in order to reduce the short channel effect of the memory cell selecting MISFETQs.

Next, as shown in FIG. 76, the polycrystalline silicon films 35C and 35B are sequentially patterned to form a lower electrode layer 35. The subsequent manufacturing method is qualitatively the same as the manufacturing method of the DRAM 1 of the first embodiment, and therefore the description thereof is omitted here.

As described above, in the information storage capacitive element C of the stacked structure of the memory cell M of the DRAM 1, the groove 35g is provided in the lower electrode layer 35, so that the groove 35 is formed.
The amount of accumulated charge can be increased by an amount corresponding to g.

Further, the lower electrode layer 35 of the information storing capacitive element C of the stacked structure has a complementary data line (DL) as shown in FIG. 77 (plan view of the main part of the memory cell in a predetermined manufacturing process). You may provide the groove 35g which traverses in the extending direction of 50. Since the DRAM 1 of the seventh embodiment adopts the folded bit line system, the arrangement interval of the lower electrode layers 35 in the extending direction of the word lines 27 is small, and the lower electrode layers 35 have the complementary data lines 50. Is formed in a rectangular shape that is long in the extending direction. Therefore, the groove 3
The increase in the surface area of the lower electrode layer 35 due to 5 g is larger than that described above.

The method of forming the information storage capacitive element C of the stacked structure shown in FIG. 77 will be described with reference to FIGS.
A brief description will be given by using 0 (a cross-sectional view of a main part shown in each manufacturing process).

First, as shown in FIG. 78, the interlayer insulating film 3 is formed.
A polycrystalline silicon film 35B is formed on the entire surface of the substrate including the upper surface of the substrate 3.

Next, as shown in FIG. 79, a groove 35g is formed in the polycrystalline silicon film 35B.

Next, a polycrystalline silicon film 35C is formed on the polycrystalline silicon film 35B, and the polycrystalline silicon films 35C and 35C are formed.
By patterning each of B, the lower electrode layer 35 can be formed as shown in FIG.

The lower electrode layer 35 of the information storage capacitor C having the stacked structure described with reference to FIGS. 72 to 76 is shown in FIGS. 81 to 84 (main part sectional views showing respective manufacturing steps). As described above, the charge storage amount can be further improved.

First, a polycrystalline silicon film 35B is formed as shown in FIG. 81, and then a groove 35g is formed as shown in FIG.

Next, as shown in FIG. 83, the polycrystalline silicon film 35B is previously patterned into the shape of the lower electrode layer 35 and a groove 35g is formed.

Next, a polycrystalline silicon film 35C is formed on the entire surface of the substrate including the surface of the inner wall of the groove 35g, the surface of the polycrystalline silicon film 35B and the exposed surface of the n-type semiconductor region 29.

Next, the lower electrode layer 35 is formed by patterning the polycrystalline silicon film 35C by anisotropic etching. The lower electrode layer 35 can improve the charge storage amount by the groove 35g as described above, and can leave the polycrystalline silicon film 35C on the outer sidewall of the polycrystalline silicon film 35B of the lower electrode layer 35. Because you can
Corresponding to the film thickness of the remaining polycrystalline silicon film 35C,
Further, the amount of accumulated charge can be improved.

Similarly, the lower electrode layer 35 of the information storage capacitor C having the stacked structure described in FIGS. 77 to 80 is shown in FIGS. 85 to 88 (main part sectional views showing each manufacturing process). As shown, the charge storage amount can be further improved.

First, a polycrystalline silicon film 35B is formed as shown in FIG. 85, and then a groove 35g is formed as shown in FIG.

Next, as shown in FIG. 87, the polycrystalline silicon film 35B is preliminarily patterned into the shape of the lower electrode layer 35.

Next, a polycrystalline silicon film 35C is formed on the entire surface of the substrate including the surface of the inner wall of the groove 35g, the surface of the polycrystalline silicon film 35B and the exposed surface of the n-type semiconductor region 29.

Next, the lower electrode layer 35 is formed by patterning the polycrystalline silicon film 35C by anisotropic etching. The lower electrode layer 35 is a polycrystalline silicon film 35.
Since the polycrystalline silicon film 35C can be left on the side wall of the outer periphery of B, the charge storage amount can be further improved by the amount corresponding to the film thickness of the remaining polycrystalline silicon film 35C.

(Embodiment 8) The eighth embodiment of the present invention is a method of manufacturing the DRAM 1 of the first embodiment, in which the amount of mask alignment (alignment) deviation is reduced and the degree of integration is improved. 8th Embodiment.

FIG. 89 (alignment tree diagram) shows the alignment relationship in the manufacturing process of DRAM 1 according to the eighth embodiment of the present invention.

In the manufacturing process of the DRAM 1 of the first embodiment, the upper layer pattern is aligned (position is aligned) with the lower layer pattern. Fig. 89
(A) shows the relationship of alignment in the X direction (for example, the extending direction of word lines). DRAM 1 of the eighth embodiment
Performs the alignment reference in the n-type well region 21. The insulating film 23 for element isolation is formed in the n-type well region 2
1 is aligned in the X direction. The gate electrode (word line) 27 performs alignment in the X direction with respect to the element isolation insulating film 23. The gate electrode 27 serves as a reference for alignment of the upper layer. Each of the lower electrode layer 35, the upper electrode layer 37, and the connection hole 40A of the stacked structure information storage capacitor C has the gate electrode 27.
Is aligned in the X direction.

On the other hand, FIG. 89B shows the alignment relationship in the Y direction (for example, the extending direction of the complementary data lines). The DRAM 1 of the eighth embodiment performs alignment in two directions, the X direction and the Y direction. Similarly,
The n − type well region 21 is used as a reference for alignment, and the element isolation insulating film 23 performs alignment in the Y direction with respect to the n − type well region 21. The gate electrode 27 performs alignment in the Y direction with respect to the element isolation insulating film 23. Unlike the X-direction alignment, the lower electrode layer 35 performs the Y-direction alignment with respect to the element isolation insulating film 23. Upper electrode layer 37, connection hole 4
Each of 0A is aligned in the Y direction with respect to the gate electrode 27.

When the lower electrode layer 35 of the information storing capacitive element C having the stacked structure is largely misaligned with the element isolation insulating film 23, the other n-type semiconductor region 29 of the memory cell selecting MISFET Qs is formed. Opening occurs in the connection hole 34 that connects the lower electrode layer 35 and the lower electrode layer 35 (see FIG. 1). This opening causes the surface of the n-type semiconductor region 29 exposed from the inside of the connection hole 34 to be etched when the lower electrode layer 35 is processed. Therefore, it is necessary to minimize the misalignment amount of the lower electrode layer 35 with respect to the element isolation insulating film 23.

When the lower electrode layer 35 is simply aligned in the X direction and the Y direction with respect to the gate electrode 27 which is the lower layer thereof, between the insulating film 23 for element isolation and the gate electrode 27, Since the amount of misalignment σ between the gate electrode 27 and the lower electrode layer 35 is generated, the amount of misalignment of the lower electrode layer 35 with respect to the element isolation insulating film 23 is 1.4σ.

Therefore, in the eighth embodiment, the lower electrode layer 35 is in the X direction (or the Y direction) with respect to the gate electrode 27 which is a pattern one layer below, as shown in FIG. 89 (A).
89B, and the alignment in the Y direction (or the X direction) is performed with respect to the insulating film 23 for element isolation, which is a pattern two layers below, as shown in FIG. That is,
Lower electrode layer 3 of stacked information storage capacitor C
Reference numeral 5 denotes the gate electrode 2 with respect to the element isolation insulating film 23.
Only the amount of misalignment σ with respect to 7 occurs. Since the lower electrode layer 35 is a layer that does not serve as a reference for the alignment of the upper layer, it can be aligned over different layers as described above.

As described above, in the alignment method for aligning (46-28) three elements different patterns of the inter-element isolation insulating film 23, the gate electrode 27, and the lower electrode layer 35 in the X direction and the Y direction, Electrode (second
The lower layer electrode layer (third pattern) 27 is formed on the gate electrode 27 by aligning the second layer pattern) 27 with the insulating film for isolation between elements (first layer pattern) 23 in the X direction and the Y direction. The layer pattern 35 is aligned in the X direction (or the Y direction) with respect to the gate electrode 27 in the lower layer, and is further aligned in the Y direction (or the X direction) with respect to the insulating film 23 for element isolation in the lower layer. With this structure, the insulating film for element isolation 23 and the gate electrode 27 are formed.
And the amount of alignment deviation between the element isolation insulating film 23 and the lower electrode layer 35 can be made substantially the same. The amount of misalignment with the lower electrode layer 35 can be reduced. As a result, the degree of integration of the DRAM 1 can be improved by the amount corresponding to the mask alignment margin in the manufacturing process. Further, as described above, there is no opening in the connection hole 34 that connects the other n-type semiconductor region 29 of the memory cell selection MISFET Qs and the lower electrode layer 35.

(Ninth Embodiment) The ninth embodiment is a preferred method of forming a target mark when performing the alignment method described in the eighth embodiment in the DRAM 1 of the first embodiment. 9th of this invention demonstrated
It is an embodiment.

The structure of the target mark portion of the DRAM 1 of the ninth embodiment is shown in FIG. 90 (main part sectional view).

As shown in FIG. 90, the target mark T
M is composed of a connection hole 53D formed in the interlayer insulating film 53 of the DRAM 1 and a wiring 55 formed on the interlayer insulating film 53. In the semiconductor wafer state, the target mark TM is a scribe area between the formation regions of the DRAMs 1, the inside of the formation region of the DRAMs 1, or the dummy DRA.
It is arranged in a formation region of M1 (not used as a DRAM but used as a target mark for alignment).

The target mark TM can be formed by forming the connection hole 53D in the region where the wiring (transition metal film) 52 is not formed on the interlayer insulating film 51. Since the wiring 52 does not exist in the lower layer inside the connection hole 53D, the transition metal film 54 for embedding is not deposited by the selective CVD method, and the wiring 55 uses the aluminum alloy film 55B having poor step coverage. Therefore, the step shape of the connection hole 53D is formed on the surface of the wiring 55. This step shape is used as the target mark TM.

In this way, the get mark TM is D
Since the step of forming the connection hole 53D and the step of forming the wiring 55 in the manufacturing process of the RAM 1 can be performed in common, the number of manufacturing steps can be reduced.

(Tenth Embodiment) The tenth embodiment is
In the method of manufacturing the DRAM 1 of the first embodiment described above,
It is the 10th Embodiment of this invention which improved the depth of focus and the resolution at the time of exposure of a photolithographic technique.

DRAM 1 which is Embodiment 10 of the present invention
91 (conceptual diagram) and FIG. 92 (process flow chart) show respective steps of the photolithography technique used in the manufacturing process of FIG.

[0328] photolithography of the tenth embodiment, FLEX (F ocus L atitudeenhancement Ex pos
ure) method and the CEL (C ontrast E nhancement L ithogr
aphy) method is used to improve the depth of focus and resolution of the photoresist film during exposure. The procedure of the exposure process of this photolithography technique is as follows.

As shown in FIGS. 91 and 92, first, a photoresist film 120 is applied to the semiconductor wafer 100 (1).

Next, a photochromic CEL material 121A is dropped on the surface of the photoresist film 120 applied to the semiconductor wafer 100 to apply the photochromic CEL film 121 (2). Photochromic CEL film 1
As the 21, for example, a nitrone is used as shown in FIG. 93 (structural formula). This photochromic CEL film 121
As shown in FIG. 94 (a diagram showing the transmittance with respect to exposure), has the property of being transparent (bleaching) when a certain amount of light is irradiated (irradiation start t ₁ ). Further, the photochromic CEL film 121 has a property of gradually becoming opaque when the light irradiation is stopped (irradiation end t ₂ ). Moreover, these properties are repetitive.

Next, in the projection exposure apparatus, the pattern of the reticle 125 is transferred to the photoresist film 120 coated on the surface of the semiconductor wafer 100 with the projection optical system 124 and the photochromic CEL film 121 interposed ( 3). This exposure uses the FLEX method, and the pattern is superimposed and exposed while changing the depth of focus.

FIG. 95 shows a photochromic CEL film 121.
F to line and space pattern with or without
The difference in the depth of focus when the LEX method is applied is shown. FIG. 95 (A)
Shows a light intensity profile at the time of exposure on the surface (in the photoresist film 120) of the semiconductor wafer 100 having a line-and-space pattern. As shown in FIG. 95 (A), light is emitted to a portion of the reticle 125 corresponding to a position where the chrome pattern 125A does not exist, and the light intensity at the focus position (0 [μm]) is maximum, and the light is vertically moved from the focus position. The light intensity decreases as it shifts.

FIG. 95B shows the relationship between the light intensity profile and the characteristics of the photochromic CEL film 121 when the FLEX method is applied and the surface of the semiconductor wafer 100 is stepped up and down to increase the depth of focus. Indicates. FIG. 9
5 (B), the surface of the semiconductor wafer 100 is reduced to 0.
When it is increased by 5 [μm], (a) the light intensity becomes higher at a deep position of the photoresist film 120. When the light intensity reaches a certain amount that makes the photochromic CEL film 121 transparent, (b) the photoresist film 120 is irradiated with an amount of light exceeding the above-mentioned certain amount. When the light intensity is equal to or less than a certain amount, that is, at a shallow position of the photoresist film 120, light irradiation is blocked by the photochromic CEL film 121.
Next, in FIG. 95 (B), the semiconductor wafer 100
When the surface of is lowered by 0.5 [μm], (c) the light intensity becomes higher at the shallow position of the photoresist film 120. When the light intensity reaches a certain amount that makes the photochromic CEL film 121 transparent, (d) the photoresist film 120 is irradiated with an amount of light that exceeds the certain amount. When the light intensity is equal to or less than a certain amount, that is, at a deep position of the photoresist film 120, light irradiation is blocked by the photochromic CEL film 121.

FIG. 95C shows a total light intensity profile of two times of light irradiation to which the FLEX method shown in FIG. 95B is applied, and (a + b) shows a photochromic CEL.
When the film 121 is not provided, (a × b + c × d) is the case where the photochromic CEL film 121 is provided. In the case where the former photochromic CEL film 121 is not provided, in the line and space pattern, when the FLEX method is applied, the light intensity profile exceeds the dissolution level of the photoresist film 120 in the unexposed portion, and means for improving the depth of focus. Is not preferable. On the other hand, when the latter photochromic CEL film 121 is present, the photochromic C
The bleaching effect of the EL film 121 and the change of the focus position by the FLEX method can improve the resolution and the depth of focus.

After the exposure process shown in FIGS. 91 and 92, the photochromic CEL film 12 is washed with the cleaning liquid 122.
1 is removed (4), and the photoresist film 120 is developed with a developing solution 123 (5).

Further, as shown in FIG. 91, a photochromic CEL film 121B may be used instead of the step of applying the photochromic CEL film 121.
This photochromic CEL film 121A is a photoresist film 1 applied on the surface of a semiconductor wafer 100.
It is pressed against the surface of 20 and used.

As described above, by using the FLEX method and the CEL method in the photolithography technique,
High resolution and high depth of focus of the pattern can be obtained.

(Eleventh Embodiment) The eleventh embodiment is
It is an eleventh embodiment of the present invention in which the alignment accuracy of each layer is improved in the manufacturing process of the DRAM 1 of the first embodiment described above.

The DRAM 1 according to the eleventh embodiment of the present invention.
FIG. 96 (schematic plan view) shows the structure of the semiconductor wafer 100 before the dicing step.

As shown in FIG. 96, the semiconductor wafer 10
Reference numeral 0 denotes a plurality of DRAMs 1 arranged in a matrix before the dicing process (before being formed into pellets). A scribe area (not shown) is provided between the DRAMs 1. As shown in FIG. 97 (enlarged plan view of portion A in FIG. 96) and FIG. 98 (enlarged plan view of portion B in FIG. 97),
DRAMs (α to
Target marks TM that are shared by adjacent DRAMs 1 are arranged in the scribe area between ε) 1. The target mark TM serves as a positioning reference in alignment in a reduction projection exposure apparatus, for example.
As shown in FIGS. 97 and 98, the adjacent DRAM 1
Target marks T that are shared by each other, for example between β and γ
M is arranged so that it can be detected by scanning the alignment beam AB once in the X direction. 97 and 98 also show the waveform of the alignment signal S when the target mark TM is detected by scanning the alignment beam AB. Based on this alignment signal,
The center position Xβ in the X direction, the center position Yβ in the Y direction, and the rotation amount Wβ of the DRAM (β) 1 shown in FIG. 97 can be calculated by the following equations.

[0341]

[Equation 2]

The alignment of the eleventh embodiment is performed by the DRA of the first layer arranged on the surface of the semiconductor wafer 100.
When the pattern (pellet pattern) of the DRAM 1 of the second layer is arranged with respect to the pattern (pellet pattern) of M1, the position of the target mark TM of the pattern of the DRAM 1 of the first layer is detected by the alignment beam AB. Is calculated and corrected so that the positional deviation between the patterns of the adjacent DRAMs 1 of the second layer becomes small, the second
This is performed by the method of arranging the pattern of the DRAM 1 of the layer. That is, the associative alignment method is employed in which the pattern of the DRAM 1 of the second layer is associatively aligned with the pattern of the DRAM 1 of the first layer. This associative alignment method can secure the regularity of mutual arrangement between the patterns of the DRAM 1 as compared with the pellet alignment method. The pellet alignment method is a method in which alignment and exposure are repeated for each pattern of each DRAM 1 on the surface of the semiconductor wafer 100.

Further, in the associative alignment method, even if the target mark TM is largely erroneously detected, a large alignment error does not occur directly and high alignment accuracy can be obtained.

Further, the associative alignment method can obtain higher alignment accuracy than the multipoint wafer alignment method even when the pattern arrangement of the DRAM 1 of the first layer has a large distortion. The multi-point wafer alignment method is a method in which a plurality of target marks TM on the surface of the semiconductor wafer 100 are sampled and aligned, the arrangement of the DRAM 1 is estimated from the statistical calculation from the result, and only the exposure is performed thereafter.

Further, the associative alignment method is the first
Based on the detection of the target marks TM arranged on the four sides of the pattern of the first layer DRAM1, the second layer DRAM1 is detected.
Since it is possible to calculate and correct the rotation amount of the pattern, the correction accuracy of the rotation amount is higher than that when the rotation amount is corrected by detecting the target marks TM arranged at two points of the DRAM 1, for example, vertically or horizontally. Obtainable. Also in the case of this correction of the rotation amount, the associative alignment method does not directly cause a correction error of a large rotation amount even when one target mark TM is erroneously detected, so that high alignment accuracy can be obtained.

When the pellet alignment method and the multi-point wafer alignment method are mixed, the alignment accuracy is generally lowered, but the associative alignment method can obtain high alignment accuracy regardless of which method is used. it can.

The associative alignment method uses two DRs that are adjacent to each other by scanning the alignment beam AB once.
Since the target mark TM having the AM1 pattern can be detected, it is possible to obtain a throughput substantially equivalent to that of the pellet alignment method.

FIG. 99 shows a comparison of alignment accuracy between the associative alignment method, the pellet alignment method and the multi-point wafer alignment method when the pattern arrangement of the DRAM 1 of the first layer has distortion or rotation. In FIG. 99 (A), (a) the ideal arrangement of the pattern (1) of the DRAM 1 on the first layer, (b) the DR on the first layer
Each of the arrangements when the arrangement (1) of AM1 has arrangement distortion and rotation is shown. In the latter pattern (1) of the DRAM 1 of the first layer, the X coordinates of α to γ do not match each other, and α-
The pitches in the Y coordinate direction between β and β-γ are different,
Moreover, each of α and γ has a rotation error. The array distortion and rotation are caused by the warp that occurs in the semiconductor wafer 100 due to the repeated heat treatment and the like.

FIG. 99 (B) shows the case where the pattern (2) of the DRAM 1 of the second layer is aligned in the case where the array of the pattern (1) of the DRAM 1 of the first layer has the above array distortion and rotation. The comparison of each alignment method is shown. In either case, the γ pattern (2) of the DRAM 1 of the second layer shows the case where the target mark TM is largely erroneously detected with respect to the γ pattern (1) of the DRAM 1 of the first layer. The correction of the rotation amount is calculated based on the detection of four target marks TM in the associative alignment method, and is calculated based on the detection of two target marks TM in the other two alignment methods. Fig. 99
As shown in (B), when the rotation amount is not corrected and when the rotation amount is corrected, the associative alignment method has higher alignment accuracy than the other pellet alignment methods and the multi-point wafer alignment method. Can be obtained.

As described above, by adopting the associative alignment method, high alignment accuracy can be obtained.

(Twelfth Embodiment) The twelfth embodiment is
In the DRAM 1 of the first embodiment described above, the reliability of the connection portion between the transition metal film embedded in the connection hole of the interlayer insulating film by the selective CVD method and the wiring extending on the interlayer insulating film is improved. Is a twelfth embodiment of the present invention.

DRAM 1 according to the twelfth embodiment of the present invention
The configuration is shown in FIG. 100 (a cross-sectional view of the main part).

The DRAM 1 of the twelfth embodiment is shown in FIG.
0, the connection hole 5 formed in the interlayer insulating film 51.
A transition metal film 54 is embedded in each of 1D and 51S, and a wiring 52 extending on the interlayer insulating film 51 is formed in the transition metal film 54.
Is connected.

In the area of the memory cell array 11E, since the memory cell M composed of the memory cell selecting MISFET Qs and the information storing capacitive element C of the stacked structure is arranged, the step shape is larger than that of the peripheral circuit area. Become. Therefore, the film thickness of the interlayer insulating film 51 in the region of the memory cell array 11E is smaller than that of the peripheral circuit region. As shown in FIGS. 100 and 101 (a cross-sectional view of an essential part in a predetermined manufacturing process), the connection hole 51S formed in the region of the memory cell array 11E of the interlayer insulating film 51 is formed to have a shallow depth, and the region of the peripheral circuit is formed. Connection hole 51 formed in
D is deeply formed.

As the transition metal film 54, a W film deposited by the selective CVD method is used as in the first embodiment.
The wiring 52 uses an aluminum alloy film in the twelfth embodiment. Further, the wiring 52 may be formed of a transition metal film such as a W film deposited by a sputtering method or a composite film mainly containing the same.

As shown in FIGS. 100 and 101, the transition metal film 54 is formed to a thickness such that the connection hole 51S having a shallow depth in the region of the memory cell array 11E is buried. That is, the transition metal film 54 is configured such that it does not protrude from the connection hole 51S, with the connection hole 51S having a shallow depth as a reference. When the transition metal film 54 largely protrudes from the connection hole 51S, the surface of the wiring 52 in the upper layer of this portion protrudes, and as a result, variations in the film thickness of the photoresist film for processing the wiring 52 and diffraction during exposure. Due to the phenomenon, the size of the etching mask changes from the set value,
The processing accuracy of the wiring 52 is reduced. In addition, the connection hole 51
Since the surface of the transition metal film 54 that greatly protrudes from S cannot be covered with the upper wiring 52, the transition metal film 54 is etched more than necessary in the etching process for processing the wiring 52. The transition metal film 54 embedded in the connection hole 51D having a deep depth in the peripheral circuit region is shown in FIG.
As shown in FIG. 5, the connection hole 51D is filled with a film thickness such that the aspect ratio does not exceed 1. When the aspect ratio exceeds 1, the step coverage of the wiring 52 in the upper layer is deteriorated, and the wiring 52 frequently causes disconnection in the connection hole 51D portion.

Thus, the interlayer insulating film 51 is formed on the underlying surface having the (48-29) stepped shape, and the region of the interlayer insulating film 51 having the high stepped shape (the area of the memory cell array 11E). A shallow connection hole 51S and a deep connection hole 51D are formed in a low stepped region (peripheral circuit region), and are connected to the transition metal film 54 embedded in each of the connection hole 51S and the connection hole 51D. In the DRAM 1 in which the wiring 52 extends on the interlayer insulating film 51 as described above, the transition metal film 54 buried in each of the shallow connection hole 51S and the deep connection hole 51D is deposited by the selective CVD method, and the transition metal film is formed. The film 54 is deposited with a film thickness approximately equal to the depth of the shallow connection hole 51S. With this configuration, the transition metal film 54 embedded in each of the shallow connection hole 51S and the deep connection hole 51D is formed to have a film thickness similar to the depth of the shallow connection hole 51S, and the shallow connection hole 51S and the deep connection hole 51D are formed. Since the transition metal film 54 does not protrude from each of the above, it is possible to improve the processing accuracy of the wiring 52 and the reliability of the wiring.

(Thirteenth Embodiment) The thirteenth embodiment is
It is a thirteenth embodiment of the present invention in which the reliability of the wiring 52 mainly composed of a transition metal film is improved in the DRAM 1 of the first embodiment described above.

DRAM 1 which is Embodiment 13 of the present invention
102 is shown in FIG. 102 (a cross-sectional view of a main part).

As shown in FIG. 102, the thirteenth embodiment is as follows.
In the DRAM 1, the wiring 52 is extended on the interlayer insulating film 51. The wiring 52 is formed of a composite film in which a transition metal film 52B which is substantially the same metal material is laminated on the transition metal film 52A.

The transition metal film 52A under the wiring 52 is formed of, for example, a W film deposited by a sputtering method, and is formed of, for example, 80
It is formed with a film thickness of about 120 [nm]. The lower transition metal film 52A has high adhesiveness to the underlying interlayer insulating film (silicon oxide based insulating film) 51. Further, if the lower layer transition metal film 52A is made too thick, it becomes an overhang shape in the upper part of the step shape formed by the connection hole 51C, a nest is generated, and the step coverage of the upper layer transition metal film 52A. It causes a decrease in film thickness and the like, and thus is formed with the above-mentioned thin film thickness. In addition, the lower transition metal film 52A is formed as shown in FIG.
As indicated by the relationship between the target voltage and film stress at the time of sputtering in 03, film stress does not occur because it causes peeling from the surface of the interlayer insulating film 51 (stress 0 or within an allowable range in the vicinity). Deposition using voltage. Also,
The lower transition metal film 52A has a property substantially equal to the etching rate of the upper transition metal film 52B. Further, the lower transition metal film 52A has higher corrosion resistance than the TiN film and the like, and has a small work function difference from Si, so that the contact resistance value can be reduced.

A transition metal film 52B in the upper layer of the wiring 52.
Is formed of a W film deposited by a CVD method, for example, 25
It is formed with a film thickness of about 0 to 350 [nm]. The upper-layer transition metal film 52A reduces the substantial resistance value of the wiring 52 and is configured as the main body of the wiring 52. Since the upper transition metal film 52B is deposited by the CVD method,
Since the step coverage at the step portion of the base is high and the disconnection defect can be reduced, the reliability as the wiring can be improved. This upper transition metal film 52B
Are formed of the same metal film material, and therefore have high adhesiveness to the transition metal film 52A which is the lower layer of the underlying layer.

As described above, in the DRAM 1 in which the wiring 52 is formed of the transition metal film 52B deposited by the CVD method on the (51-30) underlying interlayer insulating film 51, in the transition metal of the underlying interlayer insulating film 51 and the wiring 52. A transition metal film 52A of substantially the same type as the transition metal film 52B deposited by the sputtering method is provided between the transition metal film 52B and the film 52B. With this configuration, since the lower transition metal film 52A deposited by the sputtering method has high adhesiveness to the underlying interlayer insulating film 51 and the upper transition metal film 52B of the wiring 52, the underlying interlayer insulating film 51 Since the adhesiveness with the wiring 52 can be improved and the lower transition metal film 52A deposited by the sputtering method is formed of the same transition metal film as the upper transition metal film 52B, It is possible to prevent unevenness from being formed on the processed side wall of the wiring 52 and improve the processing accuracy of the wiring 52.

As shown in FIG. 102, when the transition metal film 52A in the lower layer of the wiring 52 is directly connected to the n + type semiconductor region 32 or the p + type semiconductor region 39, the transition metal film 52A in the lower layer is formed. The heat treatment after deposition is performed at a temperature not higher than the temperature at which W and Si do not undergo an alloying reaction. Specifically, the heat treatment is performed at about 600 [° C.] or less. In this way, the wiring 52
By limiting the heat treatment temperature of the lower transition metal film 52A, it is possible to suppress the increase in the resistance value of the connection portion due to the alloying reaction between W and Si and prevent the alloy spike phenomenon.

(Embodiment 14) This embodiment 14 is
This is a fourteenth embodiment of the present invention in which the reliability of the connection between the memory cell M and each element and the wiring is improved in the DRAM 1 of the first embodiment.

[0366] The DRAM 1 according to the fourteenth embodiment of the present invention.
The configuration of is shown in FIG. 104 (a cross-sectional view of the main part).

The DRAM 1 of the fourteenth embodiment is shown in FIG.
As shown in FIG. 4, in the memory cell array 11E, the intermediate conductive film 130 is interposed between the one n-type semiconductor region 29 of the memory cell selecting MISFET Qs of the memory cell M and the complementary data line (DL) 50. . The intermediate conductive film 130 is used as the connection hole 1 formed in the interlayer insulating film 131.
A part is connected to the n-type semiconductor region 29 through 31 A and the connection hole 34 A, and the other part is extended on the sidewall spacer 31 and the interlayer insulating film 131. The connection hole 34A is formed in the connection hole 131A formed in the interlayer insulating film 131, and is used as a memory cell selection MISFET.
It is formed of a sidewall spacer 31 formed on the side wall of the Qs gate electrode 27 and defines the opening size. Since the connection hole 34A is formed in self alignment with the gate electrode 27, as a result, the intermediate conductive film 130 is formed.
And the n-type semiconductor region 29 are connected to the gate electrode 27 by self-alignment. That is, the n-type semiconductor region 29 of the memory cell selecting MISFET Qs and the complementary data line 50 are connected to the gate electrode 27 of the memory cell selecting MISFET Qs in a self-aligned manner with the intermediate conductive film 130 interposed.

The intermediate conductive film 130 is formed in an upper layer than the gate electrode 27 (including the word line 27) of the memory cell selecting MISFET Qs, and lower than the lower electrode layer 35 of the stacked information storage capacitor C. It is formed in the lower layer. That is, since the lower electrode layer 35 of the information storage capacitive element C having a stacked structure is formed with a large film thickness to increase the amount of charge storage, the intermediate conductive film 130 is formed in the lower layer in order to improve processing accuracy. It is formed as a layer different from the electrode layer 35 and as a lower layer. The intermediate conductive film 130 is, for example, CV.
Formed of a polycrystalline silicon film deposited by the D method,
It is formed with a thin film thickness of about 0 [nm]. An n-type impurity that reduces the resistance value is introduced into this polycrystalline silicon film.

Since the intermediate conductive film 130 can alleviate a particularly steep step shape of the connection portion between the memory cell M and the complementary data line 50, the disconnection defect of the complementary data line 50 can be reduced. it can.

The intermediate conductive film 130 is also formed on peripheral circuit elements in the same manufacturing process. Although not limited to this, in the fourteenth embodiment, an n-channel MISF is used.
ETQn n especially in areas where layout rules are strict
It is provided between the + type semiconductor region 32 and the wiring 52. Normally, the peripheral circuit has a looser layout rule than the memory cell array 11E. As shown in FIG. 104, in the peripheral circuit region, the intermediate conductive film 130 is formed even when the wiring 52 runs on the element isolation insulating film 23.
Since it is possible to reliably connect the n + type semiconductor region 32 and the wiring 52 with the interposition of, the area of the n + type semiconductor region 32 can be reduced, and as a result, the integration degree of the DRAM 1 can be improved. In addition, the n-channel MISFE of the peripheral circuit
Even when the TQn and the p-channel MISFET Qp are connected to each other by the wiring 52 formed of a material such as a transition metal film that easily causes mutual diffusion of impurities, the intermediate conductive film 130 can prevent the mutual diffusion, and thus the connection portion. It is possible to reduce the resistance value at.

Next, the DRAM 1 according to the 14th embodiment will be described.
The method of forming the above will be briefly described with reference to FIGS.

First, similarly to the method of forming the DRAM 1 of the first embodiment, the memory cell selection MI of the memory cell M is selected.
SFETQs, n-channel MISFETQn of peripheral circuit
To form each.

Next, the memory cell selecting MISFET
An interlayer insulating film 131 is deposited on the entire surface of the substrate so as to cover the Qs and the n-channel MISFET Qn. The interlayer insulating film 131 uses a silicon oxide film deposited by a CVD method using, for example, an inorganic silane gas and a nitric oxide gas as source gases, and is formed with a film thickness of about 40 to 60 [nm].

Next, the memory cell M of the memory cell M is selected.
One n-type semiconductor region 29 of the ISFET Qs, a predetermined n
In each region of the n + type semiconductor region 32 of the channel MISFET Qn, the connection hole 13 is formed in the interlayer insulating film 131.
1A is formed and the connection hole 34A is formed.

Next, as shown in FIG. 105, the n-type semiconductor regions 29, n + are formed through the connection holes 131A and 34A.
Intermediate conductive film 130 connected to each of the type semiconductor regions 32
To form.

Next, as shown in FIG. 106, an interlayer insulating film 33 is formed on the entire surface of the substrate including the intermediate conductive film 130. Then, thereafter, the same steps as the method for forming the DRAM 1 of the first embodiment, such as the information storage capacitor C having a stacked structure and the p-channel MISFET Qp, are performed to complete the DRAM 1 of the fourteenth embodiment.

Thus, at the intersection of the (53-31) complementary data line 50 and the word line 27, the memory cell selecting MISFET Qs, the lower electrode layer 35, the dielectric film 36, and the upper electrode layer 37 are respectively provided. In the DRAM 1 in which a memory cell M formed by a series circuit of a stacked structure information storage capacitive element C is arranged, the complementary data line 50 and one n-type semiconductor region of the memory cell selecting MISFET Qs are arranged. A part of the n-type semiconductor region 29 is formed in self-alignment with the other n-type semiconductor region 29, and the other part is drawn out onto the gate electrode 27 of the memory cell selecting MISFET Qs, and also for storing information of the stacked structure. An intermediate conductive film 130 formed as a layer different from the lower electrode layer 35 of the capacitor C is provided below the lower electrode layer 35. With this configuration, since the intermediate conductive film 130 is interposed, the amount corresponding to the mask alignment margin dimension in the manufacturing process between the one n-type semiconductor region 29 of the memory cell selecting MISFET Qs and the complementary data line 50. The area of the memory cell M can be reduced to improve the degree of integration, and the distance between the intermediate conductive film 130 and the lower electrode layer 35 of the information storage capacitor C having the stacked structure is eliminated, so that the intermediate conductive film 130 is removed.
Since the area of the lower electrode layer 35 can be increased independently of the above, the charge storage amount of the information storage capacitive element C having a stacked structure can be increased, the area of the memory cell M can be reduced, and the degree of integration can be improved. .

The (54-32) intermediate conductive film 130 is formed to have a smaller film thickness than that of the lower electrode layer 35 of the information storage capacitor C having the stacked structure. With this configuration, the information storage capacitive element C having the stacked structure is
Since the film thickness of the lower electrode layer 35 can be increased to increase the area in the height direction, the charge storage amount is improved and the memory cell M is improved.
The area can be reduced and the integration can be improved, and
Since the intermediate conductive film 130 has a small thickness, it can be processed easily.

(55-33) The memory cell M is provided between the n + type semiconductor region 32 of the n channel MISFET Qn forming the peripheral circuit and the wiring 52 connected thereto.
The intermediate conductive film 130 formed of the same conductive layer as the intermediate conductive film 130 provided in the above is provided. With this configuration, DRA
Since the intermediate conductive film 130 of the peripheral circuit can be formed in the step of forming the intermediate conductive film 130 formed in the memory cell M of M1, the number of manufacturing steps of the DRAM 1 can be reduced.

The invention made by the present inventors is as follows.
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device using a DRAM as one unit, such as a microcomputer (one-chip microcomputer).

Further, the present invention is not limited to the DRAM, but can be applied to a semiconductor integrated circuit device having other storage functions such as SRAM and ROM.

Further, the present invention can be applied to a multilayer wiring technique such as a printed wiring board.

[0384]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, when each of the first channel stopper region and the second channel stopper region overlaps at the boundary region, the impurity concentration of the region becomes high,
Since no active region is arranged in the boundary region, the junction breakdown voltage between the substrate and the device can be improved. Further, when the first channel stopper region and the second channel stopper region are separated from each other in the boundary region, a large inversion layer corresponding to the area thereof is likely to occur in the boundary region,
If an active region exists in the boundary region, the area of the element formed in the active region apparently increases by the addition of the inversion layer, and the amount of leakage current increases at the junction between the substrate and the element. Since no active region is arranged in the region, the amount of leak current can be reduced at the junction.

According to the present invention, the first MISFET
Since the gate length dimension is increased to improve the hot carrier breakdown voltage, the deterioration of the threshold voltage over time can be reduced, the electrical characteristics can be improved, and the second MIS can be improved.
The FET can reduce the power consumption by using the low voltage while ensuring the hot carrier breakdown voltage by using the low voltage. Moreover, the first MISFET has a long gate length and the second MISFET has the low voltage. Since the hot carrier breakdown voltage is improved by each use, the length of the low impurity concentration semiconductor region forming the LDD structure in the gate length direction can be independently controlled, and the first MISFE can be controlled.
The lengths of the low impurity concentration semiconductor regions of the T and second MISFETs in the gate length direction can be made substantially the same.

According to the present invention, the first MISFET,
Since all the forming steps of the second MISFET can also be used in common, and especially the respective side wall spacers can be formed in the same manufacturing step, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced.

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view of a DRAM which is Embodiment 1 of the present invention.

FIG. 2 is a partial cross-sectional perspective view of a resin-sealed semiconductor device that seals the DRAM.

FIG. 3 is a chip layout diagram of the DRAM.

FIG. 4 is an equivalent circuit diagram of a main part of a memory cell array of the DRAM.

FIG. 5 is a plan view of a main part of a memory cell array of the DRAM.

FIG. 6 is a plan view of relevant parts in a predetermined manufacturing process of the memory cell array of the DRAM.

FIG. 7 is a plan view of relevant parts in a predetermined manufacturing process of the memory cell array of the DRAM.

FIG. 8 is a diagram showing a relationship between a target voltage and a specific resistance value during sputtering of a film used for the DRAM.

FIG. 9 is a diagram showing a relationship between an X-ray incident angle and an X-ray diffraction spectrum of the film.

FIG. 10 is a diagram showing a relationship between an X-ray incident angle and an X-ray diffraction spectrum of the film.

FIG. 11 is a schematic plan view showing a boundary region between the memory cell array and peripheral circuits.

FIG. 12 is an enlarged plan view of an essential part of the boundary area.

FIG. 13 is a schematic plan view showing a boundary region between the memory cell array and peripheral circuits.

FIG. 14 is an enlarged plan view of an essential part of the boundary area.

FIG. 15 is a cross-sectional view of an essential part of the DRAM at another position.

FIG. 16 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM.

FIG. 17 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 18 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 19 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 20 is a fragmentary cross-sectional view showing each step of manufacturing the DRAM.

FIG. 21 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM.

FIG. 22 is a cross-sectional view of an essential part showing each manufacturing step of the DRAM.

FIG. 23 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 24 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM.

FIG. 25 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM.

FIG. 26 is a main-portion cross-sectional view showing each of the manufacturing steps of the D2AM.

FIG. 27 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 28 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM.

FIG. 29 is a cross-sectional view of essential parts showing each manufacturing step of the DRAM.

FIG. 30 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 31 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 32 is a cross-sectional view of an essential part showing each manufacturing step of the DRAM.

FIG. 33 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM.

FIG. 34 is a sectional view of a key portion showing each manufacturing step of the DRAM.

FIG. 35 is a sectional view of a key portion showing each step of manufacturing the DRAM.

FIG. 36 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 37 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 38 is a sectional view of a key portion showing each manufacturing step of the DRAM.

FIG. 39 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 40 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 41 is a sectional view of a key portion showing each manufacturing step of the D2AM.

FIG. 42 is a sectional view of a key portion showing each step of manufacturing the DRAM.

FIG. 43 is a cross-sectional view of essential parts for each manufacturing step of the DRAM.

FIG. 44 is a sectional view of a key portion showing each step of manufacturing the DRAM.

FIG. 45 is a cross-sectional view of an essential part showing each manufacturing step of the DRAM.

FIG. 46 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM.

FIG. 47 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM.

FIG. 48 is a cross-sectional view of essential parts showing each manufacturing step of the DRAM.

FIG. 49 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 50 is a cross-sectional view of a main part of a fuse element of the DRAM.

FIG. 51 is a main-portion cross-sectional view showing each of the manufacturing steps of the fuse element;

FIG. 52 is a sectional view of a key portion showing each step of manufacturing the fuse element.

FIG. 53 is a main-portion cross-sectional view showing each of the manufacturing steps of the fuse element;

FIG. 54 is a diagram showing a relationship between temperature and vapor pressure of a film used in the DRAM.

FIG. 55 is a diagram showing etching characteristics used in the DRAM.

FIG. 56 is a main-portion cross-sectional view of a DRAM which is Embodiment 2 of the present invention.

FIG. 57 is a main-portion cross-sectional view of a DRAM which is Embodiment 2 of the present invention.

FIG. 58 is a main-portion cross-sectional view of a DRAM which is Embodiment 2 of the present invention.

FIG. 59 is a main-portion cross-sectional view of a DRAM which is Embodiment 3 of the present invention.

FIG. 60 is a main-portion cross-sectional view of a DRAM which is Embodiment 3 of the present invention.

FIG. 61 (A) is a diagram showing the relationship between the deposition time of the film used in the DRAM and the gas flow rate, and FIG. 61 (B) is the deposition time of the film and the amount of reaction by-products generated. It is a figure which shows the relationship of.

FIG. 62 is a schematic configuration diagram of a CVD apparatus that is Embodiment IV of the present invention.

FIG. 63 is a schematic configuration diagram of a main part of the CVD apparatus.

FIG. 64 is a schematic configuration diagram of a main part of the CVD apparatus.

FIG. 65 is a time chart showing an opening / closing operation of a gas valve of the CVD apparatus according to the embodiment V of the present invention.

FIG. 66 is a time chart diagram showing a gas flow rate of the CVD apparatus.

FIG. 67 is a schematic configuration diagram of the CVD apparatus.

FIG. 68 is a main-portion cross-sectional view showing each manufacturing step of the DRAM which is Embodiment 6 of the present invention;

FIG. 69 is a fragmentary cross-sectional view showing each of the manufacturing steps of the DRAM according to the sixth embodiment of the present invention.

FIG. 70 is a main-portion cross-sectional view showing each manufacturing step of the DRAM which is Embodiment 6 of the present invention;

FIG. 71 is a main-portion cross-sectional view showing each manufacturing step of the DRAM which is Embodiment 6 of the present invention;

72 is a fragmentary plan view in the predetermined manufacturing process for the DRAM according to the embodiment VII of the present invention. FIG.

FIG. 73 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 74 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 75 is a cross-sectional view of an essential part showing each manufacturing step of the DRAM.

FIG. 76 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 77 is a plan view of a main portion of another example of the DRAM in a predetermined manufacturing process.

FIG. 78 is a main-portion cross-sectional view showing each of the manufacturing steps of another example of the DRAM.

FIG. 79 is a sectional view of a key portion showing each manufacturing step of another example of the DRAM.

FIG. 80 is a main-portion cross-sectional view showing each manufacturing step of another example of the DRAM;

81 is a main-portion cross-sectional view showing each manufacturing step of another example of the DRAM; FIG.

FIG. 82 is a sectional view of a key portion showing each manufacturing step of another example of the DRAM.

FIG. 83 is a main-portion cross-sectional view showing each of manufacturing steps of another example of the DRAM.

FIG. 84 is a sectional view of a key portion showing each manufacturing step of another example of the DRAM.

FIG. 85 is a sectional view of a key portion showing each manufacturing step of another example of the DRAM.

FIG. 86 is a sectional view of a key portion showing each manufacturing step of another example of the DRAM.

87 is a main-portion cross-sectional view showing each manufacturing step of another example of the DRAM; FIG.

88 is a main-portion cross-sectional view showing each manufacturing step of another example of the DRAM; FIG.

FIG. 89 is an alignment tree diagram of the DRAM according to the eighth embodiment of the present invention.

FIG. 90 is a fragmentary cross-sectional view of a target mark portion of a DRAM which is Embodiment 9 of the present invention.

FIG. 91 is a conceptual diagram of a photolithography technique used in the DRAM manufacturing process according to the tenth embodiment of the present invention.

FIG. 92 is a process flow chart of the photolithography technique.

FIG. 93 is a structural diagram of a material used in photolithography technology.

FIG. 94 is a diagram showing characteristics of the substance.

FIG. 95 is a view for explaining the effect of using the substance.

96 is a schematic plan view showing the structure of the semiconductor wafer according to the eleventh embodiment of the present invention. FIG.

FIG. 97 is an enlarged plan view of the semiconductor wafer.

98 is an enlarged plan view of the semiconductor wafer shown in FIG. 97. FIG.

[Fig. 99] Fig. 99 is a diagram for explaining an effect when the associative alignment method is applied.

[FIG. 100] A DRAM 1 according to a twelfth embodiment of the present invention.
FIG.

101 is a cross-sectional view of essential parts in a predetermined manufacturing process for the DRAM. FIG.

102 is a fragmentary cross-sectional view of a DRAM which is Embodiment 13 of the present invention. FIG.

FIG. 103 is a diagram showing a relationship between a target voltage and stress during sputtering of a film used in the DRAM.

FIG. 104 is a DRAM 1 according to a fourteenth embodiment of the present invention.
FIG.

FIG. 105 is a main-portion cross-sectional view showing each of the manufacturing steps of the DRAM;

FIG. 106 is a cross-sectional view of essential parts for each manufacturing step of the DRAM.

[Explanation of symbols]

In the figure, 1 ... DRAM, Qs ... MISF for memory cell selection
ET, C ... Stacked structure information storage capacitor, Q
n, Qp ... MISFET.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Osamu Tsuchiya 2326 Imai, Ome, Tokyo, Hitachi Device Development Center (72) Inventor Makoto Ogasawara 2326 Imai, Ome, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Fumio Otsuka 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Kazunori Torii 1-280, Higashi-Kengokubo, Kokubunji-shi, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Yu Isano 2326 Imai, Hitachi, Ltd. Device Development Center, Ome City, Tokyo (72) Inventor Shinro Owada 2326 Imai, Ome City, Tokyo, Ltd. Device Development Center, Hitachi Ltd. (72) Inventor, Mitsuaki Horiuchi Tokyo 2326 Imai, Ome City Co., Ltd. Hitachi, Ltd. Device Development Center (72) Inventor Go Tamaru, 2326 Imai, Ome City, Tokyo Metropolitan area, Hitachi Device Development Center (72) Inventor, Hideo Aoki 2326, Imai, Ome City, Tokyo Hitachi Device Development Center, Ltd. (72) Inventor Nobuhiro Otsuka 2326 Imai, Hitachi, Ltd. Ome-shi, Tokyo (72) Inventor Seiichiro Shirai 2326 Imai Imai, Ome, Tokyo (72) Inventor Sagawa (72) Inventor Sagawa Masakazu 2326 Imai, Ome, Tokyo Metropolitan area Hitachi Device Development Center (72) Inventor Yoshihiro Ikeda 2326 Imai, Ome city Tokyo Metropolitan area Hitachi Device Development Center (72) Inventor Toru Kaga Tokyo Kokubunji city 1-280 Higashi Koigokubo Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Tsuneoka, New Year 2326, Imai, Ome City, Tokyo Hitachi, Ltd. Deva (72) Inventor Tomoji Shinmei 2326 Imai, Ome City, Tokyo Metropolitan area Hitachi, Ltd. Device Development Center (72) Inventor Shuji Ogishi 2326 Imai, Ome city, Tokyo Hitachi Device Development Center Co., Ltd. (72) Inventor Osamu Kasahara 2326 Imai, Ome City, Tokyo Within Hitachi Device Development Center (72) Inventor Hiromitsu Enami 2326 Imai, Ome City, Tokyo Within Hitachi Device Development Center (72) Inventor Atsushi Wakahara 2326 Imai, Ome, Tokyo Metropolitan area Device Development Center, Hitachi, Ltd. (72) Inventor Hiroyuki Akimori 2326 Imai, Ome, Tokyo Metropolitan area Device Development Center, Hitachi, Ltd. (72) Inventor Shinichi Suzuki Ome, Tokyo 2326 Imai, Hitachi, Ltd. Device Development Center, Hitachi, Ltd. (72) Inventor Keisuke Funatsu 2326, Imai, Ome, Tokyo, Hitachi Device Development Center (72) ) Inventor Yoshinao Kawasaki 794, Higashitoyoi Higashitoyo, Shimomatsu, Yamaguchi Prefecture Inside the Kasado Plant, Hiritsu Manufacturing Co., Ltd. (72) Tsunehiko Tsubone 794 Higashitoyoi, Shimomatsu City, Yamaguchi Prefecture Inside the Kasado Plant, Hitate Manufacturing Co., Ltd. Masaka No No. 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hiritsu Super S.E. Engineering Co., Ltd. (72) Inventor Ken Tsugane 2326 Imai, Ome-shi, Tokyo Hitachi Device Development Center

Claims (8)

[Claims] 1. A semiconductor substrate including a well region of a first conductivity type having a first region and a second region adjacent thereto, and a first insulating film formed on a main surface of the semiconductor substrate of the second region. A second conductive type first and second semiconductor regions formed in the first region at a predetermined interval, and a second region located between the first and second semiconductor regions on the main surface of the semiconductor substrate. A memory cell selection MISFET including a gate electrode formed on an insulating film, and the first region formed on the main surface of the semiconductor substrate in the second region.
A third semiconductor region of a first conductivity type located below an insulating film; a first electrode connected to the second semiconductor region and containing an impurity of a second conductivity type extending on the gate electrode; An information storage capacitive element including a dielectric film formed on a first electrode and a second electrode formed on the dielectric film; and, in the first region, in the first and second semiconductor regions. A fourth semiconductor region of the first conductivity type formed in a lower portion, the first insulating film has a thickness larger than that of the second insulating film, and the second semiconductor region has The third semiconductor region is formed by self-aligning with the first insulating film, and the third semiconductor region is formed by introducing an impurity of a first conductivity type into the second region through the first insulating film. The fourth semiconductor region has the first conductivity type impurity introduced into the first region. By the third
A semiconductor integrated circuit device, which is formed in the same process as a semiconductor region. 2. The semiconductor integrated circuit device according to claim 1, wherein the impurity concentration of the third and fourth semiconductor regions is higher than the impurity concentration of the well region. 3. The second semiconductor region according to claim 2, wherein the second semiconductor region includes a first portion having a predetermined concentration and a second portion having a higher concentration than the first portion. Is a semiconductor integrated circuit device formed by diffusing impurities contained in the first electrode into the semiconductor substrate. 4. The memory cell array according to claim 3, further comprising a plurality of memory cells, each of which is composed of the memory cell selecting MISFET and the information storing capacitive element, arranged in a matrix, and a row in the memory cell array. A plurality of data lines extending in a direction, and a plurality of word lines extending in a column direction in the memory cell array, the data lines being connected to the first semiconductor region, the word lines Is connected to the gate electrode of the MISFET for memory cell selection, the semiconductor integrated circuit device. 5. A memory cell selecting MISFET including a source / drain region and a gate electrode, a first electrode, a dielectric film, and a second electrode on a semiconductor substrate having a first conductivity type well region. In a semiconductor integrated circuit device having a plurality of memory cells in which information storage capacitors are connected in series, a step of forming a first insulating film serving as an oxidation resistant mask in a first region of the main surface of the semiconductor substrate, The second insulating film of the semiconductor substrate is formed using the first insulating film as a mask.
Forming a second insulating film in the region, and applying a first energy with sufficient energy to pass through the second insulating film.
Ion-implanting a conductive type first impurity into the first and second regions of the main surface of the semiconductor substrate; and a film thickness smaller than that of the second insulating film in the first region of the main surface of the semiconductor substrate. And a step of forming a third insulating film, the memory cell selecting MISFET being formed on the third insulating film.
And forming one of the source and drain regions,
Self-aligning with the gate electrode and the second insulating film, implanting a second impurity of the second conductivity type into the main surface of the semiconductor substrate, and electrically connecting to one of the source and drain regions. Forming a first electrode containing impurities of the second conductivity type so as to extend over the gate electrode, and forming the dielectric film and the second electrode on the first electrode. A method of manufacturing a semiconductor integrated circuit device, the method comprising: 6. The semiconductor integrated device according to claim 5, further comprising a step of removing the first insulating film from the main surface of the semiconductor substrate before the step of ion-implanting the first impurity. Method of manufacturing circuit device. 7. The method according to claim 5, wherein a step of forming a fourth insulating film on the main surface of the semiconductor substrate is performed between the step of ion-implanting the second impurity and the step of forming the first electrode. Forming a sidewall on the sidewall of the gate electrode by anisotropically etching the fourth insulating film; and forming a fifth insulating film having an opening so that one of the source and drain regions is exposed. And a step of forming on the side wall, the method for manufacturing a semiconductor integrated circuit device. 8. The impurity according to claim 5, wherein the impurity contained in the first electrode is phosphorus, and the impurity contained in the first electrode diffuses into a semiconductor substrate to form the source and drain. A method of manufacturing a semiconductor integrated circuit device, comprising forming one of the regions.