JPH03263329A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03263329A JPH03263329A JP4008490A JP4008490A JPH03263329A JP H03263329 A JPH03263329 A JP H03263329A JP 4008490 A JP4008490 A JP 4008490A JP 4008490 A JP4008490 A JP 4008490A JP H03263329 A JPH03263329 A JP H03263329A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- diffusion region
- laminated
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000010030 laminating Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は半導体装置の製造方法に関し、更に詳しくは
サイドウオールを有するゲート電極部をマスクとしてシ
リコン基板上に拡散領域を形成してなる、いわゆるＬＤ
Ｄ構造のＭＯ３型メモリセルの製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device, in which a diffusion region is formed on a silicon substrate using a gate electrode portion having a sidewall as a mask. So-called LD
The present invention relates to a method of manufacturing a D-structure MO3 type memory cell.
（ロ）従来の技術
従来のこの種方法としては、第２図１こ示すように、ま
ず、Ｓｉ基板２１上に、ゲート酸化膜２２を介してゲー
ト材料としてのポリシリコン層、あるいはポリシリコン
層上にゲート特性を高く維持するためのＮＳＣ層を順次
積層し、ゲート電極作成用の所定パターンのレジスト層
２５を用い、フォトエツチングをおこなって上面にＮ５
ＧＩＩ！２４を有するゲート電極２３のゲート電極部３
０を形威し［第２図（ａ）参照］、レジスト層２５を除
去した後、ゲート電極部３０を含むＳｉ基板２１上に５
ｈｏｔ層を積層した後、これをＲＩＥにてエツチングし
てサイドウオール２６を形成する［第２図（ｂ）参照］
。(B) Conventional Technology As shown in FIG. 1, in the conventional method of this kind, first, a polysilicon layer or a polysilicon layer as a gate material is formed on a Si substrate 21 via a gate oxide film 22. NSC layers are sequentially laminated on top to maintain high gate characteristics, and photoetching is performed using a resist layer 25 with a predetermined pattern for forming a gate electrode to form an N5 layer on the top surface.
GII! Gate electrode part 3 of gate electrode 23 having 24
0 [see FIG. 2(a)], and after removing the resist layer 25, 5 is deposited on the Si substrate 21 including the gate electrode part 30.
After laminating the hot layer, this is etched by RIE to form the sidewall 26 [see FIG. 2(b)]
.
次に、ゲート電極部３０とサイドウオール２６をマスク
としてＡｓイオン２７の注入をおこない［第２図（ｃ）
参照］、続いて、熱処理を付してＳｉ基板２１上にソー
ス、ドレインの拡散領域２８を形成する［第２図（ｄ）
参照］。Next, As ions 27 are implanted using the gate electrode section 30 and the sidewalls 26 as masks [FIG. 2(c)]
[see FIG. 2(d)], followed by heat treatment to form source and drain diffusion regions 28 on the Si substrate 21 [FIG. 2(d)]
reference].
しかる後、全面に層間絶縁膜としてのＢＰＳＧ膜を積層
した後、ＢＰＳＧ膜にコンタクトホールを拡散領域２８
まで貫通するよう形成し、メタル配線をおこなってＭＯ
９Ｏ９型メモリセル成する。After that, after laminating a BPSG film as an interlayer insulating film on the entire surface, a contact hole is formed in the BPSG film in the diffusion region 28.
The MO
A 9O9 type memory cell is formed.
（ハ）発明が解決しようとする課題
しかし、Ａｓイオンの注入２７と熱処理によってサイド
ウオールエツジ部分２６ａ［第２図（ｄ）参照］や拡散
領域２８に結晶欠陥が発生するおそれがある。(c) Problems to be Solved by the Invention However, crystal defects may occur in the sidewall edge portion 26a (see FIG. 2(d)) and the diffusion region 28 due to the As ion implantation 27 and heat treatment.
すなわち、サイドウオール２６の形成の際にＲＩＥにて
エツチングをおこなうかあ、サイドウオールエツジ部分
２６ａはＳｉ基板表面に対して急峻に落ち込む形状に形
成され、しかも次工程のＡＳイオン注入の際に、Ｓｉ基
板２１の特に拡散領域となる部分に酸素の巻き込みが発
生し、それによってＡｓがトラップされて結晶欠陥２８
ａの発生を助長する。That is, whether etching is performed by RIE when forming the sidewall 26, the sidewall edge portion 26a is formed in a shape that is steeply depressed relative to the Si substrate surface. Oxygen entrainment occurs particularly in the portion of the Si substrate 21 that becomes the diffusion region, thereby trapping As and creating crystal defects 28.
It promotes the occurrence of a.
また、ＢＰＳＧ膜を形成する工程でこれが不純物となっ
て拡散領域２８に拡散するおそれがある。Further, in the step of forming the BPSG film, there is a possibility that this becomes an impurity and diffuses into the diffusion region 28.
その結果、電気的リークが発生し歩留りが低下する。As a result, electrical leakage occurs and yield decreases.
この発明は、ＬＤＤ構造を有する半導体装置を製造する
際に、拡散領域およびサイドウオールの結晶欠陥を防止
できろ半導体装置の製造方法を提供することを目的とす
るものである。An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent crystal defects in the diffusion region and sidewalls when manufacturing a semiconductor device having an LDD structure.
（ニ）課題を解決するための手段及び作用この発明は、
サイドウオールを有するゲート電極部をマスクとしてシ
リコン基板上に拡散領域を形成するに際して、ゲート電
極部にＳｉＯ２のサイドウオールを形成した後、ゲート
電極部およびサイドウオールを含むシリコン基板上面に
Ｓｔ！４膜を積層し、しかる後イオン注入および熱処理
をおこなって拡散領域を形成することを特徴とする半導
体装置の製造方法である。(d) Means and operation for solving the problem This invention includes:
When forming a diffusion region on a silicon substrate using a gate electrode portion having a sidewall as a mask, after forming a sidewall of SiO2 on the gate electrode portion, St! This method of manufacturing a semiconductor device is characterized in that four films are stacked, and then ion implantation and heat treatment are performed to form a diffusion region.
すなわち、この発明は、ＬＤＤ構造を有するゲート電極
部をマスクとしてイオン注入、熱処理をおこなってソー
ス、ドレインの拡散領域を形成する際、ＲＩＥにてゲー
ト電極部に５ｉｎ２のサイドウオールを形成した後、全
面にＳｉ３Ｎ４膜を堆積するようにしたので、サイドウ
オール形成時のＲＩＥダメージをＳｉ、Ｎ４膜で回復で
き、拡散領域になる部分に酸素が巻き込まれるのを抑制
できるとともに３−
サイドウオールエツジ部分の形状が急峻になるのを防止
でき、熱処理の際にサイドウオールやソース、ドレイン
に発生する結晶欠陥を防止できる。That is, in the present invention, when forming source and drain diffusion regions by performing ion implantation and heat treatment using the gate electrode part having an LDD structure as a mask, after forming a 5 in 2 side wall on the gate electrode part by RIE, Since the Si3N4 film is deposited on the entire surface, the RIE damage during sidewall formation can be recovered by the Si, N4 film, and oxygen can be suppressed from getting into the diffusion region. It is possible to prevent the shape from becoming steep, and it is possible to prevent crystal defects that occur in the sidewall, source, and drain during heat treatment.
この発明において、ゲート電極部とは、ゲート電極自体
であっても、上面にゲート特性を高く維持できるＮＳＣ
膜などの絶縁膜を有するゲート電極からなるものであっ
ても良い。In this invention, the gate electrode section refers to an NSC that can maintain high gate characteristics on the upper surface, even if it is the gate electrode itself.
The gate electrode may have an insulating film such as a film.
この発明において、５ＬＮｔ膜の膜厚ｄは１００〜４０
０大が好ましい［第１図（ｂ）参照］。In this invention, the film thickness d of the 5LNt film is 100 to 40
A value of 0 is preferable [see FIG. 1(b)].
（ホ）実施例 以下図に示す実施例にもとづいてこの発明を詳述する。(e) Examples The present invention will be described in detail below based on embodiments shown in the figures.
なお、これに上ってこの発明は限定を受けるものではな
い。It should be noted that the present invention is not limited beyond this.
第１図（ｅ）において、ＭＯ３型メモリセルは、Ｓｉ基
板ｌ上に５ｉ０２のゲート酸化膜２を介して、上面にＮ
Ｓ Ｃ膜４を有するポリシリコンのゲート電極３から
なるゲート電極部４３が形成され、このゲート電極部に
ＳｉＯ２のサイドウオール６が形成され、ゲート電極部
４３およびサイドウオール６を含Ｕ Ｓ ｉ基板上の全
面に膜厚ｄが２００ÅのＳｉ３Ｎ、膜９が形成され、さ
らにそのＳｉ、Ｎ、膜上に、ソース、ドレインの拡散領
域１０に通ずるコンタクトホール１１とメタル配線部１
２が形成されたＢＰＳＧ膜１３が配設されている。In FIG. 1(e), the MO3 type memory cell has a gate oxide film 2 of 5i02 on the Si substrate l, and N2 on the upper surface.
A gate electrode part 43 consisting of a polysilicon gate electrode 3 having an SC film 4 is formed, a sidewall 6 of SiO2 is formed on this gate electrode part, and a US i substrate including the gate electrode part 43 and the sidewall 6 is formed. A Si3N film 9 with a thickness d of 200 Å is formed on the entire surface, and contact holes 11 and metal wiring portions 1 are formed on the Si, N film, which communicate with the source and drain diffusion regions 10.
A BPSG film 13 having 2 formed thereon is disposed.
以下、製造方法について説明する。The manufacturing method will be explained below.
第１図に示すように、まず、Ｓｉ基板り上に、ゲート酸
化膜２を介してゲート材料としてのポリシリコン層、Ｎ
ＳＧ層を順次積層し、ゲート電極形成用の所定パターン
のレジスト層５を用い、フォトエツチングをおこなって
上面にＮＳＣ膜４を有するゲート電極３のゲート電極部
４３を形成し［第１図（ａ）参照］、レジスト層５を除
去した後、これらの上に５ｉ０２層を積層した後、これ
をＲＩＥにてエツチングしてサイドウオール６を形威し
、続いて、全面に５ｉａＮ−膜９を膜厚ｄが２００Ａで
積層する［第１図（ｂ）参照］。As shown in FIG. 1, first, a polysilicon layer as a gate material, an N
The SG layers are sequentially laminated, and photoetching is performed using a resist layer 5 with a predetermined pattern for forming a gate electrode to form a gate electrode portion 43 of the gate electrode 3 having an NSC film 4 on the upper surface [see Fig. 1(a)]. ), after removing the resist layer 5, a 5i02 layer is deposited on top of these, and then etched by RIE to form a sidewall 6, and then a 5iaN- film 9 is deposited on the entire surface. The layers are laminated with a thickness d of 200A [see FIG. 1(b)].
次に、ゲート電極部４３とサイドウオール６をマスクと
してＡｓイオン７をｔ ｘ ｔｏ” −ｔ ｘ ｔｏ１
６のドーズ量で注入をおこない［第１図（ｃ）参照］、
続いて、８００〜９５０℃の熱処理を付してＳｉ基板１
上にソース、ドレインの拡散領域ｌＯを形成する〔第１
図（、（）参照コ。Next, using the gate electrode part 43 and the sidewall 6 as a mask, As ions 7 are irradiated with t x to" - t x to1
The implantation was carried out at a dose of 6 [see Fig. 1(c)].
Subsequently, the Si substrate 1 is subjected to heat treatment at 800 to 950°C.
Form source and drain diffusion regions 1O on top [first
See figure (, ().
しかる後、全面に層間絶縁膜としてのＢＰＳＧ膜１３膜
種３した後、そのＢＰＳＧ膜にコンタクトホール１１を
拡散領域１０に貫通するよう形威し、メタル配線１２を
おこなってＭＯ３型メモリセルを形成する。After that, a BPSG film 13 as an interlayer insulating film is coated on the entire surface, and a contact hole 11 is formed in the BPSG film so as to penetrate into the diffusion region 10, and a metal wiring 12 is formed to form an MO3 type memory cell. do.
このようにして従来法では、サイドウオール２６がＲＩ
ＥエッチやＡｓイオン２７の注入のダメージにさらに熱
処理が加わることで、サイドウオールエツジ部分２６ａ
や拡散領域２８に結晶欠陥２８ａが発生するのを防止で
きる。すなわち、本実施例では、５ｉＪ４膜９をサイド
ウオール６を含むＳｉ基板全面に堆積する事により、サ
イドウオールエツジ部分は急峻にならず、しかもＡｓイ
オン７の注入時も酸素の巻き込みがないため、Ａｓイオ
ン７がトラップされて拡散領域ＬＯやサイドウオールエ
ツジ部分６ａに結晶欠陥が発生するのを抑制できる。又
、ＢＰＳＧ膜１３中の不純物が拡散領域ｌＯに拡散する
のを防止できる。In this way, in the conventional method, the sidewall 26 is
By further adding heat treatment to the damage caused by E-etching and implantation of As ions 27, the sidewall edge portion 26a
Also, crystal defects 28a can be prevented from occurring in the diffusion region 28. That is, in this example, by depositing the 5iJ4 film 9 over the entire surface of the Si substrate including the sidewalls 6, the sidewall edge portions do not become steep, and oxygen is not involved when As ions 7 are implanted. It is possible to suppress the trapping of the As ions 7 and the generation of crystal defects in the diffusion region LO and the sidewall edge portion 6a. Further, it is possible to prevent impurities in the BPSG film 13 from diffusing into the diffusion region IO.
その結果、デバイスの電気的特性を安定にでき、歩留り
を向上てきる。As a result, the electrical characteristics of the device can be stabilized and the yield can be improved.
（へ）発明の効果
以上のようにこの発明によれば、ＬＤＤ構造を有するゲ
ート電極部をマスクとしてイオン注入、熱処理をおこな
って８１基板上に拡散領域を形成する際、Ｒ（Ｅにてゲ
ート電極部に５ｉｆｔのサイドウオールを形成後、ゲー
ト電極部およびサイドウオールを含むＳｉ基板上に、全
面に、５ｉｓＮ４膜を堆積するようにしたので、サイド
ウオール形成時のＲＩＥダメージをＳｉ３Ｎ４膜で回復
でき、サイドウオールエツジ部分も形状が急峻にならず
、熱処理の際、結晶欠陥はできにくくなり、無欠陥なサ
イドウオールおよび拡散領域を形成でき、その結果、デ
バイスの電気的特性を安定化できるとともに、歩留りを
向上できる効果がある。(F) Effects of the Invention As described above, according to the present invention, when forming a diffusion region on an 81 substrate by performing ion implantation and heat treatment using the gate electrode portion having an LDD structure as a mask, After forming a 5ift sidewall on the electrode part, a 5isN4 film was deposited on the entire surface of the Si substrate including the gate electrode part and the sidewall, so that the RIE damage during sidewall formation could be recovered by the Si3N4 film. , the shape of the sidewall edges does not become steep, and crystal defects are less likely to occur during heat treatment, making it possible to form defect-free sidewalls and diffusion regions.As a result, the electrical characteristics of the device can be stabilized, and This has the effect of improving yield.
第１図はこの発明の一実施例を示す製造工程説明図、第
２図は従来例を示す製造工程説明図である。
＝７
１・・・・・Ｓｉ基板、２・・・・・・ゲート酸化膜、
３・・・・・・ゲート電極、６・・・・・・サイドウオ
ール、６ａ・・・・・サイドウオールエツジ部分、７・
・・・・Ａｓイオン、
９・・・・・・Ｓｉ３Ｎ４膜、ＩＯ・・・・・・拡散領
域、４３・・・・・・ゲート電極部。
９FIG. 1 is a manufacturing process explanatory diagram showing an embodiment of the present invention, and FIG. 2 is a manufacturing process explanatory diagram showing a conventional example. =7 1...Si substrate, 2...gate oxide film,
3...Gate electrode, 6...Side wall, 6a...Side wall edge portion, 7...
...As ion, 9...Si3N4 film, IO...diffusion region, 43...gate electrode part. 9
Claims (1)
てシリコン基板上に拡散領域を形成するに際して、ゲー
ト電極部にＳｉＯ＿２のサイドウォールを形成した後、
ゲート電極部およびサイドウォールを含むシリコン基板
上面にＳｉ＿３Ｎ＿４膜を積層し、しかる後イオン注入
および熱処理をおこなって拡散領域を形成することを特
徴とする半導体装置の製造方法。1. When forming a diffusion region on a silicon substrate using the gate electrode part having sidewalls as a mask, after forming a sidewall of SiO_2 on the gate electrode part,
1. A method of manufacturing a semiconductor device, comprising: laminating a Si_3N_4 film on the upper surface of a silicon substrate including a gate electrode portion and sidewalls, and then performing ion implantation and heat treatment to form a diffusion region.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4008490A JPH03263329A (en) | 1990-02-20 | 1990-02-20 | Manufacture of semiconductor device |
| US07/932,746 US5298446A (en) | 1990-02-20 | 1992-08-25 | Process for producing semiconductor device |
| US07/979,457 US5420079A (en) | 1990-02-20 | 1992-11-20 | Process for producing semiconductor device comprising two step annealing treatment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4008490A JPH03263329A (en) | 1990-02-20 | 1990-02-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03263329A true JPH03263329A (en) | 1991-11-22 |
Family
ID=12571033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4008490A Pending JPH03263329A (en) | 1990-02-20 | 1990-02-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03263329A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6394683A (en) * | 1986-10-08 | 1988-04-25 | Sony Corp | Manufacture of semiconductor device |
| JPS64760A (en) * | 1987-06-23 | 1989-01-05 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH0278229A (en) * | 1988-09-13 | 1990-03-19 | Nec Corp | Field-effect transistor and its manufacture |
-
1990
- 1990-02-20 JP JP4008490A patent/JPH03263329A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6394683A (en) * | 1986-10-08 | 1988-04-25 | Sony Corp | Manufacture of semiconductor device |
| JPS64760A (en) * | 1987-06-23 | 1989-01-05 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH0278229A (en) * | 1988-09-13 | 1990-03-19 | Nec Corp | Field-effect transistor and its manufacture |
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