JPH05267330A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPH05267330A JPH05267330A JP9206792A JP9206792A JPH05267330A JP H05267330 A JPH05267330 A JP H05267330A JP 9206792 A JP9206792 A JP 9206792A JP 9206792 A JP9206792 A JP 9206792A JP H05267330 A JPH05267330 A JP H05267330A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- film
- polysilicon
- mos semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 230000001133 acceleration Effects 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 9
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 9
- 239000013078 crystal Substances 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＬＤＤ構造のＭＯＳ型
半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS type semiconductor device having an LDD structure.
【０００２】[0002]
【従来の技術】従来のＬＤＤ構造のＭＯＳ型半導体装置
は図２に示すように、シリコン基板１上に素子分離用フ
ィールド酸化膜２を形成したのち、下層のゲート電極と
なるポリシリコン膜及び上層のゲート電極となるタング
ステンシリサイド膜を形成し、パターニングして下層の
ポリシリコン電極４Ａ及び上層のタングステンシリサイ
ド電極５Ａを形成する。2. Description of the Related Art In a conventional LDD structure MOS type semiconductor device, as shown in FIG. 2, after forming an element isolation field oxide film 2 on a silicon substrate 1, a polysilicon film to be a lower gate electrode and an upper layer are formed. A tungsten silicide film to be a gate electrode is formed and patterned to form a lower polysilicon electrode 4A and an upper tungsten silicide electrode 5A.
【０００３】次に、低濃度層６をイオン注入により形成
し、酸化シリコン膜を堆積し、ドライエッチングにより
前記酸化シリコン膜のエッチバックを行いゲート電極側
面部のみに酸化シリコン膜からなるサイドウォール８を
形成後、高濃度層７をイオン注入により形成していた。Next, a low-concentration layer 6 is formed by ion implantation, a silicon oxide film is deposited, and the silicon oxide film is etched back by dry etching to form a sidewall 8 made of the silicon oxide film only on the side surface of the gate electrode. After forming, the high concentration layer 7 was formed by ion implantation.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上述し
た従来のＬＤＤ構造のＭＯＳ型半導体装置の製造方法
は、サイドウォールの応力によりシリコン基板に結晶欠
陥が形成されやすく、歩留りが低下するという欠点があ
った。However, the above-described conventional method for manufacturing a MOS type semiconductor device having an LDD structure has a drawback that crystal defects are easily formed on the silicon substrate due to the stress of the side wall and the yield is reduced. It was
【０００５】本発明の目的は、サイドウォールに起因し
た結晶欠陥による歩留り低下を防止するＭＯＳ型半導体
装置の製造方法を提供することにある。An object of the present invention is to provide a method of manufacturing a MOS type semiconductor device which prevents a yield reduction due to crystal defects caused by sidewalls.
【０００６】[0006]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係るＭＯＳ型半導体装置の製造方法は、半
導体基板上の酸化シリコン膜上にポリシリコン膜とシリ
サイド膜とを順次形成した後、パターニングしてポリシ
リコン膜とシリサイド膜との２層からなるゲート電極を
形成するＬＤＤ構造のＭＯＳ型半導体装置の製造方法で
あって、前記ポリシリコン電極の寸法より大きい前記シ
リサイド電極上から質量数の異なる同タイプの不純物イ
オンを異なる加速エネルギーで注入するものである。In order to achieve the above-mentioned object, a method of manufacturing a MOS type semiconductor device according to the present invention comprises a step of forming a polysilicon film and a silicide film on a silicon oxide film on a semiconductor substrate in order. A method for manufacturing a MOS type semiconductor device having an LDD structure, in which a gate electrode composed of two layers of a polysilicon film and a silicide film is patterned to form a gate electrode, the mass number of which is larger than the size of the polysilicon electrode Different types of impurity ions of different types are implanted with different acceleration energies.
【０００７】[0007]
【作用】ポリシリコン電極の寸法より大きいシリサイド
電極上から質量数の異なる同タイプの不純物イオンを異
なる加速エネルギーで注入することにより、サイドウォ
ールをもたない構造とする。Function: Impurity ions of the same type having different mass numbers are implanted at different acceleration energies from above the silicide electrode, which is larger than the size of the polysilicon electrode, to form a structure having no sidewall.
【０００８】[0008]
【実施例】以下、本発明の一実施例を図により説明す
る。図１（ａ）〜（ｅ）は、本発明の実施例に係るＬＤ
Ｄ構造のＭＯＳ型半導体装置を製造する方法を工程順に
示した断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1A to 1E are LDs according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a method of manufacturing a MOS semiconductor device having a D structure in the order of steps.
【０００９】まず、図１（ａ）に示すように、シリコン
基板１上に厚さ６０００Åの素子分離用のフィールド酸
化膜２を形成したのち、ＭＯＳトランジスタを形成する
能動領域にゲート絶縁膜となる酸化シリコン膜３を２５
０Åの厚さに形成する。First, as shown in FIG. 1A, a field oxide film 2 for element isolation having a thickness of 6000 Å is formed on a silicon substrate 1, and then a gate insulating film is formed in an active region for forming a MOS transistor. 25 silicon oxide film 3
Form to a thickness of 0Å.
【００１０】次に、図１（ｂ）に示すように、減圧ＣＶ
Ｄ法により下層のゲート電極となるポリシリコン膜４を
２０００Åの厚さに形成する。Next, as shown in FIG. 1B, the reduced pressure CV
A polysilicon film 4 to be a lower gate electrode is formed to a thickness of 2000 Å by the D method.
【００１１】次いで、図１（ｃ）に示すように、スパッ
タ法によりタングステンシリサイド膜５を２３００Åの
厚さに形成する。Next, as shown in FIG. 1C, a tungsten silicide film 5 is formed to a thickness of 2300Å by a sputtering method.
【００１２】次いで図１（ｄ）に示すようにフォトリソ
グラフィー工程によりパターニングし、リアクティブイ
オンエッチングにより上層のタングステンシリサイド膜
５、及び下層のポリシリコン膜４をエッチングし、タン
グステンシリサイド電極５Ａ、ポリシリコン電極４Ａを
形成する。Next, as shown in FIG. 1D, patterning is performed by a photolithography process, and the upper tungsten silicide film 5 and the lower polysilicon film 4 are etched by reactive ion etching to obtain the tungsten silicide electrode 5A and the polysilicon. The electrode 4A is formed.
【００１３】次いでフォトリソグラフィー工程によりフ
ィールド酸化膜をカバーするようにレジストをパターニ
ングし、さらにＳｉＯ2に対して２００Å／ｍｉｎ程度
のエッチングレートが得られるように調合したバッファ
ードフッ酸を用いて３０分程度エッチングし、下層のポ
リシリコン電極４Ａを０．３μｍ程度エッチングし、そ
の後フォトレジストを除去する。Then, a resist is patterned by a photolithography process so as to cover the field oxide film, and buffered hydrofluoric acid prepared so as to obtain an etching rate of about 200 Å / min with respect to SiO 2 is used for 30 minutes. To about 0.3 .mu.m, the lower polysilicon electrode 4A is etched, and then the photoresist is removed.
【００１４】上述のエッチング時間を加減し最適の特性
が得られるよう設定可能であり、プロセスの自由度が本
発明では大きくなっている。The above etching time can be adjusted so that optimum characteristics can be obtained, and the degree of freedom of the process is increased in the present invention.
【００１５】次いで図１（ｅ）に示すように、タングス
テンシリサイド電極５Ａを通過するが、ポリシリコン電
極４Ａを通過しない加速エネルギー、例えばＢ（プラ
ス）の場合１００ＫｅＶ程度で５×１０13ａｔｍ／ｃｃ
のイオンを注入し、低濃度層６を形成する。Then, as shown in FIG. 1 (e), the acceleration energy which passes through the tungsten silicide electrode 5A but does not pass through the polysilicon electrode 4A, for example, in the case of B (plus), is 5 × 10 13 atm / cc at about 100 KeV.
Ions are implanted to form the low concentration layer 6.
【００１６】次いで、タングステン電極５Ａを通過しな
い加速エネルギー、例えばＢＦ2（プラス）の場合３０
ＫｅＶ程度で５×１０15ａｔｍ／ｃｃのイオンを注入
し、高濃度層７を形成することにより、ＬＤＤ構造のＭ
ＯＳ型半導体装置を製造することができる。Next, acceleration energy that does not pass through the tungsten electrode 5A, for example, 30 in the case of BF 2 (plus)
By implanting ions of 5 × 10 15 atm / cc at about KeV and forming the high concentration layer 7, M of the LDD structure is formed.
An OS type semiconductor device can be manufactured.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、ポリシリ
コン膜とシリサイド膜からなるゲート電極を有するＬＤ
Ｄ構造のＭＯＳ型半導体装置において、サイドウォール
が存在せず、サイドウォールに起因したシリコン基板に
発生する結晶欠陥が全く無く、良好な歩留りが得られ
る。As described above, the present invention is an LD having a gate electrode composed of a polysilicon film and a silicide film.
In the MOS semiconductor device having the D structure, there is no sidewall, no crystal defects are generated in the silicon substrate due to the sidewall, and a good yield can be obtained.
【００１８】さらに、サイドウォールの形成工程が不用
であり、製造工程が短縮され、低コストで製造できる。Further, the side wall forming step is unnecessary, the manufacturing step is shortened, and the manufacturing can be performed at low cost.
【図１】本発明の一実施例を工程順に示した断面図であ
る。FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.
【図２】従来の製造方法を示す断面図である。FIG. 2 is a cross-sectional view showing a conventional manufacturing method.
１ シリコン基板 ２ フィールド酸化膜 ３ 酸化シリコン膜 ４ ポリシリコン膜 ４Ａ ポリシリコン電極 ５ タングステンシリサイド膜 ５Ａ タングステンシリサイド電極 ６ 低濃度層 ７ 高濃度層 ８ サイドウォール ９ レジスト 1 Silicon substrate 2 Field oxide film 3 Silicon oxide film 4 Polysilicon film 4A Polysilicon electrode 5 Tungsten silicide film 5A Tungsten silicide electrode 6 Low concentration layer 7 High concentration layer 8 Sidewall 9 Resist
Claims (1)
シリコン膜とシリサイド膜とを順次形成した後、パター
ニングしてポリシリコン膜とシリサイド膜との２層から
なるゲート電極を形成するＬＤＤ構造のＭＯＳ型半導体
装置の製造方法であって、 前記ポリシリコン電極の寸法より大きい前記シリサイド
電極上から質量数の異なる同タイプの不純物イオンを異
なる加速エネルギーで注入することを特徴とするＭＯＳ
型半導体装置の製造方法。1. An LDD structure in which a polysilicon film and a silicide film are sequentially formed on a silicon oxide film on a semiconductor substrate and then patterned to form a gate electrode composed of two layers of the polysilicon film and the silicide film. A method of manufacturing a MOS type semiconductor device, characterized in that impurity ions of the same type having different mass numbers are implanted at different acceleration energies from above the silicide electrode, which is larger than the size of the polysilicon electrode.
Type semiconductor device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9206792A JPH05267330A (en) | 1992-03-18 | 1992-03-18 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9206792A JPH05267330A (en) | 1992-03-18 | 1992-03-18 | Manufacture of mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05267330A true JPH05267330A (en) | 1993-10-15 |
Family
ID=14044128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9206792A Pending JPH05267330A (en) | 1992-03-18 | 1992-03-18 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05267330A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6962853B2 (en) | 2000-01-20 | 2005-11-08 | Matsushita Electronic Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2007294836A (en) * | 2006-03-27 | 2007-11-08 | Yamaha Corp | Manufacturing method of insulating gate field effect transistor |
-
1992
- 1992-03-18 JP JP9206792A patent/JPH05267330A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6962853B2 (en) | 2000-01-20 | 2005-11-08 | Matsushita Electronic Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2007294836A (en) * | 2006-03-27 | 2007-11-08 | Yamaha Corp | Manufacturing method of insulating gate field effect transistor |
| JP4725451B2 (en) * | 2006-03-27 | 2011-07-13 | ヤマハ株式会社 | Insulated gate field effect transistor manufacturing method |
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