JP3127483B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a manufacturing method required for miniaturization of a device for high speed and high integration of a semiconductor device.

[0002] With the development of a highly information-oriented society, faster information processing is required. For that purpose, a computer that performs high-speed arithmetic processing is required.
The need for highly integrated semiconductor devices has led to an urgent need to develop and manufacture fine transistors.

[0003]

2. Description of the Related Art Miniaturization techniques around a base / emitter have been most actively developed to increase the speed of a bipolar transistor. (Here, it is called base / emitter peripheral technology.) FIG. 7 is a diagram for explaining a conventional base / emitter peripheral technology.

As shown in FIG. 7 (a), silicon (Si)
Chemical Vapor Depositio as an insulating film on the substrate 51
n (CVD) silicon dioxide (SiO ₂ ) film 52, boron (B) doped poly-Si film 53 as a conductive film, and a CVD SiO ₂ film 5
After depositing 4, a base opening is provided by etching with a resist mask to expose the Si substrate 51. Next,
As shown in FIG. 7 (b), after depositing poly-Si on the entire surface, anisotropic etching by reactive ion etching (RIE) is performed to form a sidewall 55 made of poly-Si.
Next, as shown in FIG. 7 (c), the upper end portion of the sidewall 55 is etched and removed from the upper end of the CVD SiO ₂ film 54 to form a first sidewall 56. Next, as shown in FIG. 7 (d), after depositing a CVD SiO ₂ film on the entire surface, anisotropic etching is performed to form a _second SiO ₂ film on the first sidewall 56.
Is formed. A specific forming method will be described later in detail. As shown in Fig. 7 (e), poly-Si
The first side wall 56 made of CVD SiO ₂ is covered with a second side wall 57 and is electrically insulated from an emitter electrode 58 formed in a subsequent step.

However, in the method shown in FIG. 7, if the upper end portion of the side wall 55 made of poly-Si is removed by anisotropic etching, the second side as shown in FIG. A portion where the first sidewall 56 is incompletely covered with the sidewall 57 occurs, and a poor electrical insulation occurs between the first sidewall 56 and the emitter electrode 58. Conversely, when the upper end portion removed by etching the first side wall 55 made of poly-Si is large, as shown in FIG. 8B, the first side wall 56 and the B-doped poly-silicon are removed. The contact with the Si film 53 is incomplete, so that the connection between the base layer and the extraction electrode is incomplete, and good transistor characteristics cannot be obtained.

That is, the amount of the upper end portion removed by the etching of the first sidewall 55 needs to be accurately controlled. One method of forming a structure as shown in FIG. 7 (c) by removing a predetermined amount of the upper end portion of the first sidewall 55 by etching is to perform anisotropic etching as shown in FIG. 9 (a). In this method, the substrate 51 is formed by over-etching.

As another method, as shown in FIG. 9 (b1), a poly-Si film 61 is first deposited on the entire surface, and then a photoresist is applied thereon, followed by anisotropic etching. The resist film 62 is left only in the base opening. Next, as shown in FIG. 9 (b2), the side wall 61 is anisotropically etched using the resist
The upper end portion of the film 62 is removed. Thereafter, as shown in FIG. 9 (b3), the resist film 62 is removed, and the portion of the poly-Si film 61 which is covered under the resist film 62 is again removed by anisotropic etching, and the first side is removed. The wall 63 is formed.

[0008]

However, in the method of FIG. 9A, however, 1) the amount of the upper end portion of the first sidewall 55 to be removed is controlled by the oversize of the anisotropic etching. Therefore, it is difficult to control this stably. 2) Since the silicon substrate 51 is over-etched, a crystal defect is introduced into that portion. This leads to a decrease in product yield and reliability. 3) Due to the step formed in the Si substrate 51, the outer base region 60 formed by the first sidewall 56 and the inner base region 59
Electrical connection failure occurs between the two. This also leads to a decrease in product yield and reliability.

In the method of FIG. 9B, 4)
Although the problems 2) and 3) are solved, similar to the method in Fig. 9 (a),
The amount of the removed upper end portion of the first sidewall 55 is
It is difficult to stably control the anisotropic etching because it is controlled by the over amount. 5) Increasing the number of resist embedding steps leads to complicated steps and high costs.

These two conventional methods have five problems to be solved as described above. Therefore, the present invention is capable of stably reducing the amount of the upper end portion of the first sidewall of the base opening to be removed by etching without reducing the yield and reliability and complicating the process.
It is an object of the present invention to provide a method controlled with high accuracy.

[0011]

SUMMARY OF THE INVENTION The above-mentioned problem is caused by a step of sequentially depositing a first CVD SiO ₂ and a first poly-Si on a field region of a Si substrate and then forming an opening reaching the Si substrate. ,
Depositing a second poly-Si on the entire surface, performing anisotropic etching to form a first sidewall made of poly-Si on the side wall of the opening, and then forming a first side wall on the exposed side of the Si substrate in the opening. Depositing a _second CVD SiO ₂ on the entire surface so as to be thinner and thicker on the first poly-Si outside the opening; and removing the _second SiO ₂ layer inside the opening. Etching the _second CVD SiO ₂ film such that the second SiO ₂ layer outside the opening remains without being removed, and on the first sidewall made of the second poly-Si, The problem is solved by a method including a step of forming a second sidewall made of the second SiO ₂ .

FIG. 1 is a diagram illustrating the principle of the present invention. Fig. 1 (a)
As shown in FIG. 1, a CVD SiO ₂ layer 2 is formed on the surface of a Si substrate 1, and then a poly-Si layer 3 is deposited thereon. Next, a poly-Si film is deposited on the entire surface, and anisotropic etching is performed to form a poly-Si sidewall 4 on the side wall of the opening.

Next, as shown in FIG.
The CVD SiO ₂ film 5 is deposited, and the thickness of the CVD SiO ₂ is thinner at the bottom of the opening and thicker outside the opening. Next, when anisotropic etching is performed, as shown in FIG. 1 (c), the CVD SiO ₂ film 5 is left outside the opening, and the CVD S
The iO ₂ film is removed, and the side wall 4 of poly-Si is formed by CVD SiO ₂
Covered by membrane 5.

[0014]

Operation In the present invention, as shown in FIG.
Since the amount of the upper end portion of the first sidewall to be removed, that is, the height of the first sidewall 4 is determined by the sum of the thicknesses of the CVD SiO ₂ layer 2 and the poly-Si layer 3, the controllability is improved. Very good. That is, problems 1) and 4) are solved.

Further, since there is no over-etching on the Si substrate, there is no problem of crystal defects. Therefore, the yield and reliability of the product are increased. This solves problem 2). Also, since there is no over-etching on the Si substrate,
There is no step as shown in FIG. 9 (a). Therefore, there is no occurrence of electrical connection failure between the external base region 60 and the internal base region 59. Therefore, the yield and reliability of the product are improved. This will solve problem 3).

[0016] In addition, the problem 4) of the method of FIG.
Is resolved as in 1). In addition, the step of burying the resist, which is indispensable in the method of FIG. 9 (b), is omitted, and the insulating layer on the surface and the insulating layer on the side walls are formed at the same time. Time is reduced. As a result, costs are reduced. This solves problem 5).

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Two embodiments of the present invention will now be described with reference to the drawings. First Embodiment FIG. 4 is a view for explaining each step when the manufacturing method of the present invention is applied to the manufacture of a bipolar transistor.

As shown in FIG. 4A, a 200 nm thick CVD SiO ₂ film 2 is deposited on a Si substrate 1 by a conventional method, and then a 300 nm thick boron-doped poly-Si film is formed thereon. Deposit 3

As shown in FIG. 4B, the resist is patterned and a CVD SiO ₂ film is formed by using an anisotropic etching method.
2 and a base opening reaching the Si substrate 1 through the boron-doped poly-Si film 3.After depositing 100-nm-thick poly-Si over the entire surface, anisotropic etching equivalent to 100 nm is performed to About 100 nm thick sidewall 4
To form

Next, as shown in FIG. 4 (c), a CVD SiO ₂ film was deposited as a through film for ion implantation to a thickness of 30 nm (not shown), the energy was 30 KeV, and the dose was 3 × 10 ¹³ cm ⁻² . The internal base region 7 is formed by performing boron ion implantation. After that, 400 nm thick C using 1% silane (SiH ₄ )
A VD SiO ₂ film 5 is deposited on the entire surface. In this case, only 240 nm thickness is deposited on the bottom of the opening. This takes advantage of the fact that the growth gas does not flow into the openings. (Experiment A described later) In this step, a 30-nm CVD SiO ₂ film is deposited as a through film for ion implantation, but this step can be omitted.

Next, as shown in FIG. 4 (d), the CVD SiO ₂ film 5 outside the opening is etched by about 156 nm using an anisotropic etching method, so that a 240 nm thick layer is formed at the bottom of the opening. CV
Although the D SiO ₂ film 5 is removed and an exposed portion of the Si substrate 1 is generated,
Doped poly-Si film 3 and sidewall 4 are approximately 244 nm thick
The state covered with the CVD SiO ₂ film 5 is formed. This utilizes the fact that the etching rate at the bottom of the opening is 35% higher than the etching rate outside the opening.
(Experiment B described later) Finally, a poly-Si layer 6 having a thickness of 100 nm is deposited, and arsenic (As) ions are implanted for forming an emitter.
Conditions for ion implantation are energy of 40 KeV and dose of 1x10.
¹⁶ cm ^-2 . Next, in a dry oxygen atmosphere, 1
Heat treatment at 100 ° C for 20 seconds. This heat treatment
As in the Si layer 6 diffuses into the internal base region 7, and an emitter region 8 is formed. At the same time, the boron in the doped poly-Si film 3 diffuses into the sidewalls 4 and further diffuses into the Si substrate 1 to form an external base region, and at the same time, in the step shown in FIG. Activate the implanted boron. Thus, a base portion connecting the external base and the internal base is formed, and the base region 9 is completed. This state is shown in FIG.

The base region 9 may be formed by depositing a doped Si layer instead of introducing impurities. Second Embodiment FIGS. 5 and 6 are diagrams illustrating each step when the manufacturing method of the present invention is applied to MOS transistor manufacturing.

As shown in FIG. 5A, a 200-nm thick CVD SiO ₂ film 2 is deposited on a Si substrate 1 by a conventional method, and a 300-nm thick poly-Si film 3 is deposited thereon. I do. Next, ion implantation is performed on the entire surface of the poly-Si film 3. When the MOS transistor to be formed is an n-channel type, the ion implantation conditions are As, the energy is 70 KeV, and the dose is 4 × 10 ¹⁵ cm.
^In the case of ^-2 , p-type channel, the energy is 60 KeV and the dose is 1.5 x 10 ¹⁵ cm ^-2 using BF2.

As shown in FIG. 5B, the resist is patterned and the CVD SiO ₂ film is formed by using an anisotropic etching method.
2 and a device region opening reaching the Si substrate 1 through the poly-Si film 3 is provided.Next, a 100 nm-thick poly-Si is deposited on the entire surface, and then anisotropic etching equivalent to 100 nm is performed. Remove the poly-Si film and apply a thickness of approx.
A sidewall 4 made of 100 nm poly-Si is formed.

Next, as shown in FIG.
m, 1% silane (SiH_Four) Using CVDSiO_TwoFilm 5 is deposited on the entire surface.
Stack. In this case, the bottom of the opening only has a thickness of 240 nm.
It will not be deposited. This is due to the growth gas in the opening.
We take advantage of the fact that the wraparound is small. (
A) Next, as shown in Fig. 5 (d), anisotropic etching
CVD SiO outside the opening using the method_TwoEtch film 5 to 156 nm
In this way, a 240 nm thick CVD SiO _TwoMembrane 5
Is removed, and an exposed portion of the Si substrate 1 is formed.
The poly-Si film 3 and sidewall 4 are approximately 244 nm thick by CVD.
SiO_TwoThe state covered with the film 5 is formed. (After
Experiment B) As shown in Fig. 6 (e), the Si-based
A gate oxide film 10 having a thickness of about 20 nm is formed on the exposed portion of the plate 1.
After that, a poly-Si film 11 for gate electrode with a thickness of about 300 nm is
PBr deposited from above_ThreeImpurity gas diffusion using
P 2 is introduced into the poly-Si film 11.

Next, as shown in FIG. 6 (f), after the gate electrode is formed by patterning the gate electrode poly-Si film 11, a heat treatment is performed at 900 ° C. for 30 minutes to form the source 14 / drain.
Form 15 areas. Finally, openings for the source / drain electrodes are provided in the CVD SiO ₂ film 5, and the source / drain electrodes 12 and 13 made of aluminum are formed respectively. Thus, the MOS FET structure is completed.

Experiment A As shown in FIG. 1 (b), the entire surface including the openings was made of SiO _2.
Is deposited on the bottom of the opening when depositing by CVD
The thickness of the SiO ₂ layer, the thickness of the SiO ₂ layer deposited on the surface of the opening outsiders were compared.

[0028] FIG. 2 is a graph showing the thickness of the relationship between the SiO ₂ layer is deposited on the surface of the thickness and opening outer SiO ₂ layer deposited on the bottom of the opening as measured by the inventors. According to the graph, the thickness of the SiO ₂ layer than the thickness of the SiO ₂ layer deposited on the surface of the opening outer deposited on the bottom of the opening is small, the thickness of the SiO ₂ layer deposited on the surface of the opening outer Above 800 nm, the thickness of the SiO ₂ layer deposited on the bottom of the opening hardly increased,
It shows a constant value at about 550 nm. This is based on the fact that the vapor growth gas is less likely to flow into the opening. Therefore, deposition conditions are possible in which the thickness of the SiO ₂ layer deposited on the surface outside the opening is much larger than the thickness of the SiO ₂ layer deposited on the bottom of the opening.

[0029] As shown in Experiment B Figure 1 (c), when performing anisotropic etching of the SiO ₂ layer, the etching rate for the SiO ₂ layer deposited on the bottom surface of the opening portion is deposited on the surface of the opening outer It was confirmed by the inventor that the etching rate was higher than that for the SiO ₂ layer as shown in FIG. In Fig. 3, the horizontal axis is the thickness (depth) of the SiO ₂ layer deposited on the surface outside the opening, and the vertical axis is the SiO ₂ layer deposited on the bottom of the opening in the same time. Thickness.
In the graph, the solid line is the measured value, and the broken line is the graph when the etching rate is equal inside and outside the opening. It is considered that the ion beam in the anisotropic etching is concentrated in the opening because the CVD SiO ₂ film is deposited on the conductive substrate at the bottom of the opening, and the etching rate is temporarily increased. Therefore, outside the opening
Leaving the CVD SiO ₂ film, CVD SiO ₂ film of the opening bottom there is the condition to be removed.

[0030]

According to the method of the present invention, in the opening, the poly-Si which becomes the base of the bipolar transistor or the source / drain lead electrode of the MOS transistor is formed.
Can be formed stably and the process is not complicated. In addition, since there is no over-etching on the substrate, no crystal defects are introduced.
Further, there is no problem that the connection area between the external base and the internal base becomes discontinuous. As a result, the present invention greatly contributes to the development of high-speed, highly integrated devices.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a graph showing the relationship between the thickness of a CVD SiO ₂ film inside and outside an opening;

FIG. 3 is a graph showing a relationship between an etching amount inside and outside an opening;

FIG. 4 is a diagram showing a first embodiment of the present invention.

FIG. 5 is a diagram (part 1) of a second embodiment of the present invention.

FIG. 6 is a view showing a second embodiment of the present invention (part 2);

FIG. 7 is a diagram of a conventional example.

FIG. 8 illustrates a conventional problem.

FIG. 9 shows a conventional improvement and a problem.

[Explanation of symbols]

1, 51 Si substrate 2, 5, 52, 54 CVD SiO2 film 3, 6, 53, 55, 61 Poly Si layer 4, 56, 63 Poly Si sidewall 5, 57 SiO ₂ sidewall 7, 59 Internal base region 8 Emitter region 9 Base region 10 Gate oxide film 11 Gate electrode 12 Source electrode 13 Drain electrode 14 Source region 15 Drain region 58 Emitter electrode 60 External base region 62 Photoresist

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-183558 (JP, A) JP-A-2-58233 (JP, A) JP-A-60-216580 (JP, A) JP-A-53-183 10982 (JP, A) JP-A-55-118651 (JP, A) JP-A-56-105675 (JP, A) JP-A-58-112367 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H01L 29/73 H01L 29/78

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising: a step of sequentially forming a first insulator layer and a first conductor layer on a semiconductor substrate of a first conductivity type; Removing the first insulator layer to form a first opening reaching the semiconductor substrate; and covering the first opening with a second conductive layer on the first conductive layer. Depositing a body layer and forming a first sidewall made of the second conductive layer on a side wall in the first opening by anisotropic etching; and a semiconductor substrate in the first opening. Depositing a second insulator layer so as to be thinner on the exposed surface of the first layer and to be thicker on the first and second conductor layers outside the first opening ; And the first conductive layer
A second insulator layer is left, and a second insulating layer is formed in the first opening.
Etching the second insulating film so as to form an opening;
The method of manufacturing a semiconductor device characterized by having a that step. 2. The method of manufacturing a semiconductor device, further comprising: forming a second conductive type semiconductor substrate in the first opening on the first conductive type semiconductor substrate.
Forming a base diffusion region by introducing an impurity of a conductivity type; and forming an emitter diffusion region by introducing an impurity of a first conductivity type into the base region in the second opening. The method for manufacturing a semiconductor device according to claim 1, further comprising: 3. The method of manufacturing a semiconductor device, further comprising: introducing a second conductivity type impurity into the first sidewall; and a step of introducing the second conductivity type impurity into the first sidewall. Introducing into the first conductivity type semiconductor substrate below the first sidewall to form source and drain diffusion regions; and the first conductivity type semiconductor substrate in the second opening. Forming a third insulator layer on the surface, and forming a gate electrode covering the second opening.