JPH0629533A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce stress at the part of a gate insulation film by increasing the thickness of an insulation film on a gate electrode side surface and an edge part as compared with the gate insulation film on the gate electrode surface. CONSTITUTION:A silicon oxide film 202 which is 10-500nm is formed on a silicon substrate 201. A polycrystalline silicon film is deposited by 100-400nm and then BF2 ions are implanted, thus forming a high-concentration impurity layer. After patterning, the polycrystalline silicon is etched, thus forming a gate electrode 203 of a thin-film transistor. After a silicon oxide film is deposited on the entire wafer surface by 100nm-1mum, anisotropic etching is performed, thus providing a gate electrode on a side wall 204. Then, a silicon oxide film which becomes a gate oxide film 205 is thermally oxidized for forming 10-100nm silicon oxide film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a thin film transistor formed on a MIS type semiconductor substrate.

[0002]

2. Description of the Related Art In a conventional thin film transistor formed on a MIS type semiconductor substrate, a gate insulating film surrounding a gate electrode is formed on the gate electrode surface and the gate electrode side surface at the same time.

[0003]

However, such an M
In a thin film transistor formed on an IS type semiconductor substrate, a gate insulating film surrounding a gate electrode has a thickness of a gate insulating film on a surface of the gate electrode which is horizontal to the semiconductor substrate and a side surface of the gate electrode which is vertical to the semiconductor substrate. The film thickness of the insulating film was equal or thin.

Therefore, the insulating film on the side surface of the gate electrode or the insulating film on the edge portion of the gate electrode is liable to cause dielectric breakdown, and it is difficult for ions to be implanted in the region located on the side surface of the gate electrode, and the impurity concentration varies. However, there is a problem that the characteristics of the thin film transistor are not stable. An object of the present invention is to solve the above problems and provide a semiconductor device with high yield and high reliability, and a method for manufacturing the same.

[0005]

The present invention comprises at least two or more layers of polycrystalline silicon film or amorphous silicon film, wherein the lower layer polycrystalline silicon is used as a gate electrode and the upper layer polycrystalline silicon is used as a channel, a source, In the thin film transistor serving as the drain, the gate insulating film surrounding the gate electrode has a thickness in the horizontal direction with respect to the semiconductor substrate surface on the gate electrode surface that is greater than the thickness of the insulating film in the vertical direction with respect to the semiconductor substrate surface on the side surface of the gate electrode. The gate insulating film is thick.

Further, a step of forming a first insulating film on the semiconductor substrate, and a step of forming a gate electrode made of a first polycrystalline silicon film or an amorphous silicon film on the first insulating film. A step of forming the gate electrode as a high concentration impurity layer, a step of forming a side wall on a side surface of the gate electrode, and a step of forming a second insulating film on the gate electrode and a side wall of a side surface of the gate electrode. And a step of forming a second polycrystalline silicon film or an amorphous silicon film on the second insulating film, and a step of forming a channel, a source and a drain region by ion implantation.

[0007]

In the semiconductor device and the method for manufacturing the same according to the present invention, the insulating film on the side surface of the gate electrode and the edge portion is thicker than the gate insulating film on the surface of the gate electrode. The electric field applied to the insulating film is lower than the electric field applied to the gate insulating film on the surface of the gate electrode, and the stress applied to the gate insulating film is small.

Since the side surface of the gate electrode has a side wall,
Since the conductive film forming the channel, source, and drain regions formed on the gate electrode does not have a steep step,
Ions injected into the region located on the side surface of the gate electrode are more likely to enter than in the conventional case, and the variation in impurity concentration is reduced.

[0009]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. 2 is a sectional view of a semiconductor device showing an embodiment of the present invention in the order of steps. Here, 101, 201
Is a semiconductor substrate, 102 and 202 are silicon oxide films, 10
3, 203 are gate electrodes, 104, 204 are side walls, 10
5, 205 are gate oxide films, 106, 206 are channel regions of thin film transistors, 107, 207 are source regions of thin film transistors, and 108, 208 are drain regions of thin film transistors.

Now, the process steps will be described with reference to the sectional view of the semiconductor device according to the embodiment of the present invention shown in FIG.

First, a silicon oxide film 202 having a thickness of 10 nm to 500 nm is formed on a silicon substrate 201 by a CVD method or thermal oxidation. (FIG. 2 (a)) Next, a polycrystalline silicon film having a thickness of 100 nm to 400 is formed by a CVD method in a monosilane atmosphere at a temperature of 600 ° C. to 650 ° C.
nm after being deposited, ions of BF ₂ which is a P-type impurity or As (arsenic) and P (phosphorus) which are N-type impurities are deposited on the entire surface.
Ion energy 30KeV～120keV, a dose of 1 × 10 ¹⁴ is implanted in cm ^-2 or more conditions to form a high concentration impurity diffusion layer. Then, after patterning by the photo-etching method, the polycrystalline silicon which is the gate electrode material is etched under a pressure of several mTorr using a mixed gas of Freon 123 and O ₂ and SF ₆ to form a gate electrode. Formed and thin film transistor gate electrode 20
3 is formed. (FIG. 2 (b)) Next, a silicon oxide film is deposited on the entire surface of the wafer by a CVD method to a thickness of 100 nm to 1 μm, and then the reaction gas CHF _{3 is used} to form the silicon oxide film in an anisotropic thickness corresponding to the film thickness of the silicon oxide film. Side wall 204 is provided on the gate electrode by performing a positive etching. (FIG. 2C) Next, the silicon oxide film to be the gate oxide film 205 is thermally oxidized or 10 nm to 100 nm by CVD method.
Forming a silicon oxide film. (FIG. 2 (d)) Next, the polycrystalline silicon film 206 is formed by a CVD method in a monosilane atmosphere at a temperature of 600 ° C. to 650 ° C. to a thickness of 20 nm to 5 nm.
After being deposited to a thickness of 00 nm, ions of BF ₂ which is a P-type impurity or ions of As (arsenic) and P (phosphorus) which are N-type impurities for adjusting the threshold voltage of the thin film transistor are formed on the entire surface to form a channel region of the thin film transistor. To form. (FIG. 2E) Then, the source 207 and drain 208 regions of the thin film transistor are opened by a photolithography method, and ions of BF ₂ which is a P-type impurity or As which is an N-type impurity are formed using the resist 209 as a mask. (Arsenic) and P (phosphorus) ions 210 with an energy of 30 keV to 120 keV,
Dosing is performed under the condition of a dose amount of 1 × 10 ¹⁴ cm ⁻² or more,
A high concentration impurity diffusion layer is formed. (FIG. 2F) Next, after patterning by photolithography, a mixed gas of Freon 123, O ₂ and SF ₆ was used for several mTo.
Under the pressure of rr, etching is performed on the polycrystalline silicon which will be the channel, source and drain of the thin film transistor. (FIG. 2 (g)) In the subsequent steps, an NSG film as an interlayer insulating film of about 100 nm is deposited on the entire surface of the wafer according to a usual method, and contact holes for extracting the source and the drain are formed by photolithography. After that, aluminum or its alloy for electrode wiring is sputtered, and the aluminum wiring is patterned by the photolithography method to form the aluminum wiring.

Then, a silicon oxide film is deposited as a passivation film by the CVD method, the pad is opened by the photo-etching method, the passivation film is removed by a solution containing hydrofluoric acid, and the electrode lead-out port is formed. Form.

In the semiconductor device thus formed, the insulating film on the side surface of the gate electrode and the edge portion is thicker than the gate insulating film on the surface of the gate electrode, and therefore the insulating film on the side surface of the gate electrode and the insulating film on the edge portion is formed. The electric field applied to
It is lower than the electric field applied to the gate insulating film on the surface of the gate electrode.

Therefore, conventionally, it is possible to reduce the stress in the portion of the gate insulating film which is apt to cause dielectric breakdown and prevent the defect of the thin film transistor.

Further, since the side wall is provided on the side surface of the gate electrode and the polycrystalline silicon film forming the channel, source and drain regions formed on the gate electrode does not have a steep step, it is injected into the region located on the side surface of the gate electrode. The generated ions are more likely to enter than in the conventional case, and variations in impurity concentration are reduced.

Therefore, the voltage and current characteristics of the thin film transistor are stable.

Therefore, it is possible to provide a highly reliable semiconductor device having stable characteristics and a manufacturing method thereof.

[0019]

As described above, in the semiconductor device and the manufacturing method thereof according to the present invention, the applied electric field can be reduced and the stress can be reduced by increasing the thickness of the gate insulating film in the region where the defect easily occurs. . As a result, it is possible to provide a high-yield and highly reliable device as a semiconductor device.

Further, by providing the side wall on the side surface of the gate electrode, the conductive film forming the channel, source and drain regions formed on the gate electrode is prevented from having a steep step and is located on the side surface of the gate electrode. Ions implanted into the region are more likely to enter than in the conventional case, and variations in impurity concentration are reduced. This stabilizes the voltage and current characteristics of the thin film transistor.

Therefore, it is possible to reduce the defects of the gate insulating film, stabilize the characteristics of the thin film transistor, and provide a high yield and high reliability device as a semiconductor device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the method for manufacturing the semiconductor device according to the exemplary embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

101,201,301 Semiconductor substrate 102,202,302 Silicon oxide film 103,203,303 Gate electrode 104,204, Side wall 105,205,304 Gate oxide film 106,206,305 Thin film transistor channel region 107,207,306 Thin film transistor Source region 108, 208, 307 of the thin film transistor drain region 209 resist 210 BF ₂ , As (arsenic) or P (phosphorus) ions

Claims (2)

[Claims] 1. A thin film transistor comprising at least two or more layers of polycrystalline silicon film or amorphous silicon film, wherein the lower layer polycrystalline silicon is used as a gate electrode and the upper layer polycrystalline silicon is used as a channel, source and drain. The gate insulating film surrounding the gate insulating film is thicker in the horizontal direction with respect to the semiconductor substrate surface on the gate electrode surface than the film thickness of the insulating film on the side surface of the gate electrode in the vertical direction with respect to the semiconductor substrate surface. Characteristic semiconductor device. 2. A step of forming a first insulating film on a semiconductor substrate, and a step of forming a gate electrode made of a first polycrystalline silicon film or an amorphous silicon film on the first insulating film. A step of forming the gate electrode as a high concentration impurity layer, a step of forming a side wall on a side surface of the gate electrode, and a step of forming a second insulating film on the gate electrode and a side wall of a side surface of the gate electrode. And a step of forming a second polycrystalline silicon film or an amorphous silicon film on the second insulating film, and a step of forming a channel, a source and a drain region by ion implantation. Device manufacturing method.