JPS61100958A - Semiconductor memory integrated circuit device - Google Patents

Abstract

PURPOSE:To increase radiation-resisting strength without particularly enlarging a cell area by forming an insulated gate type capacitor formed by extending a gate insulating film and a gate electrode in an insulated gate type field-effect transistor to a source region or a drain region or onto these regions. CONSTITUTION:In a memory IC containing insulated gate type field-effect transistors 21, 22 with a P-type silicon substrate 11, an N<+> region 20 as a source region or a drain region shaped faced into the substrate and polycrystalline silicon 14 as a gate electrode formed through a gate oxide film 13, the gate oxide film 13 and the polycrystalline silicon 14 extend onto the source region and the drain region, thus forming insulated gate type capacitors 23, 24. When writing is conducted at a node B at a high level, a transistor TA (the transistor 21) is turned ON, a node A is grounded at a low level, and the drain region is also brought to a low level. Accordingly, the capacitors 23, 24 contribute to charge storage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory integrated circuit device comprising an insulated gate field effect transistor.

[Conventional technology]

Semiconductor memory integrated circuit device (hereinafter referred to as memory IC).

) is the person who configures the device! The wiring layer or the case housing the chip contains a trace amount of radioactive elements such as U and Th. It is widely known that the radiation emitted from these elements may destroy the information written in the mesoricell, so countermeasures are being taken, such as increasing the purity of the constituent materials of the device. In addition, in order to increase the strength of radiation particles, it is necessary to improve the chip structure in parallel.
As the density of trap memory ICs increases, structural improvements have become an important theme.

[The problem that the invention attempts to solve]

For example, in an N-channel MO8 static random access memory, the radiation intensity is determined by the node capacitance CA of node A and the node capacitance ii CB K of node B in the cell equivalent circuit shown in FIG.

In other words, if these capacitance values are made large enough,
It is possible to suppress a drop in node potential due to electrons generated in the P-bonded conductor substrate due to radiation, and it is possible to prevent destruction of written information. Node capacity CA
is mainly formed by the junction capacitance of the drain region of transistor TA and the gate capacitance of transistor Tn. These capacitances are also becoming smaller due to the miniaturization of patterns accompanying the increase in the number of bits in memory ICs. Therefore, increasing the node capacitance without expanding the cell area is a problem with respect to radiation.
This is an extremely important issue in line reinforcement measures. Furthermore, the third
In the figure, T A * TB is a driver transistor for the transistor block, TA' and TB' are transfer gate transistors, RA and RB are resistors, D and D are digit lines, W company's word line, and vcc is a power supply.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor memory integrated circuit device that has enhanced radiation resistance without increasing the cell area by a significant amount.

[Means for solving problems]

The semiconductor memory integrated circuit device of the present invention includes a semiconductor substrate of one conductivity type, a source region and a drain region of opposite conductivity types provided in opposition in the semiconductor substrate, and a substrate between the source region and the drain region. In a semiconductor memory integrated circuit device including an insulated gate field effect transistor having a gate electrode provided through a gate insulating film, the gate insulating film and the gate electrode are at least connected to the source region or the drain region or the source region. 2' and an insulated gate search capacitor formed by extending over the drain region 1a.

That is, the insulated gate type capacitor newly provided in the present invention does not exist in conventional static type memory cells. nodes A and B of the circuit
At the same time as the potential of is determined, a charge pk corresponding to the appearance value of the capacitor is accumulated. The radiation intensity increases due to the increase in node capacitance due to the addition of a capacitor.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention.

In this embodiment, the memory cell shown in FIG. 3 has one driver transistor and 121 transfer gate transistors.
This section shows the part of the priest.

In this embodiment, a P mud silicon substrate 11, an N region 20 provided oppositely in the P type silicon substrate 11 and a source region 20 serving as a drain region, and a P type silicon substrate 11 between the source region and the drain region are used. In the memo IJIc which includes an insulating layer t4.uE field effect transistor 21 and 22 having a polycrystalline silicon layer 14 provided on a silicon substrate via a gate oxide film 13, the gate becomes ugly. The film 13 and the polycrystalline silicon 14 serving as the gate electrode extend over the source region and the drain region to form insulating goo (ffl) capacitors 23 and 24.

Here, transistors 21 and 22 constitute transistors TA and T' in FIG. 3, respectively. That is, capacitors 23 and 24 are formed in the source and drain regions of transistor TA, respectively. In addition, in Figure 1, 12
15 is a field oxide film, 15 is a P region, and 18 is an interlayer insulation layer 2.19 AJ wiring layer.

FIG. 2<aJ-((D is a sectional view showing the main steps of an embodiment of the moxibustion method of the present invention.

First, as shown in FIG. 2(al), in the same way as a conventional MO8 integrated circuit board is prepared using a sP"l-silicon substrate 11, an oxide film 12 is formed by the LOCO8 method. Also, gate oxide film 3 and polycrystalline silicon 14 are sequentially formed.P+ region 15 for channel stopper is formed directly under field oxide film 12.As a substrate, P+ region 15 is formed directly under field oxide film 12.
The case where pm silicon is used will be described, but when forming a KP well in an N-type substrate and forming an N-channel transistor in the well, the same back method as in the non-embodiment can be applied. The polycrystalline silicon 14 is doped with phosphorus and has sufficient conductivity to not interfere with circuit operation.

Next, as shown in FIG. 2(b), a PSG layer 16 is selectively deposited on the polycrystalline silicon 14 at the portion that will become the gate electrode of the MO8 transistor in the future. The thickness of the PSG film 16 is set to a thickness sufficient to provide masking properties when ion implantation is performed to form source/drain regions in the future. Furthermore, a photoresist 17 is deposited thereon to form a pattern on the portion of the polycrystalline silicon 14 that will form a capacitor in the future.

Next, as shown in FIG. 1C, the polycrystalline silicon 14 on the semiconductor substrate shown in FIG. The remaining polycrystalline silicon 14 is formed.These will act as gates T& in the future.If necessary, a polycrystalline silicon wiring layer can be formed although not shown in this drawing.Polycrystalline silicon 14 After selective etching is completed, the photoresist 17 is removed, and the PSGkt6 is used as a mask to perform high-strength N21 impurity doping for forming source/drain regions by ion implantation to form the N region 20. In this case, polycrystalline silicon is used. It is necessary to set the implantation energy so that the impurity reaches && in the portion where only the PSG film 16 and the polycrystalline silicon 1402 layer are formed by masking the portion 14 so that the impurity does not reach the substrate surface. The depth of the N region 200 from the substrate surface is shallower in the region where impurities are introduced through the polycrystalline silicon 14, as shown in FIG. Activation of impurities is performed by high temperature heat treatment as necessary.

Next, as shown in FIG. 2 (dl K), the PSG film 16 is
, it can be removed by etching in a short time using an acid-based etching solution. After that, a post-static insulating film 18 is deposited and a contact hole is formed, and then an A4 wiring r@19 is provided to obtain the embodiment shown in FIG.

Now, in the circuit shown in Figure 3, if node B is filled, if node B is written to a high level, trough 9 and 21 people (
The transistor 21) is turned on, the node A is grounded at a low level, and the drain region is also at a low level.

Therefore, capacitors 23 and 24 contribute to charge storage as node capacitance CB of node B. Conversely, when node A is at high level, node B is at low level, so
The gate electrode of the capacitor 24 is at a low level, and the capacitor 24 contributes as a node capacitance CA.

Capacitors corresponding to capacitors 23 and 24 are similarly formed on the source and drain 2 regions of transistor TB (not shown), and the contribution of charge storage as node capacitance is the same as capacitors 23 and 2.
This is the same as in case 4.

By increasing the node capacitance by providing a capacitor in this way, even if electrons due to radiation flow into the junction of high-level nodes, an amount of positive charge will be accumulated that will not cause the node level to be reversed. things become possible.

In this embodiment, the capacitors 23 and 24 can be provided on the region of the driver transistor 21 that was simply the source or drain in the conventional device, and there is no need to particularly increase the cell area. Of course, if necessary, a special area for the capacitor may be provided.

In addition, in this example □, polycrystalline silicon 1 is used as the gate electrode.
4 was used, but in addition to that, Tim1d and Tacit.

It is also possible to use silicide of a high melting point metal such as WSi2 or the high melting point metal itself.

〔Effect of the invention〕

As described in detail above, in the semiconductor memory integrated circuit device of the present invention, the gate insulating film and the gate electrode of the insulated gate field effect transistor constituting the device extend over the source region or the drain region or the source region and the drain region. The node capacitance of the cell increases because it contains an insulated gate capacitor formed by
Even if electrons due to radiation flow into the node junction, it is possible to prevent the level of the node from reversing. Moreover, the formation of this capacitor does not necessarily require a chip area, and can be formed using a conventional chip area.

Therefore, according to the present invention, it is possible to obtain a semiconductor memory integrated circuit device with enhanced radiation resistance without particularly increasing the cell area.

[Brief explanation of drawings]

Figure 1 is a sectional view showing one embodiment of the present invention, Figure 2 (a)
-(d) are cross-sectional views of main steps of one embodiment showing a manufacturing method of one embodiment of the present invention, and FIG. 3 is a memory cell of a semiconductor memory integrated circuit device for explaining the prior art and the present invention in detail. FIG. 11...P-type silicon substrate, 12...
Field oxide film, 13... Gate oxide film, 1
4...Polycrystalline silicon = ry, tsP region, 16
---------- P fi cTg, 17...
Photoresist, 18-... Interlayer insulating film, 19.
...A! Wiring layer, 20...N region, 2
1.22...Transistor, 23.24...
... Capacitor, A, B ... Node, D, D
... Digit line, CA, CB ... Storage capacitance, RA, RB ... Resistance, TA. TB... Ant, Pflop driver transistor, TA' + TB'... Transfer gate transistor, vcc... Power supply. $2 Figure $3 Figure

Claims (1)

[Claims] A semiconductor substrate having one conductivity type, a source region and a drain region of opposite conductivity type provided oppositely in the semiconductor substrate, and a gate insulating film provided on the substrate between the source region and the drain region. In a semiconductor memory integrated circuit device including an insulated gate field effect transistor having a gate electrode, the gate insulating film and the gate electrode extend at least over the source region or the drain region or the source region and the drain region. A semiconductor memory integrated circuit device comprising an insulated gate capacitor formed therein.