JPS6425558A - Semiconductor memory device and manufacture thereof - Google Patents

Semiconductor memory device and manufacture thereof

Info

Publication number
JPS6425558A
JPS6425558A JP62181100A JP18110087A JPS6425558A JP S6425558 A JPS6425558 A JP S6425558A JP 62181100 A JP62181100 A JP 62181100A JP 18110087 A JP18110087 A JP 18110087A JP S6425558 A JPS6425558 A JP S6425558A
Authority
JP
Japan
Prior art keywords
region
regions
semiconductor
drain
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62181100A
Other languages
Japanese (ja)
Other versions
JP2574801B2 (en
Inventor
Shuji Ikeda
Satoshi Meguro
Norio Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62181100A priority Critical patent/JP2574801B2/en
Publication of JPS6425558A publication Critical patent/JPS6425558A/en
Application granted granted Critical
Publication of JP2574801B2 publication Critical patent/JP2574801B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B10/00Static random access memory [SRAM] devices

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To increase the amount of charge accumulation and to prevent soft errors, by constituting a semiconductor region, which is in contact with a drain region and has high impurity concentration having a reverse conductivity type with respect to the drain region, at the lower part of the drain region and a channel forming region of a MISFET, which is an accumulating node of the amount of the charge accumulation that becomes information. CONSTITUTION:One end part of a gate electrode of each driving MISFET Q is directly connected to semiconductor regions 9 and 11 through connecting holes 6A, which are provided in a gate insulating film 6. The semiconductor regions 9 are provided so as to include or wrap the high impurity concentration regions 11, which are used as the drain regions of the driving MISFETs Q. The junction depth is constituted deeply. Thus the turning of the semiconductor region 9 into the lower part of the gate electrode 7 of each driving MISFET Q (to the side of a channel forming region) becomes large. The capacitance of the gate is increased by increasing the area, where the semiconductor regions 9 (drain regions) and the gate electrodes 7 are overlapped. The charge accumulating amount of a capacitor C can be increased. Therefore, when minority carries, to be generated by alpha rays in a well region 2, intrude into the capacitor element C for accumulating the charge, the inversion of information can be made hard to occur.
JP62181100A 1987-07-22 1987-07-22 Semiconductor memory device and method of manufacturing the same Expired - Fee Related JP2574801B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181100A JP2574801B2 (en) 1987-07-22 1987-07-22 Semiconductor memory device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181100A JP2574801B2 (en) 1987-07-22 1987-07-22 Semiconductor memory device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPS6425558A true JPS6425558A (en) 1989-01-27
JP2574801B2 JP2574801B2 (en) 1997-01-22

Family

ID=16094838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181100A Expired - Fee Related JP2574801B2 (en) 1987-07-22 1987-07-22 Semiconductor memory device and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2574801B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0453961A2 (en) * 1990-04-20 1991-10-30 Kabushiki Kaisha Toshiba SRAM using E/R memory cells that help decrease the software error rate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224663A (en) * 1985-07-24 1987-02-02 Hitachi Vlsi Eng Corp Semiconductor memory device
JPS62249474A (en) * 1986-04-23 1987-10-30 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224663A (en) * 1985-07-24 1987-02-02 Hitachi Vlsi Eng Corp Semiconductor memory device
JPS62249474A (en) * 1986-04-23 1987-10-30 Hitachi Ltd Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0453961A2 (en) * 1990-04-20 1991-10-30 Kabushiki Kaisha Toshiba SRAM using E/R memory cells that help decrease the software error rate

Also Published As

Publication number Publication date
JP2574801B2 (en) 1997-01-22

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees