JPS647661A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS647661A
JPS647661A JP16125987A JP16125987A JPS647661A JP S647661 A JPS647661 A JP S647661A JP 16125987 A JP16125987 A JP 16125987A JP 16125987 A JP16125987 A JP 16125987A JP S647661 A JPS647661 A JP S647661A
Authority
JP
Japan
Prior art keywords
gate electrode
layer polysilicon
layer
polysilicon
anisotropic etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16125987A
Other languages
Japanese (ja)
Inventor
Masayuki Minowa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16125987A priority Critical patent/JPS647661A/en
Publication of JPS647661A publication Critical patent/JPS647661A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a semiconductor device with a MOS type transistor, characteristics of which are not deteriorated by applying high voltage and working speed of which can be increased, by disposing upper-layer polysilicon formed through anisotropic etching on a side face on at least the drain side of a gate electrode and holding the potential of the upper-layer polysilicon at the same value as the gate electrode. CONSTITUTION:In a MOS type transistor composed of a gate electrode 3 organized of polysilicon and source-drain regions constructed in LDD structure by each impurity layer 5, 7 in low concentration and high concentration, upper- layer polysilicon 6 shaped through anisotropic etching is arranged on a side face on at least the drain side of the gate electrode 3, and the potential of the upper-layer polysilicon 6 is held at the same value as the gate electrode 3. The gate electrode 3 is formed, an oxide film 4 is shaped onto the surface of the gate electrode 3, and the low-concentration impurity layer 5 is formed. Upper-layer polysilicon 6 is shaped, the upper-layer polysilicon 6 is left only on the sidewall of the gate electrode 3 through anisotropic etching, and the high-concentration impurity 7 is formed. The gate electrode 3 and the upper- layer polysilicon 6 are connected electrically by an Al electrode.
JP16125987A 1987-06-30 1987-06-30 Semiconductor device Pending JPS647661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16125987A JPS647661A (en) 1987-06-30 1987-06-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16125987A JPS647661A (en) 1987-06-30 1987-06-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS647661A true JPS647661A (en) 1989-01-11

Family

ID=15731695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16125987A Pending JPS647661A (en) 1987-06-30 1987-06-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS647661A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0348428A (en) * 1989-04-21 1991-03-01 Matsushita Electron Corp Semiconductor device
JPH04115538A (en) * 1990-09-05 1992-04-16 Mitsubishi Electric Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0348428A (en) * 1989-04-21 1991-03-01 Matsushita Electron Corp Semiconductor device
JPH04115538A (en) * 1990-09-05 1992-04-16 Mitsubishi Electric Corp Semiconductor device

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