JPH04133436A - Mos type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture the title MOS type semiconductor device having the characteristics meeting the requirements of restraining the short channel effect while enhancing the resistance to deterioration in hot electrons in the miniaturization step by a method wherein the first conductivity type high concentration layers are formed on the positions beneath the second conductivity type second source/drain layers formed to be overlapped with a gate electrode. CONSTITUTION:The title MOS type semiconductor device is provided with the first conductivity type semiconductor substrate 1, a gate insulating film selectively formed on the semiconductor substrate 1, a gate electrode 7 formed on the gate insulating film 6, the second conductivity type first source/drain layer 4 formed in the semiconductor substrate 1 excluding said substrate 1 beneath the gate electrode 7, the second source/drain layers 5 shallower than the first source/drain layer 4 and formed in the part of the semiconductor substrate 1 beneath the gate electrode 7, the first conductivity type high concentration layers 2 deeper than the second source/drain layers 5 and having the maximum concentration value on the shallower position than the bottom part of the first source/drain layer 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention aims to suppress deterioration of device characteristics caused by short channel effects and hot electrons as the iLMOS type semiconductor device is miniaturized by independent device structural elements. High-density MO for reliability
The present invention relates to an S-type semiconductor device and a method for manufacturing the same.

Conventional Technology Ultra-integrated circuit devices In so-called VLSI, MOS integrated circuit devices have become increasingly important due to the demand for low power consumption and high integration. However, with miniaturization, subthreshold characteristics deteriorate and The deterioration of hot electron-induced device characteristics caused by the so-called short channel effect and the high electric field near the drain is becoming a serious problem with miniaturization.

Therefore, various structures and manufacturing processes have been proposed to solve this problem, and will be explained below from two points: (I) suppression of short channel effect and (II) suppression of hot electron degradation.

For example, IEE 1982 IEDM (IEEE, 1982 IEDM)
) Technical Digest p, 718
FIG. 3 shows the structure proposed by S., Ogura et al.

In the figure, 31 is a low concentration substrate (p type), 32 is a high concentration p type impurity @ 33 is a p type impurity for threshold voltage control, 34 is a high concentration source/drain lj 35
is a low concentration source/drain! , 36 is gate insulation I
ll, 37 is a gate electrode, and 38 is an aluminum wiring, but this structure is maintained (Yo) Using the gate electrode 37 as a mask, double ion implantation is performed in a self-aligned manner to form a low concentration source/drain layer 35 and a high concentration p-type impurity layer 32. A highly doped source/drain layer 34 is formed in a self-aligned manner using the gate electrode 37 and sidewall oxide film 38 as a mask.

This low-concentration source/drain layer 35 alleviates the high electric field near the drain and improves hot electron degradation resistance, and the +'w high-concentration p-type impurity layer 32 suppresses potential growth from the drain layer source/drain. This suppresses the short channel effect without increasing the parasitic capacitance between the substrate and the substrate.

Also 1988 VLSI Symposium Technic
C, S, O in al Digest p, 73-74
The structure proposed by H. et al. is shown in FIGS. 4(a) to 4(C).

In the figure, 41 is a low concentration substrate (p type), 42 beams, a shallow region with a depth of l-0, 15 um, and a shallow region with a depth of l-0, 15 um.
A source consisting of a deep region with a depth of 0.2 um/
The drain electrode 43 is the gate insulating film 44, and the gate electrode 4
5, the L-shaped sidewall oxide film 46 is sidewall nitrided! Even if 47 becomes a p-type impurity layer for threshold voltage control, in this structure (the sidewall nitride film 46 forms an L-shaped sidewall oxide film 4).
After that, using the resistive gate electrode 44 from which the sidewall nitride film 46 was removed and the L-shaped sidewall oxide film button 45 as a mask, ion implantation was performed at -degrees to 0°1.
A shallow region with a depth of -0.15 um and a 0.15-0.
A source/drain layer 42 consisting of a deep region having a depth of 2u and rn is formed (FIG. 2(C)), and the shallow source/drain layer portion contributes to suppressing the short channel effect.

As mentioned above, two major proposals have been made.

However, these structures are still not sufficient to solve the problem that the invention aims to solve (1
o The structure shown in Figure 3 has the following serious problems. The high concentration p-type impurity layer 32 and the low concentration source/drain layer 35 are formed in a self-aligned manner using the gate electrode 37 as a mask. Source/drain layer 35
It has a structure that surrounds it. This number is effective in suppressing the short channel effect. A high concentration p-type impurity layer is also formed on the side surface of the low concentration source/drain layer 35. This number strengthens the electric field near the drain and makes it resistant to hot electron degradation. However, the structure shown in FIG. 4(c) has the following problems. -0
, 15 um, and a source/drain layer 42 having a shallow region.

The effect of suppressing the short channel effect can be expected to some extent (it is not possible to expect much improvement in resistance to hot electron degradation).The reason (1) The concentration value of the impurity layer in the shallow region of the source/drain layer 42 is 1.0E19
/am' and does not significantly improve hot electron degradation resistance (~ (2) Gate electrode 44 and L-shaped sidewall oxide film pattern 4
Since the source/drain layer 42 is formed using the gate electrode 44 as a mask, only a slight overlap between the gate electrode 44 and the source/drain layer 42 is formed, which greatly improves hot electron degradation resistance.

(3) There is no high-concentration layer of the same conductivity type as the substrate other than the p-type impurity layer 47 for threshold voltage control. As the device becomes finer, the short channel effect becomes more noticeable.

In other words, the conventional structure does not exhibit characteristics that satisfy both short channel effect suppression and improvement of hot electron degradation resistance during miniaturization.
The present invention has been made in view of the problems of the conventional structure, and is a MOS type semiconductor device with a new structure and a manufacturing method thereof using a completely new process. A semiconductor substrate of a first conductivity type, a gate insulating film selectively formed on this semiconductor substrate, a gate electrode formed on this gate insulating film, and a semiconductor substrate of a first conductivity type directly below this gate electrode. A first source/drain layer of a second conductivity type formed in the outer semiconductor substrate, and a second source/drain layer formed shallower than the first source/drain layer and extending to a part of the semiconductor substrate directly under the gate electrode. a second source/drain layer, and a first source/drain layer that is deeper than the second source/drain layer, immediately below the second source/drain layer and on a side of the first source/drain layer. This is a MOS type semiconductor device including a first conductivity type high concentration layer having a maximum concentration value at a position shallower than the lower portion.

The present invention also provides a method for manufacturing the above-mentioned MOS type semiconductor device by the following method. Namely, the present invention provides a method for manufacturing a MOS type semiconductor device by forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and then using the gate electrode as a mask. a step of forming a second source/drain layer of a second conductivity type; a step of depositing a first insulating film over the entire surface of the semiconductor substrate; and a step of depositing a second insulating film over the entire surface of the first insulating film. After dry etching the second insulating film to form a second insulating film pattern in a self-aligned manner so as to cover the side surface of the first insulating film, the gate electrode and the side surface of the gate electrode are etched. forming a first source/drain layer using the first insulating film and the second insulating film pattern as masks;
After removing the second insulating film pattern by etching, a step of introducing impurities of a first conductivity type using the gate electrode and the first insulating film covering the side surfaces of the gate electrode as a mask to form a highly concentrated layer is performed. Alternatively, a gate electrode is formed on a semiconductor substrate of a first conductivity type via a gate insulating film, and then a second source/drain of a second conductivity type is formed using the gate electrode as a mask. A step of forming a layer and depositing an insulating film over the entire surface of the semiconductor substrate. Using the gate electrode and the insulating film covering the side surfaces of the gate electrode as a mask, impurities of a first conductivity type are introduced to form a highly concentrated layer. re-depositing and fitting an insulating film over the entire surface of the semiconductor substrate; dry etching the insulating film to form an insulating film pattern in a self-aligned manner so as to cover the side surfaces of the gate electrode; A MOS comprising a step of forming a first source/drain layer using an insulating film pattern covering the side surface of the gate electrode as a mask.
A method for manufacturing a type semiconductor device is used.

Operation of the MOS type semiconductor device of the present invention (i.e., a first source/drain layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and a second source/drain layer of a second conductivity type is formed so as to overlap a gate electrode.
In a source/drain structure in which a source/drain layer is formed outside the first source/drain layer and deeper than the first source/drain layer, a highly doped layer of the first conductivity type is formed between the first source/drain layer and the first source/drain layer. A low concentration impurity layer of the first conductivity type for threshold voltage control is formed on the side of the second layer/drain layer at a position directly below the second source/drain layer. This number can also be
The high concentration layer of the first conductivity type for suppressing the short channel effect suppresses the short channel effect and facilitates miniaturization without causing a decrease in hot electron degradation resistance. This makes it possible to achieve higher density. In other words, a shallow source/drain layer with a low concentration is formed using the gate electrode as a mask, a highly concentrated impurity layer of the same conductivity type as the substrate is formed using the gate electrode and the first insulating layer as a mask, and a layer with a high concentration of impurities of the same conductivity type as the substrate is formed with the gate electrode and the first insulating layer. Using the second insulating layer as a mask, it is possible to define a highly concentrated impurity layer of the same conductivity type as the Atsushi substrate on which a highly concentrated and deep source/drain layer is formed without causing a high electric field near the drain. EXAMPLES Below, examples of the present invention will be explained based on FIGS. 1 and 2. In FIG. 1, 1 is a low concentration substrate (p type), 2 is a high concentration p type impurity layer, and 3 is a threshold. P-type impurity for value voltage control #
4 is a high concentration source/drain layer 5 is a low concentration and shallow source/drain layer 6 is a gate insulation layer 7 is a gate electrode 8
is an aluminum wiring. What is distinctive about this figure is that the high concentration p-type impurity layer 2 is formed only directly under the low concentration and shallow source/drain layer 5; A p-type impurity layer 3 for threshold voltage control is formed on the side.

In this case, a high electric field is not generated at the side edges of the low-concentration, shallow source/drain layer 5, and the resistance to hot electron degradation can be significantly improved. It is possible to significantly suppress the short channel effect without reducing the resistance to hot electron degradation.In other words, with this structure, the resistance to hot electron degradation can be improved while suppressing the short channel effect. It is possible to suppress it significantly.

Next, the main points of an example of the manufacturing method will be explained using FIGS. 2(a) to 2(d).

First, as shown in FIG. 2(a), a low concentration substrate (p-type) has a p-type impurity layer 3 for threshold voltage control on its surface.
1, a gate insulating film 6 and a gate electrode 7 are selectively formed. Thereafter, using the gate electrode 7 as a mask, arsenic ions are implanted at an acceleration voltage of 40 KeV and a dose of 4.0E13/cm2 to form the source/drain layer 5. At this time, the source/drain layer 5 can be formed shallowly with a low concentration.
completely overlap.

Next (to) As shown in Figure 2 (b), CVD is applied to the entire surface of the substrate.
An oxide film 9a and a nitride film 10a are deposited by a method.

Here, the oxide film thickness is 50nm, and the nitride film thickness is 250nm.
Set to about m.

Thereafter, as shown in FIG. 2C, dry etching is performed to form a nitride film pattern 10b in a self-aligned manner so as to cover the side surface of the oxide film 9b. At this time, the oxide film 9b on the substrate is reduced to about 30 nm. After that, using the gate electrode 7 and the oxide film 9a covering the side surfaces of the gate electrode 7 and the nitride film pattern 10b as masks, arsenic is heated at an acceleration voltage of 80 KeV and at a dose. Source/drain layers 4 are formed by ion implantation at a dose of 6', 0E15/cm2. At this time, the source/drain layer 4 can be formed deep with a high concentration, and the ions are implanted from a distance of 0.3 um from the end of the gate electrode.
does not cover the shallow source/drain layer 5 with low concentration (
Next, as shown in FIG. 2(d), two nitride film patterns 10 are formed.
After treating b with hydrofluoric acid HF for about 200 seconds, it was removed by etching with hot phosphoric acid H, PO. At this time, the oxide film 9C on the substrate is reduced to about 10 nm.4 After this step,
Using the gate electrode 7 and the oxide film pattern 9C covering the side surfaces of the gate electrode 7 as a mask, boron was heated at an acceleration voltage of 80 KeV.
Although the highly concentrated p-type impurity layer 2 can be formed by ion implantation at a dose of 3゜2E12/am2, the gate electrode 7
The high concentration p-type impurity layer 2 does not cover the side surfaces of the low concentration and shallow source/drain layer 5 due to the oxide film pattern 9C covering the side surfaces of the MO.
In this embodiment, a gate electrode 7 is formed on a semiconductor substrate of a first conductive type via a gate insulating film 6, and then a second conductive semiconductor is formed using the gate electrode 7 as a mask. a step of forming a second source/drain layer 5 of a type, a step of depositing a first insulating film 9a on the entire surface of the semiconductor substrate, and a step of depositing a second insulating film 10a on the entire surface of the first insulating film 9a. After forming a second insulating film pattern 10b in a self-aligned manner so as to cover the side surface of the first insulating film 9a by dry etching the second insulating film 10a, the gate electrode 7 and the second insulating film pattern 10b are formed in a self-aligned manner. After forming the first source/drain layer 4 using the first insulating film and the second insulating film pattern covering the side surfaces of the gate electrode as masks, and etching away the second insulating film pattern 10b, a first insulating film 9c covering the side surfaces of the gate electrode 7 and the goo 1 electrode;
A method for manufacturing a MOS type semiconductor device comprising a step of introducing impurities of a first conductivity type to form a highly concentrated layer 2 using a mask as a mask (a method of manufacturing a MOS type semiconductor device comprising a step of forming a highly concentrated layer 2 on a semiconductor substrate of a first conductivity type through a gate insulating film). After forming a gate electrode, a step of forming a second source/drain layer of a second conductivity type using the gate electrode as a mask, and depositing an insulating film on the entire surface of the semiconductor substrate to form a second source/drain layer between the gate electrode and the second conductivity type. A step of introducing an impurity of the first conductivity type using the insulating film covering the side surface of the gate electrode as a mask to form a highly concentrated layer, and dry etching of the insulating film without depositing the insulating film again on the entire surface of the semiconductor substrate. After forming an insulating film pattern in a self-aligned manner so as to cover the side surface of the gate electrode, a first source/drain layer is formed using the gate electrode and the insulating film pattern covering the side surface of the gate electrode as a mask. Effects of the Invention As is clear from the above explanation, the MOS type semiconductor device having the structure of the present invention can be used to produce a highly concentrated impurity layer of the same conductivity type as the substrate. can be formed directly under the shallow, low-concentration source/drain layer, and generates a high electric field on the side surface of the shallow, low-concentration source/drain layer due to the highly concentrated impurity layer of the same conductivity type as the substrate. The concentration value of the highly concentrated impurity layer of the same conductivity type as the substrate can be made sufficiently high without reducing the conductivity, and the short channel effect can be significantly suppressed, making it possible to easily miniaturize MOS.
In other words, the manufacturing method of the present invention makes it possible to obtain extremely reliable and high-density semiconductor devices.
A high concentration impurity layer of the same conductivity type as the substrate is formed using the drain layer as a mask, a high concentration impurity layer of the same conductivity type as the substrate is formed using the gate electrode and the first insulating layer as a mask, and a high concentration deep source layer is formed using the gate electrode, the first insulating layer and the second insulating layer as masks. / A highly concentrated impurity layer of the same conductivity type as the substrate in which the drain layer is formed can be determined without causing a high electric field in the vicinity of the drain.

Therefore, the MOS type semiconductor device of the present invention has high resistance to hot electron degradation required for the VLSI, and is essential for high integration technology that significantly suppresses short channel effects, and its industrial value is high. Very dog-like l,%

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the structure of a MOS semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of the manufacturing process of the device. FIG. 3 is a cross-sectional view of the structure of a conventional MOS semiconductor device. FIG. 2 is a structural cross-sectional view and a schematic cross-sectional view of the manufacturing process of another conventional MOS type semiconductor device. 1...Low concentration substrate (p-type) 2...High concentration p-type impurity Jt3...P-type impurity for threshold voltage control
4... High concentration source/drain layer 5... Low concentration and shallow source/drain layer 6... Gate insulation A 7.
...Getoden Kaede 8...Name of aluminum vibration-resistant agent Patent attorney Akira Okaji Haga 2 persons Figure 1, Figure 2, Figure 7, Kate IR Arrogance! 2 P-type impurity layer Fig. 37 Ketodeni Fig. (α)

Claims (5)

[Claims] (1) A semiconductor substrate of a first conductivity type, a gate insulating film selectively formed on this semiconductor substrate, a gate electrode formed on this gate insulating film, and a first conductivity type semiconductor substrate directly below this gate electrode. a first source/drain layer of a second conductivity type formed in the semiconductor substrate outside the semiconductor substrate; and a part of the semiconductor substrate that is shallower than the first source/drain layer and directly below the gate electrode. a second source/drain layer formed therein; A MOS type semiconductor device comprising a first conductivity type high concentration layer having a maximum concentration value at a position shallower than a lower part of a source/drain layer. (2) The MOS semiconductor device according to claim 1, wherein L-shaped insulating film layers are formed on both sides of the gate electrode. (3) The MOS semiconductor device according to claim 1, further comprising an impurity layer of the second conductivity type that decreases monotonically from the end of the first source/drain layer to the end of the gate electrode. (4) forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and then forming a second source/drain layer of a second conductivity type using the gate electrode as a mask; a step of depositing a first insulating film over the entire surface of the semiconductor substrate; a step of depositing a second insulating film over the entire surface of the first insulating film; and dry etching the second insulating film to remove the first insulating film. After forming a second insulating film pattern in a self-aligned manner so as to cover the side surface of the insulating film, a second insulating film pattern is formed using the gate electrode and the first insulating film and second insulating film pattern covering the side surface of the gate electrode as masks. After removing the second insulating film pattern by etching, a first conductivity type impurity is added using the gate electrode and the first insulating film covering the side surfaces of the gate electrode as a mask. 1. A method for manufacturing a MOS type semiconductor device, comprising a step of introducing a high concentration layer to form a high concentration layer. (5) forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and then forming a second source/drain layer of a second conductivity type using the gate electrode as a mask; depositing an insulating film over the entire surface of the semiconductor substrate, and using the gate electrode and the insulating film covering the side surfaces of the gate electrode as a mask, introducing impurities of a first conductivity type to form a highly concentrated layer; An insulating film is again deposited on the insulating film, and this insulating film is dry-etched to form an insulating film pattern in a self-aligned manner so as to cover the side surfaces of the gate electrode. A method for manufacturing a MOS type semiconductor device, comprising a step of forming a first source/drain layer using a film pattern as a mask.