WO2010029681A1

WO2010029681A1 - Semiconductor device and method for manufacturing the same

Info

Publication number: WO2010029681A1
Application number: PCT/JP2009/003473
Authority: WO
Inventors: 山下恭司; 生駒大策; 亀井政幸
Original assignee: パナソニック株式会社
Priority date: 2008-09-10
Filing date: 2009-07-23
Publication date: 2010-03-18

Abstract

Provided is a semiconductor device, wherein a gate insulating film (5) is formed on a first conductivity type semiconductor region (1a), a gate electrode (6) is formed on the gate insulating film (5), and on a side surface of the gate electrode (6), a first offset spacer (7a), a second offset spacer (7b) and a side wall (10) are sequentially formed. Furthermore, a second conductivity type extension region (8) is formed below a side of the gate electrode (6) in the semiconductor region (1a), and a first conductivity type pocket region (9) is formed below the side of the gate electrode (6) below the extension region (8) in the semiconductor region (1a).

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device including a first offset spacer formed on a side surface of a gate electrode, and a second offset spacer formed on a side surface of the gate electrode via the first offset spacer, and the semiconductor device It relates to a manufacturing method.

As a result of reducing the gate length and the gate width with the miniaturization of the semiconductor device, there is a risk that random variations of the transistors may increase. If random variations of transistors increase, it becomes difficult to stably operate a semiconductor device such as SRAM (Static Random Access Memory). Therefore, it is desired to develop a semiconductor device structure and a manufacturing method thereof that can reduce random variations of transistors. It is rare. Here, “transistor random variation” means that the characteristics of two transistors provided in close proximity vary completely at random. As a main cause of random variations of transistors, a phenomenon in which the number of impurity atoms present in the channel region varies statistically or a phenomenon in which the spatial positions of atoms vary statistically is cited. Other causes include, for example, variations in gate length, gate insulating film thickness, or gate width in two adjacent transistors. In addition, if the short channel effect is not sufficiently suppressed, the random variation increases due to the variation in the gate length. Therefore, it is important to sufficiently suppress the short channel effect in order to suppress an increase in the random variation of the transistor. It is.

σVT = A · Teff · Na ^1/4 · Leff ⁻¹ / ² · Weff ^−1/2 : (Formula 1)
In Equation 1, A is a proportionality coefficient, Teff is the electrical effective film thickness of the gate insulating film, Na is the channel impurity concentration, Leff is the electrical effective gate length, and Weff is This is the electrical effective gate width. As shown in Equation 1, when the dimensions of Leff and Weff are small, or when Teff is thick and Na is high, σVT increases and the random variation of the transistors increases.

Here, as a conventional semiconductor device for suppressing the short channel effect, there is an NMOS (Negative ChannelhanMetal Oxide Semiconductor) transistor having a single layer offset spacer functioning as a mask when forming an extension region and a pocket region. (For example, refer to Patent Document 1). This offset spacer is a technique adopted from around 90 nm process technology or 65 nm process technology. FIG. 5 is a cross-sectional view of a conventional semiconductor device.

As shown in FIG. 5, the conventional semiconductor device includes a semiconductor substrate 101 made of P-type silicon, an element isolation region 102 formed in the semiconductor substrate 101, and an NMOS transistor region in the semiconductor substrate 101 from the element isolation region 102. A deeply formed P-type well 103, an active region 101a composed of a semiconductor substrate 101 surrounded by an element isolation region 102, a P-type impurity region 104 formed in an upper region of the active region 101a and serving as a channel region, and an active region A gate insulating film 105 formed on the region 101a, an N-type gate electrode 106 formed on the gate insulating film 105 and made of polycrystalline silicon containing an N-type impurity such as P, and side surfaces of the N-type gate electrode 106 An offset spacer 107 formed thereon and having a thickness of 3 nm, and an N type in the active region 101a N-type extension region 108 formed laterally below the gate electrode 106 and a P-type pocket region 109 formed below the N-type extension region 108 of the active region 101a laterally below the N-type gate electrode 106. A sidewall 110 formed on the side surface of the N-type gate electrode 106 with an offset spacer 107 interposed therebetween, and an N-type source / drain region 111 formed on the outer side of the sidewall 110 in the active region 101a. ing.

In the conventional semiconductor device having the above configuration, the thickness of the offset spacer 107 is optimized from the viewpoint of suppressing the short channel effect and realizing a high driving force. That is, from the viewpoint of suppressing the short channel effect, the distance between the N-type extension regions 108 formed on both sides of the N-type gate electrode 106 may be increased to some extent according to the junction depth of the N-type extension region 108. Preferably, from the viewpoint of realizing a high driving force, it is preferable that the N-type gate electrode 106 and the N-type extension region 108 overlap each other to some extent. Optimization of the film thickness of the offset spacer 107 is performed by a procedure such as confirmation with an actual prototype wafer after narrowing down conditions using TCAD (Technology computer-aided design).

Subsequently, a conventional method for manufacturing a semiconductor device will be described. 6A to 6G are cross-sectional views showing the method of manufacturing the semiconductor device of this embodiment in the order of steps.

As shown in FIG. 6A, first, an element isolation region 102 made of a silicon oxide film is formed on a semiconductor substrate 101 made of P-type silicon. Next, a P-type well 103 and a P-type impurity region 104 are formed by implanting a P-type impurity such as B into the portion of the semiconductor substrate 101 that becomes the NMOS transistor region. The P-type well 103 is formed deeper than the element isolation region 102 in the NMOS transistor region of the semiconductor substrate 101, and a region of the NMOS transistor region surrounded by the element isolation region 102 functions as the active region 101a. . The P-type impurity region 104 is formed in the upper region of the active region 101a and functions as a channel region of the NMOS transistor.

Next, for example, a silicon oxide film (not shown) is formed on the upper surface of the semiconductor substrate 101. Thereafter, a polycrystalline silicon film (not shown) is deposited on the silicon oxide film by a CVD (Chemical Vapor Deposition) method or the like. Thereafter, an N-type impurity such as P is selectively implanted into the NMOS transistor region, thereby doping the polycrystalline silicon film with the N-type impurity.

Next, the polycrystalline silicon film doped with the N-type impurity and the silicon oxide film are selectively removed by dry etching to form a gate insulating film 105 on the active region 101a and on the gate insulating film 105. Then, an N-type gate electrode 106 made of a polycrystalline silicon film is formed.

Next, as shown in FIG. 6B, an offset spacer 107A made of a silicon oxide film or the like and having a thickness of 3 nm is formed on the upper surface of the semiconductor substrate 101. Next, as shown in FIG. Thereby, the offset spacer 107 </ b> A is formed on the semiconductor substrate 101 so as to cover the N-type gate electrode 106.

Next, as shown in FIG. 6C, anisotropic etching is performed on the offset spacer 107A. Thereby, an offset spacer 107 having a film thickness of 3 nm is formed on the side surface of the N-type gate electrode 106.

Next, as shown in FIG. 6D, with the offset spacer 107 and the N-type gate electrode 106 used as a mask, an N-type impurity such as As is formed below the side of the N-type gate electrode 106 in the active region 101a. Ion implantation. As a result, an N-type extension region 108 is formed below the side of the N-type gate electrode 106 in the active region 101a.

Next, as shown in FIG. 6E, with the offset spacer 107 and the N-type gate electrode 106 as a mask, a P-type impurity such as B, for example, is formed below the side of the N-type gate electrode 106 in the active region 101a. Ion implantation. As a result, a P-type pocket region 109 is formed under the N-type extension region 108 in the active region 101a. Usually, FIG.6 (d) and FIG.6 (e) are performed continuously.

Next, as shown in FIG. 6 (f), a sidewall 110 made of a silicon oxide film or the like is formed on the side surface of the offset spacer 107.

Next, as shown in FIG. 6G, an N-type impurity such as As is formed on the outside of the sidewall 110 in the active region 101a with the sidewall 110, the offset spacer 107 and the N-type gate electrode 106 as a mask. Ion implantation. Thereafter, the semiconductor substrate 101 is heat-treated. As a result, N-type source / drain regions 111 are formed below the sidewalls 110 in the active region 101a.

JP 2004-63746 A

However, if the structure of the semiconductor device shown in FIG. 5 is adopted as a MOS transistor after the 32 nm process technology, there is a risk of increasing random variations of the transistors as shown below.

With the miniaturization of semiconductor devices, shallow junctions in extension regions are required. In this case, in order to sufficiently overlap the extension region and the gate electrode, it is necessary to reduce the thickness of the offset spacer.

On the other hand, when the offset spacer is thinned, impurity ions may penetrate through the offset spacer and polycrystalline silicon (gate electrode) and reach the channel region in the ion implantation step when forming the pocket region (channeling). . If the transistors are different, the impurity concentration in the channel region differs depending on whether or not channeling has occurred and the degree of channeling, which causes variations in transistor characteristics such as a large variation in the threshold voltage of the transistor shown in Equation 1. In the following, the reason why channeling occurs in the ion implantation process when forming the pocket region will be described in detail with reference to FIGS. 7A to 7C.

FIG. 7A is a drawing for explaining an ion implantation process when forming the P-type pocket region 109 in FIG. Here, as various dimensions, the gate length of the N-type gate electrode 106 is 32 nm, the gate height is 100 nm, and the film thickness of the offset spacer 107 is 3 nm. Also, in this ion implantation process, boron (B) ions are implanted four times at an implantation angle of 25 degrees with an implantation energy of 8 keV (the semiconductor substrate is rotated by 90 ° and ion implantation is performed every 90 °). It is assumed that boron ions having a total dose of 4.0 × 10 ¹³ cm ⁻² are implanted. Here, in the polycrystalline silicon constituting the N-type gate electrode 106, Si atoms are regularly arranged in each grain, but the direction of the crystal axis differs depending on the grain.

FIG. 7B and FIG. 7C are diagrams schematically showing the arrangement of Si atoms in the grains constituting the polycrystalline silicon, and FIG. 7B and FIG. Then, the directions of the crystal axes of grains composed of Si atoms are different from each other.

For example, when Si atoms are arranged as shown in FIG. 7B when polycrystalline silicon is viewed from the angle B → B ′ shown in FIG. 7A, boron ions are shown in FIG. ), The energy is lost by colliding with Si atoms and remains in the polycrystalline silicon. Therefore, in this case, channeling does not occur. On the other hand, when the polycrystalline silicon is viewed from the angle C → C ′ shown in FIG. 7A and the Si atoms are arranged as shown in FIG. When the implantation is performed from the angle of C → C ′ shown in FIG. 4, the channel region is reached through between adjacent Si atoms. Therefore, in this case, channeling occurs. Thus, depending on the arrangement of Si atoms in the N-type gate electrode 106, channeling occurs when the P-type pocket region 109 is formed. Therefore, if the N-type gate electrode 106 is different, the occurrence of channeling and the degree of channeling are different. Therefore, the impurity concentration in the channel region is different if the transistors are different.

As a method of suppressing the occurrence of such channeling, a method of increasing the thickness of the offset spacer 107 can be considered. Since the offset spacer 107 is amorphous, boron ions can be scattered in the offset spacer 107 if the offset spacer 107 has a certain thickness. However, since the thickness of the offset spacer 107 is required to be reduced as described above, the P-type pocket region 109 is formed while suppressing the occurrence of channeling by increasing the thickness of the offset spacer 107. Is difficult to realize.

Further, if the thickness of the offset spacer 107 is increased, the amount of overlap between the N-type gate electrode 106 and the N-type extension region 108 is reduced, and a high driving force cannot be realized.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can realize both high driving force and reduction in random variations of transistors.

The semiconductor device according to the present invention is manufactured by the following first or second manufacturing method.

A first manufacturing method of a semiconductor device according to the present invention includes a step (a) of forming a gate insulating film on a semiconductor region of the first conductivity type, and a step of forming a gate electrode on the gate insulating film (b) ), A step (c) of forming a first offset spacer on the side surface of the gate electrode, and a side of the gate electrode in the semiconductor region after the step (c) using the gate electrode and the first offset spacer as a mask. A step (d) of forming an extension region of the second conductivity type below, and a step of forming a second offset spacer on at least the side surface of the gate electrode via the first offset spacer after the step (d) ( e) and after the step (e), the gate electrode, the first offset spacer, and the second offset spacer are used as masks and the gate electrode in the lower side of the semiconductor region is exposed. Forming a first conductivity type pocket region under the tension region; and after the step (f), a sidewall is formed on the side surface of the gate electrode via the first offset spacer and the second offset spacer. (G) which forms.

The second method for manufacturing a semiconductor device according to the present invention includes steps (a) to (d) in the first manufacturing method and the following steps (e) to (g). Step (e) is a step of forming a second offset spacer forming film on the semiconductor region so as to cover the gate electrode and the first offset spacer after step (d). In the step (f), after the step (e), the gate electrode, the first offset spacer, and the second offset spacer forming film are used as masks to be below the extension region in the semiconductor region below the gate electrode. This is a step of forming a pocket region of the first conductivity type. In the step (g), after the step (f), a sidewall is formed on the side surface of the gate electrode via the first offset spacer and the second offset spacer formation film, and then the second offset spacer formation. This is a step of forming a second offset spacer by etching a portion exposed from the sidewall of the film.

As described above, in the first and second manufacturing methods of the semiconductor device according to the present invention, the extension region is formed using the first offset spacer as a mask, and the pocket region is formed using the first and second offset spacers as a mask. . Therefore, if the film thickness of the first offset spacer is optimized, the short channel effect can be suppressed and a high driving force can be realized. Further, if the total film thickness of the first and second offset spacers is optimized, the pocket region can be formed while suppressing the occurrence of channeling.

In particular, the thickness of the first offset spacer is 2 nm to 4 nm, the thickness of the second offset spacer is 2 nm to 4 nm, and the thickness of the first offset spacer and the thickness of the second offset spacer are If the total film thickness is 6 nm or more, the above effect can be obtained effectively.

In a preferred embodiment described later, the first offset spacer has an I-shaped cross-sectional shape, and the second offset spacer has an I-shaped or L-shaped cross-sectional shape.

According to the present invention, the short channel effect can be suppressed, high driving power can be realized, and random variations of transistors can be reduced.

1A to 1F are cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment in the order of steps. 2A to 2C are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. 3A to 3E are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment in the order of steps. 4A to 4D are cross-sectional views showing a method of manufacturing a semiconductor device according to the third embodiment in the order of steps. FIG. 5 is a cross-sectional view of a conventional semiconductor device. 6A to 6G are cross-sectional views showing a conventional method of manufacturing a semiconductor device in order of steps. FIGS. 7A to 7C are diagrams conceptually illustrating that impurity ions penetrate through polycrystalline silicon in an ion implantation process when forming a pocket region.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiment, an NMOS transistor will be described as an example, but the present invention is not limited to the NMOS transistor. In addition, the same components are denoted by the same reference numerals, and the description thereof may be omitted.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described in order with reference to the drawings. FIG. 1A to FIG. 2C are cross-sectional views showing a method of manufacturing a semiconductor device according to this embodiment in the order of steps.

As shown in FIG. 1A, first, an element isolation region 2 made of a silicon oxide film is formed on a semiconductor substrate 1 made of P-type silicon. Next, a P-type well 3 and a P-type impurity region 4 are formed by injecting a P-type impurity such as B (boron) into the portion of the semiconductor substrate 1 that becomes the NMOS transistor region. The P-type well 3 is formed deeper than the element isolation region 2 in the NMOS transistor region of the semiconductor substrate 1, and the region of the NMOS transistor region surrounded by the element isolation region 2 is the active region (first region). It functions as a conductive semiconductor region 1a. The P-type impurity region 4 is formed in the upper region of the active region 1a and functions as a channel region of the NMOS transistor.

Next, for example, a silicon oxide film (not shown) is formed on the upper surface of the semiconductor substrate 1. Thereafter, a polycrystalline silicon film (not shown) is deposited on the silicon oxide film by a CVD (Chemical Vapor Deposition) method or the like. Thereafter, an N-type impurity such as P (phosphorus) is selectively implanted into the NMOS transistor region, thereby doping the polycrystalline silicon film with the N-type impurity.

Next, the polycrystalline silicon film and the silicon oxide film are selectively removed by dry etching. As a result, a gate insulating film 5 made of a silicon oxide film is formed on the active region 1a (step (a)), and an N-type gate electrode 6 made of a polycrystalline silicon film is formed on the gate insulating film 5. (Step (b)).

Next, as shown in FIG. 1B, a first offset spacer forming film 7 A made of a silicon oxide film and having a thickness of 3 nm is formed on the upper surface of the semiconductor substrate 1. Thus, the first offset spacer forming film 7 A is formed on the semiconductor substrate 1 so as to cover the N-type gate electrode 6.

Next, as shown in FIG. 1C, anisotropic etching is performed on the first offset spacer forming film 7A. As a result, the first offset spacer forming film 7 A is removed from the portion of the upper surface of the semiconductor substrate 1 exposed from the N-type gate electrode 6 and the upper surface of the N-type gate electrode 6. A first offset spacer 7a having an I-shaped cross-sectional shape is formed (step (c)).

At this time, so-called over-etching is performed in which etching is performed for a predetermined time even after the anisotropic etching for the first offset spacer forming film 7A is completed. As a result, the portion exposed from the N-type gate electrode 6 and the first offset spacer 7 a in the upper surface of the active region 1 a in the semiconductor substrate 1, that is, the first offset spacer 7 a in the upper surface of the active region 1 a in the semiconductor substrate 1. As a result, the upper surface (S _B ) of the portion is etched below the upper surface (S _A ) of the active region 1a located immediately below the first offset spacer 7a (for example, about 1 nm). (Down).

Next, as shown in FIG. 1D, using the first offset spacer 7a and the N-type gate electrode 6 as a mask, for example, As (arsenic) or the like below the side of the N-type gate electrode 6 in the active region 1a. N-type impurities (second conductivity type first impurities) are ion-implanted. As a result, an N-type extension region (second conductivity type extension region) 8 is formed below the side of the N-type gate electrode 6 in the active region 1a (step (d)).

At this time, N-type impurities are also ion-implanted into the first offset spacer 7a. Therefore, the first offset spacer 7a becomes an insulating film containing an N-type impurity. Here, the concentration distribution of the N-type impurity in the first offset spacer 7a differs depending on the implantation angle in the ion implantation of the N-type impurity. For example, when the implantation angle in N-type impurity ion implantation is 0 degree, the concentration of the N-type impurity is the upper portion of the first offset spacer 7a (close to the upper surface of the N-type gate electrode 6 of the first offset spacer 7a). The portion is higher than the lower portion of the first offset spacer 7a (the portion of the first offset spacer 7a near the lower surface of the N-type gate electrode 6).

Next, as shown in FIG. 1E, a second offset spacer forming film 7B made of, for example, a silicon oxide film and having a thickness of 3 nm is formed on the upper surface of the semiconductor substrate 1. Next, as shown in FIG. Thus, the second offset spacer forming film 7B is formed on the semiconductor substrate 1 so as to cover the N-type gate electrode 6 and the first offset spacer 7a.

Next, as shown in FIG. 1F, anisotropic etching is performed on the second offset spacer forming film 7B. As a result, the second offset spacer forming film 7B is removed from the upper surface of the semiconductor substrate 1 at the portion exposed from the N-type gate electrode 6 and the first offset spacer 7a and the upper surface of the N-type gate electrode 6. A second offset spacer 7b having an I-shaped cross-sectional shape is formed on the side surface of the N-type gate electrode 6 through the one offset spacer 7a (step (e)).

At this time, over-etching is performed even after the anisotropic etching for the second offset spacer forming film 7B is completed. Thereby, the part exposed from the N-type gate electrode 6, the first offset spacer 7a, and the second offset spacer 7b in the upper surface of the active region 1a in the semiconductor substrate 1, that is, the upper surface of the active region 1a in the semiconductor substrate 1 Of these, a region located outside the second offset spacer 7b is etched, and the upper surface (S _D ) of that portion is lower than the upper surface (S _C ) of the active region 1a located immediately below the second offset spacer 7b. (For example, about 1 nm downward). Therefore, on the upper surface of the active region 1a, the portion located immediately below the gate insulating film 5 and the portion (S _A ) located directly below the first offset spacer 7a are flush with each other and are located immediately below the first offset spacer 7a. A portion (S _A ), a portion (S _C ) located immediately below the second offset spacer 7 b, and a portion exposed from the N-type gate electrode 6, the first offset spacer 7 a, and the second offset spacer 7 b ( It is located below in the order of S _D ). Accordingly, the bottom surface of the second offset spacer 7b is lower than the bottom surface of the first offset spacer 7a.

Next, as shown in FIG. 2A, using the second offset spacer 7b, the first offset spacer 7a and the N-type gate electrode 6 as a mask, the lateral lower side of the N-type gate electrode 6 in the active region 1a. In addition, for example, a P-type impurity such as B (second impurity of the first conductivity type) is ion-implanted. As a result, a P-type pocket region (first-conductivity-type pocket region) 9 is formed below the N-type extension region 8 in the lower side of the N-type gate electrode 6 in the active region 1a (step (f)). ).

At this time, a P-type impurity is also ion-implanted into the second offset spacer 7b. Therefore, the second offset spacer 7b becomes an insulating film containing a P-type impurity. Here, the concentration distribution of the P-type impurity in the second offset spacer 7b differs depending on the implantation angle in the ion implantation of the P-type impurity. For example, when the implantation angle in ion implantation of P-type impurities is 25 degrees, the concentration of the P-type impurities is substantially the same in the height direction of the second offset spacer 7b. In addition, if the ion implantation energy of the P-type impurity is large, a part of the P-type impurity may pass through the second offset spacer 7b and be implanted into the first offset spacer 7a.

Next, as shown in FIG. 2B, a sidewall 10 made of a silicon oxide film is formed on the side surface of the N-type gate electrode 6 via the first and second offset

spacers

7a and 7b (process). (G)).

Next, as shown in FIG. 2C, using the sidewall 10, the first and second offset

spacers

7a and 7b, and the N-type gate electrode 6 as a mask, the outside lower side of the sidewall 10 in the active region 1a. For example, an N-type impurity (second conductivity type impurity) such as As is ion-implanted. Thereafter, the semiconductor substrate 1 is heat-treated. As a result, an N-type source / drain region 11 is formed outside the sidewall 10 in the active region 1a. In this way, the semiconductor device according to this embodiment can be manufactured.

At this time, N-type impurities are also ion-implanted into the first and second offset

spacers

7a and 7b. Therefore, the first and second offset

spacers

7a and 7b are insulating films containing N-type impurities implanted in the step shown in FIG. Here, in this step, since the N-type impurity is implanted outside the sidewall 10 in the active region 1a, it is not implanted into the lower portions of the first and second offset

spacers

7a and 7b. Therefore, the first and second offset

spacers

7a and 7b contain the N-type impurity implanted in this step in each upper part but not in each lower part.

Here, as an example of the size of the N-type gate electrode 6 and the implantation conditions for ion implantation, the gate length of the N-type gate electrode 6 is 32 nm and the gate height is 100 nm. As the ion implantation conditions for forming the N-type extension region 8, As ions are implanted with an implantation energy of 2 keV and an implantation angle of 0 degree, and a total dose of 1.0 × 10 ¹⁵ cm ⁻² . Implant an amount of As ions. Also, as the ion implantation conditions for forming the P-type pocket region 9, B ions are implanted four times at an implantation energy of 8 keV and an implantation angle of 25 degrees, for a total of 4.0 × 10 ¹³ cm ^−2. B ions of a dose of

Hereinafter, the effects of the semiconductor device manufacturing method according to the present embodiment will be described while comparing with known semiconductor device manufacturing methods.

6A to 6G, the N-type extension region 108 and the P-type pocket are formed below the side of the N-type gate electrode 106 in the active region 101a using the offset spacer 107 as a mask. Region 109 is formed. In this case, since the thickness of the offset spacer 107 is 3 nm, a high driving force can be realized while suppressing the short channel effect. However, when the P-type pocket region 109 is formed, P-type impurity ions are offset. Difficult to scatter at 107. Therefore, P-type impurity ions are not implanted into the P-type impurity region 104 when the arrangement of Si atoms in the N-type gate electrode 106 is shown in FIG. 7B, but the arrangement of Si atoms in the N-type gate electrode 106 is not. In the case shown in FIG. 7C, the impurity is implanted into the P-type impurity region 104. Therefore, if the transistors are different, the P-type impurity ion concentration in the P-type impurity region 104 is different, and as a result, random variations of the transistors are increased.

On the other hand, if the thickness of the offset spacer 107 is 6 nm in the method for manufacturing the semiconductor device shown in FIGS. 6A to 6G, the P-type impurity implanted when the P-type pocket region 109 is formed. Since ions can be scattered in the offset spacer 107, the P-type pocket region 109 can be formed while suppressing the occurrence of channeling. Therefore, even if the transistors are different, the concentration of the P-type impurity ions in the P-type impurity region 104 does not change so much. However, when the thickness of the offset spacer 107 is 6 nm, when the N-type extension region 108 is formed, implantation of N-type impurity ions below both ends of the N-type gate electrode 106 is suppressed. The amount of overlap between 106 and the N-type extension region 108 is reduced, and a high driving force cannot be realized.

However, in the method of manufacturing the semiconductor device according to the present embodiment, the N-type extension region 8 is formed using the first offset spacer 7a as a mask as shown in FIG. 1D, and as shown in FIG. A P-type pocket region 9 is formed using the first and second offset

spacers

7a and 7b as a mask. Thus, in the method for manufacturing a semiconductor device according to the present embodiment, the mask for forming the N-type extension region 8 and the mask for forming the P-type pocket region 9 are different from each other. The film thickness of the mask when forming the mask and the film thickness of the mask when forming the P-type pocket region 9 can be optimized separately.

Specifically, in the method of manufacturing a semiconductor device according to the present embodiment, the film thickness of the mask (the film thickness of the first offset spacer 7a) when forming the N-type extension region 8 is offset in FIG. Since the thickness of the spacer 107 is the same as that of the semiconductor device shown in FIG. 5, the overlap amount between the N-type gate electrode 6 and the N-type extension region 8 can be optimized, thereby suppressing the short channel effect. High driving force can be realized.

In the method for manufacturing the semiconductor device according to the present embodiment, the thickness of the mask (the total thickness of the first and second offset

spacers

7a and 7b) when forming the P-type pocket region 9 is as shown in FIG. ) Is thicker than the thickness of the offset spacer 107 in FIG. 9, the P-type impurity ions implanted into the P-type pocket region 9 can be scattered by the first and second offset

spacers

7 a and 7 b. Therefore, the P-type impurity ions implanted into the P-type pocket region 9 can be prevented from being implanted into the P-type impurity region 4 (channel region) regardless of the arrangement of the Si atoms in the N-type gate electrode 6. Can be reduced.

Thus, in the semiconductor device manufacturing method according to the present embodiment, a semiconductor device capable of realizing a high driving force can be provided, and the short channel effect can be suppressed. In addition, in the method for manufacturing a semiconductor device according to the present embodiment, the P-type pocket region 9 can be formed while suppressing the occurrence of channeling, so that random variations in transistors can be reduced.

In the semiconductor device manufacturing method according to the present embodiment, the second offset spacer 7b is formed after the first offset spacer 7a is formed. Therefore, unlike the case where only one offset spacer is formed or the case where a plurality of offset spacers are formed simultaneously, as shown in FIG. 2B, the first offset spacer is formed on the upper surface of the active region 1a. _A portion (S _A ) located immediately below 7 a, a portion (S _C ) located immediately below the second offset spacer 7 b, and a portion (S _E ) located directly below the sidewall 10 are positioned below in this order.

As shown in FIG. 2C, the semiconductor device using the semiconductor device manufacturing method according to this embodiment includes a semiconductor substrate 1 made of P-type silicon, an element isolation region 2 formed in the semiconductor substrate 1, and In the NMOS transistor region of the semiconductor substrate 1, a P-type well 3 formed deeper than the element isolation region 2, an active region 1a composed of the semiconductor substrate 1 surrounded by the element isolation region 2, and an upper region in the active region 1a From the formed P-type impurity region (channel region) 4, the gate insulating film 5 formed on the active region 1a, and formed on the gate insulating film 5, for example, from polycrystalline silicon containing N-type impurities such as P An N-type gate electrode 6, a first offset spacer 7 a formed on the side surface of the N-type gate electrode 6 and having an I-shaped cross-section, and the first offset spacer 7 a A second offset spacer 7b formed on the side surface of the n-type gate electrode 6 and having an I-shaped cross-sectional shape; and an N-type extension region 8 formed below the side of the N-type gate electrode 6 in the active region 1a. In the active region 1a, a P-type pocket region 9 formed below the N-type extension region 8 out of the side of the N-type gate electrode 6 and the N-type via the first and second offset

spacers

7a and 7b. A sidewall 10 formed on the side surface of the gate electrode 6 and an N-type source / drain region 11 formed outside the sidewall 10 in the active region 1a are provided.

Unlike the conventional semiconductor device shown in FIG. 5, such a semiconductor device includes first and second offset

spacers

7a and 7b. The first and second offset

spacers

7a and 7b are both made of a silicon oxide film and have a thickness of 3 nm. The first offset spacer 7a functions as a mask for forming the N-type extension region 8 and the P-type pocket region 9 in the same manner as the offset spacer 107 in the conventional semiconductor device shown in FIG. 7b functions as a mask when the P-type pocket region 9 is formed. Therefore, in the semiconductor device according to the present embodiment, a high driving force can be realized, and further, the short channel effect can be suppressed. Further, in the semiconductor device according to the present embodiment, the P-type impurity concentration in the P-type impurity region 4 does not change so much even if the transistors are different, so that random variations of the transistors can be reduced.

The first and second offset

spacers

7a and 7b will be briefly described below.

The first offset spacer 7a functions as a mask when the N-type extension region 8 is formed. However, since the second offset spacer 7 b cannot function as a mask when forming the N-type extension region 8, the second offset spacer 7 b does not contain the N-type impurity constituting the N-type extension region 8. Therefore, the concentration of the N-type impurity constituting the N-type extension region 8 is higher in the first offset spacer 7a than in the second offset spacer 7b.

The first and second offset

spacers

7 a and 7 b function as a mask when forming the P-type pocket region 9. The P-type impurity is injected into the first offset spacer 7a when passing through the second offset spacer 7b. Therefore, the concentration of the P-type impurity is higher in the second offset spacer 7b than in the first offset spacer 7a.

The first and second offset

spacers

7a and 7b function as a mask when the N-type source / drain region 11 is formed. Since the N-type source / drain region 11 is formed outside the sidewall 10 in the active region 1a, the N-type impurities constituting the N-type source / drain region 11 are the first and second offset spacers 7a. 7b can be injected into each upper part, but not into each lower part. Therefore, the concentration of the N-type impurity constituting the N-type source / drain region 11 is higher in the upper part than in the lower part in each of the first and second offset

spacers

7a and 7b.

(Second Embodiment)
In the second embodiment of the present invention, unlike the first embodiment, the cross-sectional shape of the second offset spacer is L-shaped. In the following, differences from the first embodiment will be mainly described.

FIG. 3A to FIG. 3E are cross-sectional views showing a part of the steps of the semiconductor device manufacturing method according to this embodiment in the order of steps.

First, FIG. 1A to FIG. 1E in the first embodiment are sequentially performed to obtain the structure shown in FIG. At this time, in the step shown in FIG. 1D, N-type impurities are ion-implanted not only in the lateral region of the N-type gate electrode 6 in the active region 1a but also in the first offset spacer 7a. Therefore, the first offset spacer 7a becomes an insulating film containing an N-type impurity. Here, the concentration distribution of the N-type impurity in the first offset spacer 7a differs depending on the implantation angle in the ion implantation of the N-type impurity. For example, when the implantation angle in N-type impurity ion implantation is 0 degree, the concentration of the N-type impurity is higher in the upper part of the first offset spacer 7a than in the lower part of the first offset spacer 7a.

Next, as shown in FIG. 3B, the second offset spacer forming film 7B, the first offset spacer 7a and the N-type gate electrode 6 are used as a mask to form the N-type gate electrode 6 in the active region 1a. For example, a P-type impurity such as B is ion-implanted under the side. As a result, a P-type pocket region 9 is formed below the N-type extension region 8 at the side of the N-type gate electrode 6 in the active region 1a (step (f)).

At this time, P-type impurities are also ion-implanted into the second offset spacer forming film 7B. Therefore, the second offset spacer forming film 7B is an insulating film containing a P-type impurity. Here, the concentration distribution of the P-type impurity in the second offset spacer forming film 7B varies depending on the implantation angle in the ion implantation of the P-type impurity. For example, when the implantation angle in the ion implantation of the P-type impurity is 25 degrees, the concentration of the P-type impurity is as follows in the portion of the second offset spacer forming film 7B located on the side surface of the N-type gate electrode 6. It becomes substantially the same in the height direction of the N-type gate electrode 6. Further, if the ion implantation energy of the P-type impurity is large, a part of the P-type impurity may pass through the second offset spacer forming film 7B and be implanted into the first offset spacer 7a.

Next, as shown in FIG. 3C, a sidewall forming film 20 A made of a silicon nitride film is formed on the upper surface of the semiconductor substrate 1. As a result, the sidewall forming film 20A is formed on the second offset spacer forming film 7B.

Next, as shown in FIG. 3D, anisotropic etching is sequentially performed on the sidewall forming film 20A and the second offset spacer forming film 7B. As a result, the sidewalls are formed on the upper surface of the N-type gate electrode 6, the element isolation region 2, and the peripheral portion of the element isolation region 2 (the source / drain formation region of the upper surface of the semiconductor substrate 1). The forming film 20A and the second offset spacer forming film 7B are removed, and the second offset spacer 7c and the sidewall 20 having an L-shaped cross-sectional shape are connected to the N-type gate via the first offset spacer 7a. It is formed on the side surface of the electrode 6 (step (e), step (g)). At this time, the sidewall forming film 20A is anisotropically etched to form the sidewall 20, and then exposed from the sidewall 20 in the second offset spacer forming film 7B using the sidewall 20 as a mask. The portion subjected to anisotropic etching is subjected to anisotropic etching to form a second offset spacer 7c.

At this time, when the anisotropic etching for the second offset spacer formation film 7B and the sidewall formation film 20A is completed, the etching is stopped. Thereby, on the upper surface of the active region 1a, the portion (S _F ) located immediately below the second offset spacer 7c is positioned below the portion (S _A ) located directly below the first offset spacer 7a. It is flush with the portion (S _G ) exposed from the N-type gate electrode 6, the first offset spacer 7a, and the second offset spacer 7c.

Next, as shown in FIG. 3 (e), the sidewall 20, the first and second offset

spacers

7a and 7c, and the N-type gate electrode 6 are used as a mask to lower the outside of the sidewall 20 in the active region 1a. For example, an N-type impurity such as As is ion-implanted. Thereafter, the semiconductor substrate 1 is heat-treated. As a result, an N-type source / drain region 11 is formed outside the sidewall 20 in the active region 1a.

At this time, as described in the first embodiment, the N-type impurity is ion-implanted into the upper portion of the first offset spacer 7a, but is not implanted into the lower portion of the first offset spacer 7a. Similarly, the N-type impurity is ion-implanted into the upper portion of the second offset spacer 7c located on the side surface of the N-type gate electrode 6, but the N-type gate electrode 6 in the second offset spacer 7c. Ion implantation is not performed on the lower portion of the portion located on the side surface of the first offset spacer and the portion of the second offset spacer 7 c located between the semiconductor substrate 1 and the sidewall 20.

As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the mask for forming the N-type extension region 8 and the mask for forming the P-type pocket region 9 are the same as in the first embodiment. Since they are different from each other, the film thickness of the mask when forming the N-type extension region 8 and the film thickness of the mask when forming the P-type pocket region 9 can be optimized separately. Therefore, the short channel effect can be suppressed, a high driving force can be realized, and the P-type pocket region 9 can be formed while suppressing the occurrence of channeling.

Further, in the method for manufacturing a semiconductor device according to the present embodiment, unlike the method for manufacturing a semiconductor device according to the first embodiment, for example, as shown in FIG. A sidewall forming film 20A is formed through the offset spacer forming film 7B. Therefore, since the sidewall 20 is formed on the upper surface of the semiconductor substrate 1 via the second offset spacer 7c, it is possible to avoid providing the sidewall 20 directly on the upper surface of the semiconductor substrate 1. Therefore, the stress applied to the semiconductor substrate 1 by the sidewall 20 can be reduced. In particular, when a silicon oxide film is used as the second offset spacer 7c and a silicon nitride film is used as the sidewall 20, the stress applied to the semiconductor substrate 1 by the silicon nitride film (sidewall 20) can be efficiently reduced. Can do.

Further, unlike the method for manufacturing a semiconductor device according to the first embodiment, the method for manufacturing a semiconductor device according to the present embodiment can avoid providing the sidewalls 20 directly on the upper surface of the semiconductor substrate 1. The capacitance (fringe capacitance) between the side surface of the gate electrode 6 and the N-type source / drain region 11 can be reduced. In particular, when a silicon oxide film is used as the second offset spacer 7c and a silicon nitride film is used as the sidewall 20, the silicon nitride film (sidewall 20) is a silicon oxide having a relative dielectric constant smaller than that of the silicon nitride film. Since it is provided on the upper surface of the semiconductor substrate 1 via the film (second offset spacer 7c), the fringe capacity can be efficiently reduced.

As described above, in the method for manufacturing a semiconductor device according to the present embodiment, in addition to the effects exhibited by the method for manufacturing a semiconductor device according to the first embodiment, the stress applied to the semiconductor substrate 1 by the sidewall 20 is reduced. And the fringe capacity can be reduced.

In the semiconductor device manufactured using the manufacturing method according to the present embodiment, as shown in FIG. 3E, the second offset spacer 7c is different from the second offset spacer 7b in the first embodiment. Unlike the sidewall 10 in the first embodiment, the sidewall 20 is provided on the upper surface of the semiconductor substrate 1 via the second offset spacer 7c. . Other configurations are the same as those in the first embodiment.

In such a semiconductor device, as in the semiconductor device according to the first embodiment, the first offset spacer 7a functions as a mask when forming the N-type extension region 8 and the P-type pocket region 9, The second offset spacer 7 c functions as a mask when forming the P-type pocket region 9. Therefore, like the semiconductor device according to the first embodiment, the semiconductor device according to the present embodiment can realize a high driving force while suppressing the short channel effect. It is possible to prevent the concentration of the P-type impurity in the type impurity region 4 from varying.

Furthermore, since the sidewall 20 is provided on the upper surface of the semiconductor substrate 1 via the second offset spacer 7c having an L-shaped cross-sectional shape, it is possible to reduce the stress applied to the semiconductor substrate 1 by the sidewall 20. And fringe capacity can be reduced. In particular, when the second offset spacer 7c is made of a silicon oxide film and the sidewall 20 is made of a silicon nitride film, the stress applied to the semiconductor substrate 1 by the silicon nitride film (sidewall 20) is effectively reduced. And fringe capacity can be effectively reduced.

The first and second offset

spacers

7a and 7c will be briefly described below.

As described in the first embodiment, the second offset spacer 7c does not include the N-type impurity constituting the N-type extension region 8, and the concentration of the N-type impurity constituting the N-type extension region 8 is as follows. The first offset spacer 7a is higher than the second offset spacer 7c. The concentration of the P-type impurity constituting the P-type pocket region 9 is higher in the second offset spacer 7c than in the first offset spacer 7a. In addition, the concentration of the N-type impurity constituting the N-type source / drain region 11 is higher in the upper part than in the lower part in each of the first and second offset

spacers

7a and 7c (however, the "first" The “lower part of the second offset spacer 7c” does not include a part of the lower part of the second offset spacer 7c located between the semiconductor substrate 1 and the sidewall 20).

(Third embodiment)
Unlike the first embodiment, the semiconductor device according to the third embodiment includes a sidewall composed of two layers. Hereinafter, differences from the first embodiment will be mainly described.

FIGS. 4A to 4D are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of steps.

First, FIG. 1A to FIG. 2A in the first embodiment are sequentially performed to obtain the structure shown in FIG. At this time, the N-type extension region 8, the second offset spacer 7b, and the P-type pocket region 9 are formed in this order. Therefore, a P-type impurity (P-type impurity implanted when forming the P-type pocket region 9) is implanted into the second offset spacer 7b, but an N-type impurity (N-type extension region 8 is formed). N-type impurities) are not implanted.

Next, as shown in FIG. 4B, an inner side wall forming film 30A made of a silicon oxide film and an outer side wall forming film 30B made of a silicon nitride film are sequentially formed on the upper surface of the semiconductor substrate 1. To do. Thus, the inner side wall forming film 30A is formed on the upper surface of the semiconductor substrate 1 so as to cover the N-type gate electrode 6, the first offset spacer 7a, and the second offset spacer 7b. The outer sidewall forming film 30B is formed on the inner sidewall forming film 30A.

Next, as shown in FIG. 4C, anisotropic etching is sequentially performed on the inner side wall forming film 30A and the outer side wall forming film 30B. As a result, the inner side of the upper surface of the N-type gate electrode 6, the element isolation region 2, and the peripheral portion of the element isolation region 2 (the source / drain formation region of the upper surface of the semiconductor substrate 1) of the upper surface of the semiconductor substrate 1. The wall forming film 30A and the outer side wall forming film 30B are removed, and the side wall 30 including the inner side wall 30a and the outer side wall 30b having an L-shaped cross-sectional shape is the first and second offset spacers 7a. , 7b on the side surface of the N-type gate electrode 6 (step (g)).

Next, as shown in FIG. 4D, the sidewall 30, the first and second offset

spacers

7 a and 7 b, and the N-type gate electrode 6 are used as a mask to lower the outside of the sidewall 30 in the active region 1 a. For example, an N-type impurity such as As is ion-implanted. Thereafter, the semiconductor substrate 1 is heat-treated. As a result, an N-type source / drain region 11 is formed below the sidewall 30 in the active region 1a.

Furthermore, the semiconductor device manufacturing method according to the present embodiment has an L-shaped cross-sectional shape as shown in FIG. 4C, for example, unlike the semiconductor device manufacturing method according to the first embodiment. Since the sidewall 30 having the inner sidewall 30a and the outer sidewall 30b is formed, it is possible to avoid providing the outer sidewall 30b directly on the upper surface of the semiconductor substrate 1. Therefore, the stress applied to the semiconductor substrate 1 by the outer sidewall 30b can be reduced. In particular, when a silicon oxide film is used as the inner side wall 30a and a silicon nitride film is used as the outer side wall 30b, stress applied to the semiconductor substrate 1 by the silicon nitride film (outer side wall 30b) can be efficiently reduced. Can do.

As described above, in the method for manufacturing a semiconductor device according to the present embodiment, in addition to the effects exhibited by the method for manufacturing a semiconductor device according to the first embodiment, the stress exerted on the semiconductor substrate 1 by the outer sidewall 30b is applied. Can be reduced.

As shown in FIG. 4D, in the semiconductor device manufactured using the method for manufacturing a semiconductor device according to the present embodiment, the side wall 30 is different from the side wall 10 in the first embodiment. It is comprised by the inner side wall 30a and the outer side wall 30b which have a letter-shaped cross-sectional shape. The outer side wall 30b is formed on the upper surface of the semiconductor substrate 1 via the inner side wall 30a. Other configurations are the same as those in the first embodiment.

Such a semiconductor device can obtain the same effects as those of the semiconductor device according to the first embodiment.

Furthermore, since the outer side wall 30b is formed on the upper surface of the semiconductor substrate 1 via the inner side wall 30a, the stress applied to the semiconductor substrate 1 by the outer side wall 30b can be reduced. In particular, when the inner side wall 30a is made of a silicon oxide film and the outer side wall 30b is made of a silicon nitride film, the stress applied to the semiconductor substrate 1 by the silicon nitride film (outer side wall 30b) can be efficiently reduced. it can.

In the semiconductor device according to the present embodiment, the portion (S _C ) located immediately below the second offset spacer 7b on the upper surface of the active region 1a is the same as in the semiconductor device according to the first embodiment. The portion (S _E ) located below the portion (S _A ) located immediately below the offset spacer 7a, and the portion (S _E ) located directly below the sidewall 30 from the portion (S _C ) located directly below the second offset spacer 7b. Is also located below.

(Other embodiments)
The first to third embodiments may have the following configurations.

The first and second offset spacers are made of a silicon oxide film, but may be made of a silicon nitride film. In addition, since the material of the other offset spacer can be selected without being limited to the material of one offset spacer, the first offset spacer is made of a silicon oxide film and the second offset spacer is made of a silicon nitride film. Alternatively, the first offset spacer may be made of a silicon nitride film, and the second offset spacer may be made of a silicon oxide film. In any case, the effects exhibited by the first to third embodiments can be obtained. In the second embodiment, if the second offset spacer is made of a silicon oxide film, the stress on the substrate and the fringe capacity can be reduced.

Although the film thickness of the first offset spacer is 3 nm, it is preferable to change this film thickness according to the ion implantation conditions for forming the extension region. For example, the film thickness is set to 2 nm or more and 4 nm or less. Can do. Further, it is preferable that the thickness of the first offset spacer is 2 nm or more and 4 nm or less because the short channel effect can be suppressed and a high driving force can be realized.

Although the film thickness of the second offset spacer is 3 nm, it is preferable to change this film thickness according to the ion implantation conditions for forming the pocket region. For example, the film thickness is set to 2 nm or more and 4 nm or less. Can do. Further, if the total film thickness of the first offset spacer and the second offset spacer is 6 nm or more, it is preferable because the pocket region can be formed while channeling is suppressed. Therefore, the film thicknesses of the first and second offset spacers may be set so that the total film thickness is 6 nm or more and each film thickness is 2 nm or more and 4 nm or less.

Although the gate insulating film is made of a silicon oxide film, it may be a single layer film made of a high dielectric constant insulating film or a laminated film of a base insulating film (for example, silicon oxide film) and a high dielectric constant insulating film. There may be. The high dielectric constant insulating film is an insulating film having a relative dielectric constant higher than that of the silicon nitride film, and is a film made of an insulating metal oxide or insulating metal silicate having a relative dielectric constant of 8 or more, preferably 10 or more. When a high dielectric constant insulating film is used as the gate insulating film in this way, in addition to the effects exhibited by the first to third embodiments, the generation of leakage current can be suppressed, so that a highly reliable semiconductor device Can be realized.

Although the gate electrode is made of a polycrystalline silicon film, it may be made of a single layer film made of a metal film or a laminated film made of a metal film and a polycrystalline silicon film. When a metal film is used as the gate electrode in contact with the gate insulating film in this way, depletion of the gate electrode can be suppressed in addition to the effects exhibited by the first to third embodiments, thereby improving the transistor characteristics. Can be planned.

Although the semiconductor device is an NMOS transistor, it may be a PMOS (Positive / Channel / Metal / Oxide / Semiconductor) transistor. If the semiconductor device is a PMOS transistor, the semiconductor substrate is made of N-type silicon, and a P-type extension region and an N-type pocket region are formed in the semiconductor substrate. Even in such a case, the effects exhibited by the first to third embodiments can be obtained.

Further, the sidewall in the second embodiment may be composed of an inner sidewall and an outer sidewall having an L-shaped cross-sectional shape like the sidewall in the third embodiment.

In the first to third embodiments, the portion of the upper surface of the active region 1a located immediately below the gate insulating film 5 and the portion (S _A ) located immediately below the first offset spacer 7a are flush with each other. As described above, the portion (S _A ) located immediately below the first offset spacer 7 a may be located below the portion located directly below the gate insulating film 5. A silicide layer may be formed on the upper surface of the N-type gate electrode 6 and the upper surface of the N-type source / drain region 11.

In the first to third embodiments, the upper ends of the first offset spacer, the second offset spacer, and the sidewall are located at the same height, but the upper ends are different from each other. It may be located at a height. For example, the upper ends of the first and second offset spacers may be positioned at the same height, and the upper ends of the sidewalls may be lower than the upper ends of the first and second offset spacers. Further, the upper end of the second offset spacer may be lower than the upper end of the first offset spacer and higher than the upper end of the sidewall.

As described above, the present invention is useful for miniaturization and high drive of a semiconductor device.

1 Semiconductor substrate
1a Active region
2 Device isolation region
3 P-type well
4 P-type impurity region
5 Gate insulation film
6 N-type gate electrode
7A First offset spacer forming film
7B Second offset spacer forming film
7a First offset spacer
7b Second offset spacer
7c Second offset spacer
8 N-type extension area
9 P-type pocket area
10 Sidewall
11 N-type source / drain regions
20 sidewall
20A Side wall forming film
30 side walls
30A Inner side wall forming film
30B Film for forming outer side wall
30a Inside sidewall
30b Outer side wall

Claims

A gate insulating film formed on the semiconductor region of the first conductivity type;
A gate electrode formed on the gate insulating film;
A first offset spacer formed on a side surface of the gate electrode;
A second offset spacer formed on at least a side surface of the gate electrode via the first offset spacer;
A sidewall formed on a side surface of the gate electrode through the first offset spacer and the second offset spacer;
An extension region of a second conductivity type formed below the side of the gate electrode in the semiconductor region;
A semiconductor device comprising: a pocket region of a first conductivity type formed below the extension region of the semiconductor region below the side of the gate electrode.
The semiconductor device according to claim 1,
The first offset spacer has an I-shaped cross-sectional shape,
The semiconductor device, wherein the second offset spacer has an I-shaped cross-sectional shape.
The semiconductor device according to claim 1,
The first offset spacer has an I-shaped cross-sectional shape,
The semiconductor device, wherein the second offset spacer has an L-shaped cross-sectional shape.
The semiconductor device according to claim 1,
The side wall includes an inner side wall having an L-shaped cross section and an outer side wall formed on the inner side wall.
The semiconductor device according to claim 1,
The thickness of the first offset spacer is 2 nm or more and 4 nm or less,
The thickness of the second offset spacer is 2 nm or more and 4 nm or less,
The total thickness of the film thickness of the first offset spacer and the film thickness of the second offset spacer is 6 nm or more.
The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein an upper surface of the semiconductor region located immediately below the sidewall is located below a top surface of the semiconductor region located immediately below the second offset spacer.
The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein an upper surface of the semiconductor region located immediately below the second offset spacer is located below a top surface of the semiconductor region located immediately below the first offset spacer.
The semiconductor device according to claim 1,
The extension region contains a first impurity of the second conductivity type,
The pocket region contains a second impurity of the first conductivity type,
The second offset spacer includes the second impurity, but does not include the first impurity.
The semiconductor device according to claim 1,
A semiconductor device, wherein a second conductivity type impurity is not contained in at least a lower part of a portion of the second offset spacer formed on the side surface of the gate electrode.
The semiconductor device according to claim 1,
The semiconductor device, wherein the first offset spacer is made of a silicon nitride film.
The semiconductor device according to claim 1,
The semiconductor device, wherein the gate insulating film has at least a high dielectric constant insulating film.
The semiconductor device according to claim 1,
The semiconductor device, wherein the gate electrode has at least a metal film in contact with the gate insulating film.
The semiconductor device according to claim 1,
The semiconductor device is characterized in that the thickness of the first offset spacer is 2 nm or more and 4 nm or less.
The semiconductor device according to claim 1,
The semiconductor device is characterized in that the thickness of the second offset spacer is 2 nm or more and 4 nm or less.
Forming a gate insulating film on the semiconductor region of the first conductivity type (a);
Forming a gate electrode on the gate insulating film (b);
Forming the first offset spacer on a side surface of the gate electrode;
After the step (c), using the gate electrode and the first offset spacer as a mask, a step (d) of forming a second conductivity type extension region below the side of the gate electrode in the semiconductor region;
After the step (d), a step (e) of forming a second offset spacer on at least a side surface of the gate electrode through the first offset spacer;
After the step (e), the gate electrode, the first offset spacer, and the second offset spacer are used as a mask to form a first under the extension region of the semiconductor region below the gate electrode. Forming a conductive pocket region (f);
After the step (f), a step (g) of forming a sidewall on a side surface of the gate electrode through the first offset spacer and the second offset spacer is provided. A method for manufacturing a semiconductor device.
In the manufacturing method of the semiconductor device according to claim 15,
In the step (c), the first offset spacer has an I-shaped cross-sectional shape,
In the step (e), the second offset spacer has an I-shaped cross-sectional shape.
In the manufacturing method of the semiconductor device according to claim 15,
The film thickness of the first offset spacer is 2 nm or more and 4 nm or less,
The film thickness of the second offset spacer is 2 nm or more and 4 nm or less,
A method of manufacturing a semiconductor device, wherein a total film thickness of the film thickness of the first offset spacer and the film thickness of the second offset spacer is 6 nm or more.
Forming a gate insulating film on the semiconductor region of the first conductivity type (a);
Forming a gate electrode on the gate insulating film (b);
Forming the first offset spacer on a side surface of the gate electrode;
After the step (c), using the gate electrode and the first offset spacer as a mask, a step (d) of forming a second conductivity type extension region below the side of the gate electrode in the semiconductor region;
After the step (d), a step (e) of forming the second offset spacer forming film on the semiconductor region so as to cover the gate electrode and the first offset spacer;
After the step (e), using the gate electrode, the first offset spacer, and the second offset spacer forming film as a mask, below the extension region of the semiconductor region below the gate electrode. Forming a first conductivity type pocket region in (f),
After the step (f), a sidewall is formed on the side surface of the gate electrode via the first offset spacer and the second offset spacer forming film, and then the second offset spacer forming film. And (g) forming a second offset spacer by etching a portion exposed from the sidewall.