JP2007123439A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To mitigate a stress to be applied to peripheral materials with a metal gate electrode. <P>SOLUTION: The semiconductor device comprises an n-channel MIS transistor including the first gate insulating film 3a formed on a semiconductor substrate 1, the first metal gate electrode 4A formed on the first gate insulating film 3a, the first impurity diffusing region 12a formed in a region located in the side of the first metal gate 4A, and the first side wall 10a formed on the side surface of the first metal gate electrode 4A. Between the first metal gate electrode 4A and the first side wall 1a, the stress mitigating portions (9a, 16) are formed in the structure for reducing an internal stress of the first metal gate electrode 4a. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, in a semiconductor device including a MIS transistor using a metal gate electrode, applied to peripheral materials due to internal stress of a metal constituting the metal gate electrode. The present invention relates to a method for suppressing stress.

  Conventionally, a highly doped semiconductor (high concentration impurity semiconductor) has been used as an electrode constituting a semiconductor device. Thus, for example, if a high-concentration impurity semiconductor is used as a material for forming a gate electrode of a field effect element, a simple element manufacturing process can be obtained.

  However, when a high-concentration impurity semiconductor is used for a gate electrode of a field effect element, when a voltage is applied to the gate electrode, a depletion layer is formed at the interface with the gate insulating film inside the gate electrode, thereby There is a problem in that the effective thickness of the film increases and the electrical characteristics deteriorate.

  Hereinafter, a method for manufacturing a semiconductor device having a conventional MIS transistor will be described.

  9 (a) to 9 (d) and FIGS. 10 (a) to 10 (d) show the cross-sectional states in the respective steps of the conventional method for manufacturing a semiconductor device in the order of steps. In FIG. 9A and FIG. 10A, the n-type MIS transistor formation region Rn and the p-type MIS transistor are formed as regions where the n-type MIS transistor is formed. P-type MIS transistor formation region Rp.

  First, as shown in FIG. 9A, an element isolation region 102 made of shallow trench isolation (STI) is formed on a semiconductor substrate 101 by a normal element isolation formation method. Thereby, the active region of the n-type MIS transistor and the active region of the p-type MIS transistor are partitioned. Subsequently, a p-type impurity is ion-implanted into the semiconductor substrate 101 in the n-type MIS transistor formation region Rn to form a p-type well region 101a, while an n-type impurity is added into the semiconductor substrate 101 in the p-type MIS transistor formation region Rp. Are ion-implanted to form an n-type well region 101b.

  Subsequently, a gate oxide film to be a gate insulating film, a polysilicon film to be a gate forming silicon film, and a protective oxide film to be a protective insulating film are sequentially formed on the semiconductor substrate 101. Subsequently, the protective oxide film, the polysilicon film, and the gate oxide film are sequentially etched by using lithography technology and anisotropic dry etching, so that the gate insulating films 103a and 103b, the gate forming silicon films 104a and 104b, and Protective insulating films 105a and 105b are formed. As a result, an n-type gate forming portion 106a composed of the gate insulating film 103a, the gate forming silicon film 104a, and the protective insulating film 105a is formed on the semiconductor substrate 101 in the n-type MIS transistor formation region Rn, and the p-type is formed. On the semiconductor substrate 101 in the MIS transistor formation region Rp, a p-type gate formation portion 106b including a gate insulating film 103b, a gate forming silicon film 104b, and a protective insulating film 105b is formed.

  Subsequently, by using the n-type gate forming portion 106a as a mask, n-type impurities are ion-implanted into the semiconductor substrate 101 in the n-type MIS transistor forming region Rn, thereby forming an n-type extension region 107a. A p-type pocket region 108a is formed by ion-implanting p-type impurities into the semiconductor substrate 101 in the n-type MIS transistor formation region Rn using the gate formation portion 106a as a mask. Also, by using the p-type gate formation portion 106b as a mask, p-type impurities are ion-implanted into the semiconductor substrate 101 in the p-type MIS transistor formation region Rp, thereby forming a p-type extension region 108b. An n-type pocket region 108b is formed by ion-implanting an n-type impurity into the semiconductor substrate 101 in the p-type MIS transistor formation region Rp using the formation portion 106b as a mask.

  Next, as shown in FIG. 9B, a first insulating film 20 nm thick made of a silicon oxide film and a second insulating film 50 nm thick made of a silicon nitride film are formed on the entire surface of the semiconductor substrate 101. A film is sequentially formed. Thereafter, by sequentially etching back the second insulating film and the first insulating film, the cross-sectional shape made of the first insulating film is formed on each side surface of the n-type gate forming portion 106a and the p-type gate forming portion 106b. L-shaped first sidewalls 109a and 109b and second sidewalls 110a and 110b made of a second insulating film are formed on the first sidewalls 109a and 109b.

Subsequently, arsenic ions, which are n-type impurities, are implanted into the semiconductor substrate 101 in the n-type MIS transistor formation region Rn using the n-type gate formation portion 106a and the first and second sidewalls 9a and 10a as masks. N-type source / drain regions 111a are formed by ion implantation under the conditions of 10 keV and an implantation dose of 1 × 10 ¹⁵ / cm ² . Further, boron ions, which are p-type impurities, are implanted into the semiconductor substrate 101 in the p-type MIS transistor formation region Rp using the p-type gate formation portion 106b and the first and second sidewalls 109b and 110b as masks. P-type source / drain regions 111b are formed by ion implantation under conditions of ² keV and an implantation dose of 1 × 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 9C, a 10 nm thick metal film made of nickel is formed on the entire surface of the semiconductor substrate 101. Subsequently, a heat treatment is performed on the semiconductor substrate 101 at 500 ° C. for about 20 seconds to cause the metal and silicon to react, so that the n-type source / drain region 111a and the p-type source / drain region 111b are formed. The silicide films 112a and 112b are selectively formed. Thereafter, the unreacted remaining metal film is selectively removed.

  Next, as shown in FIG. 9D, an etching stop film 113 made of a silicon nitride film and having a thickness of 30 nm is formed on the entire surface of the semiconductor substrate 101.

  Next, as shown in FIG. 10A, an interlayer insulating film 114 made of a silicon oxide film and having a thickness of 300 nm is formed on the etching stop film 113. Subsequently, the interlayer insulating film 114 and the etching stop film 13 are polished and removed by CMP until the surfaces of the gate forming silicon films 104a and 104b are exposed, thereby planarizing the surfaces.

  Next, as shown in FIG. 10B, a 100 nm thick metal film (not shown) made of nickel is formed on the entire surface of the semiconductor substrate 101. Subsequently, the semiconductor substrate 101 is subjected to a heat treatment, for example, in a nitrogen atmosphere at a temperature of 400 ° C., so that the silicon of the gate forming silicon films 104a and 104b reacts with the metal in contact with the silicon. The gate forming silicon films 104a and 104b are fully silicided (FUSI) to form full silicide gate electrodes 104A and 104B. Full silicide gate electrodes 104A and 104B formed in this way have tensile internal stress.

  Next, as shown in FIG. 10C, a silicon oxide film is formed on the entire surface of the semiconductor substrate 101 including the n-type gate forming portion 106a and the p-type gate forming portion 106b by using a CVD method having excellent coverage. An interlayer insulating film 117 having a thickness of 200 nm is formed. Subsequently, by sequentially etching the interlayer insulating film 117, the interlayer insulating film 114, and the etching stop film 113, the contact hole 118a reaching the silicide film 112a on the n-type source / drain region 111a in the n-type MIS transistor formation region Rn. Then, a contact hole 118b reaching the silicide film 112b on the p-type source / drain region 111b of the p-type MIS transistor formation region Rp is formed.

Next, as shown in FIG. 10D, after a metal film made of tungsten is formed on the interlayer insulating film 117 including the contact holes 118a and 118b, the CMP is performed on the interlayer insulating film 117 in the metal film. These portions are polished and removed to form contact plugs 119a and 119b in the contact holes 118a and 118b. Subsequently, a metal film having a thickness of 100 nm made of Al is formed on the interlayer insulating film 117 including the contact plugs 119a and 119b, and then the metal film is patterned to form a metal wiring connected to the contact plugs 119a and 119b. 120 is formed. (See, for example, Patent Document 1)
JP 2004-79757 A

  By the way, when the metal gate electrode is formed as in the conventional method of manufacturing a semiconductor device described above, for example, the thermal expansion coefficient of the metal is larger than the thermal expansion coefficient of the semiconductor. It will have a large internal stress that tends to shrink toward it. For this reason, stress is applied to the peripheral material of the gate electrode. When stress is applied to the carrier moving region in the semiconductor element, depending on the type of carrier, the mobility of the carrier may decrease depending on the direction of the applied stress, and the electrical characteristics of the semiconductor element deteriorate. There is a problem that it ends up.

  In the case of a field effect type semiconductor device, the region immediately below the gate insulating film formed under the gate electrode is a channel region where carriers flow, so the influence of the tensile internal stress of the metal gate electrode is particularly problematic. Become. In the case of a field effect semiconductor element, as described in the above-described conventional example, when forming a gate electrode made of metal, an insulating film serving as a sidewall is in contact with the left and right sides of the region where the gate electrode is formed. Furthermore, a gate insulating film is provided below the region where the gate electrode is formed. Therefore, when attempting to shrink after the formation of the metal gate electrode, the tensile internal stress of the metal gate electrode is applied to the peripheral material, so that the channel region located immediately below the gate insulating film is laterally moved. While compressive stress works, tensile stress works in the vertical direction of the channel region. In this case, considering the influence on the mobility of carriers flowing in the left and right direction of the channel region, for example, when electrons move in the <110> crystal axis direction in the (100) substrate, or <100 in the (100) substrate When electrons move in the direction of the crystal axis of 100>, the electron mobility decreases. In addition, when holes move in the <110> crystal axis direction in the (100) substrate, the hole mobility is improved, and in the case where the holes move in the <100> crystal axis direction in the (100) substrate, Mobility is hardly affected. As described above, the tensile internal stress of the metal gate electrode is applied to the peripheral material, which affects the mobility of carriers flowing in the left-right direction of the channel region.

  In view of the foregoing, it is an object of the present invention to provide a semiconductor device having a structure capable of relieving stress applied to a peripheral material by a metal gate electrode and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a first gate insulating film formed on a semiconductor substrate and a first gate insulating film formed on the first gate insulating film. A metal gate electrode; a first impurity diffusion region formed in a region located on a side of the first metal gate in the semiconductor substrate; and a first sidewall formed on a side surface of the first metal gate electrode And a structure for reducing internal stress of the first metal gate electrode between the first metal gate electrode and the first sidewall. The stress relieving part which has is formed.

  According to the semiconductor device of one aspect of the present invention, the stress relief portion having a structure for reducing the internal stress of the first metal gate electrode is formed on the side surface of the first metal gate electrode. The tensile internal stress of the first metal gate electrode can be reduced. As a result, stress applied to the peripheral material by the metal gate electrode can be relieved, so that the mobility of carriers flowing in the channel region in the n-channel MIS transistor is improved, and a semiconductor device having excellent electrical characteristics is provided. Can do.

  In the semiconductor device according to one aspect of the present invention, the stress relieving portion is formed on the semiconductor substrate, and the first insulating film formed by a portion remaining after the insulating film is removed by etching and the first insulating film exposed by etching. It is preferable that the upper surface of one insulating film is a bottom portion and has a gap portion surrounded by the first metal gate electrode and the first sidewall.

  As described above, the stress mitigating portion includes the first insulating film formed of the portion that remains after the insulating film is removed by etching, so that the tensile internal stress of the metal gate electrode can be reduced when the etching is removed. Can be reduced. Further, since the gap is above the first insulating film and air exists on the side surface of the metal gate electrode, the tensile internal stress of the metal gate electrode is further reduced.

  In the semiconductor device according to one aspect of the present invention, the stress relieving portion is formed on the semiconductor substrate, and the first insulating film formed by a portion remaining after the insulating film is removed by etching and the first insulating film exposed by etching. And a second insulating film formed on the upper surface of the first insulating film.

  As described above, the stress mitigating portion includes the first insulating film formed of the portion that remains after the insulating film is removed by etching, so that the tensile internal stress of the metal gate electrode can be reduced when the etching is removed. Can be reduced.

  In the semiconductor device according to one aspect of the present invention, the third insulating film is sidewall-insulated between the stress relaxation portion and the first metal gate electrode or between the stress relaxation portion and the first metal gate electrode. It may be a structure further formed as a film.

  In the semiconductor device according to one aspect of the present invention, the stress relaxation portion and the third insulating film may form a sidewall insulating film having an L-shaped or I-shaped cross section.

  In the semiconductor device according to one aspect of the present invention, a second gate insulating film formed on the semiconductor substrate, a second metal gate electrode formed on the second gate insulating film, and the semiconductor substrate A p-channel MIS transistor having a second impurity diffusion region formed in a region located on the side of the second metal gate and a second sidewall formed on the side surface of the second metal gate electrode It is preferable that a structure that does not have a structure that reduces the internal stress of the second metal gate electrode is provided between the second sidewall and the second metal gate electrode.

  As described above, the p-channel type MIS transistor has a configuration in which the tensile internal stress of the metal gate electrode is not reduced. Therefore, the n-channel type MIS transistor and the p-channel type MIS transistor are formed on the same semiconductor substrate 1. Thus, a semiconductor device having excellent electrical characteristics can be realized.

  In the semiconductor device according to one aspect of the present invention, the metal gate electrode is preferably configured to be a fully silicided gate electrode or a metal gate electrode embedded with metal.

  A method for manufacturing a semiconductor device according to a first aspect of the present invention is a method for manufacturing a semiconductor device having an n-channel type MIS transistor disposed in an n-type semiconductor formation region partitioned by element isolation in a semiconductor substrate, A first gate insulating film and a first gate silicon film are sequentially formed on a semiconductor substrate, and the first gate insulating film and the first gate silicon film are patterned to thereby form a first gate insulating film. Forming a first gate electrode forming film comprising a film and a first gate silicon film, forming a first insulating film on a side surface of the first gate electrode forming film, and a first insulation Forming a first sidewall on a side surface of the film, and a first gate electrode formation film on which the first insulating film and the first sidewall are formed as a mask on the semiconductor substrate; A step of forming a first metal gate electrode by performing a predetermined process on the first gate electrode formation film after the step of forming the impurity layer, the step of forming the first impurity, By etching the first insulating film existing between the first metal gate electrode and the first side wall, the first insulating film is etched between the first metal gate electrode and the first side wall. Forming a first recess that exposes the upper surface of the remaining portion of the insulating film etched.

  According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, the portion of the first insulating film remaining after etching is left between the first metal gate electrode and the first sidewall. Since the first concave portion exposing the upper surface is formed and the first insulating film in contact with the first metal gate electrode is partially removed, the first metal generated at the time of forming the first metal gate electrode The tensile internal stress of the gate electrode can be reduced. As a result, stress applied to the peripheral material by the metal gate electrode can be relieved, so that the mobility of carriers flowing in the channel region in the n-channel MIS transistor is improved, and a semiconductor device having excellent electrical characteristics is provided. Can do.

  The method for manufacturing a semiconductor device according to the first aspect of the present invention further includes a step of depositing an insulating film so that a gap is formed in the first recess after the step of forming the first recess. As a result, the first recess on the first insulating film becomes a gap, and air exists on the side surface of the metal gate electrode, so that the tensile internal stress of the metal gate electrode is further reduced.

  A method of manufacturing a semiconductor device according to a second aspect of the present invention includes an n-channel MIS transistor disposed in an n-type semiconductor formation region partitioned by element isolation in a semiconductor substrate, and an element isolation in the semiconductor substrate. A method of manufacturing a semiconductor device having a p-channel type MIS transistor disposed in a p-type semiconductor formation region, wherein a gate insulating film and a gate silicon film are sequentially formed on a semiconductor substrate, and the gate insulating film and the gate use film are formed. By patterning the silicon film, a first gate electrode forming film made of a gate insulating film and a gate silicon film is formed in the n-type semiconductor forming region, and a gate insulating film and gate gate are formed in the p-type semiconductor forming region. A step of forming a second gate electrode formation film made of a silicon film, and a side surface of the first gate electrode formation film; Forming a first insulating film, forming a second insulating film on the side surface of the second gate electrode formation film, forming a first sidewall on the side surface of the first insulating film; The step of forming the second sidewall on the side surface of the second insulating film, and the n-type using the first insulating film and the first gate electrode forming film on which the first sidewall is formed as a mask The step of forming the first impurity layer in the semiconductor formation region and the second gate electrode formation film in which the second insulating film and the second sidewall are formed are used as a mask to form the second impurity in the p-type semiconductor formation region. After the step of forming the impurity layer and the step of forming the first impurity and the second impurity, a predetermined treatment is performed on the first gate electrode formation film and the second gate electrode formation film, First metal gate electrode and second metal gate electrode The first insulating film existing between the first metal gate electrode and the first sidewall is removed by the step of forming and etching process, and the first insulating film is etched and remains. Forming a first recess exposing the upper surface of the exposed portion, and removing the second insulating film existing between the second metal gate electrode and the second sidewall. .

  According to the method for manufacturing a semiconductor device according to the second aspect of the present invention, in the n-channel MIS transistor, the first insulating film formed on the side surface of the metal gate electrode is etched to form the first recess. Thus, the tensile internal stress of the metal gate electrode is released, and in the p-channel type MIS transistor, the tensile internal stress of the metal gate electrode is not released, so that the n-channel type MIS is formed on the same semiconductor substrate 1. A semiconductor device having excellent electrical characteristics in which a transistor and a p-channel MIS transistor are formed can be realized.

  In the method for manufacturing a semiconductor device according to the first and second aspects of the present invention, a step of depositing an insulating film so that a gap is formed in the first recess after the step of forming the first recess. Furthermore, since the first recess on the first insulating film becomes a gap and air exists on the side surface of the metal gate electrode, the tensile internal stress of the metal gate electrode is further reduced.

  In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the method further includes a step of embedding an insulating film in the first recess after the step of forming the first recess. A configuration in which an insulating film is embedded in the recess may be used.

  In the method for manufacturing a semiconductor device according to the first and second aspects of the present invention, the step of forming the first metal gate electrode includes forming the metal film on the first gate electrode formation film, A step of forming a first metal gate electrode in which the first gate silicon film is fully silicided may be performed by performing a heat treatment.

  In the method of manufacturing a semiconductor device according to the first and second aspects of the present invention, the step of forming the first metal gate electrode includes removing the first gate silicon film to form the upper surface of the gate insulating film. A step of forming a first metal gate electrode in which a metal is embedded by embedding a metal in the second recess after forming the exposed second recess.

  In the method for manufacturing a semiconductor device according to the first and second aspects of the present invention, after the step of forming the first gate electrode formation film and before the step of forming the first insulating film. The semiconductor device may further include a step of forming a first extension diffusion layer on the side of the first gate electrode formation film in the semiconductor substrate using the first gate electrode formation film as a mask.

  According to the method for manufacturing a semiconductor device of the present invention, stress on the peripheral material generated by the metal gate electrode can be relaxed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, a p-type well region 1a and an n-type well region 1b separated from each other by element isolation 2 are formed on a semiconductor substrate 1 made of, for example, silicon. The p-type well region 1a is a region in which a p-type impurity (for example, boron) is ion-implanted into the semiconductor substrate 1 in the n-type MIS transistor formation region Rn, and the n-type well region 1b is a p-type MIS transistor formation. This is a region formed by ion implantation of an n-type impurity (for example, arsenic) in the region Rp. On the semiconductor substrate 1 in the p-type well region 1a, a gate insulating film 3a formed in order from the bottom and a full silicide gate electrode 4A made of a polysilicon film are formed. Further, on the semiconductor substrate 1 in the n-type well region 1b, a gate insulating film 3b formed in order from the bottom and a full silicide gate electrode 4B made of a polysilicon film are formed.

  In the n-type MIS transistor formation region Rn, an n-type source / drain region 11a formed by implanting n-type impurity ions is formed in the p-type well region 1a. The n-type source / drain region 11a is formed in a lower region on the side of the gate insulating film 3a and the full silicide gate electrode 4A, and an n-type extension region having a relatively shallow junction depth formed by ion implantation of n-type impurities. 7a and a p-type pocket region 8a formed under the n-type extension region 7a.

  On the other hand, in the p-type MIS transistor formation region Rp, a p-type source / drain region 11b formed by implanting p-type impurity ions is formed in the n-type well region 1b. The p-type source / drain region 11b is formed in the lower region of the side surfaces of the gate insulating film 3b and the full silicide gate electrode 4B, and the p-type extension region 7b having a relatively shallow junction depth formed by ion implantation of p-type impurities. And an n-type pocket region 8b formed below the p-type extension region 7b.

  In the n-type MIS transistor formation region Rn, a first sidewall 9a having an L-shaped cross section is formed on the side surfaces of the gate insulating film 3a and the full silicide gate electrode 4A. A second sidewall 10a is formed on the bottom and side surfaces of 9a. Here, a part of the first sidewall 9a is removed by etching, and the upper end position thereof is formed lower than the upper end position of the first sidewall 9b described later. That is, a recess is once formed between the full silicide gate electrode 4A and the second sidewall 10a, and a second interlayer insulating film 17 described later is buried in the recess. Further, the upper end position of the first side wall 9a is higher than the upper surface of the gate insulating film 3a, and is preferably 1/2 or less, preferably 1/3 or less of the height of the full silicide gate electrode 4A. .

  On the other hand, in the p-type MIS transistor formation region Rp, on the side surfaces of the gate insulating film 3b and the full silicide gate electrode 4B, a first sidewall 9b having an L-shaped cross section is formed. A second sidewall 10b is formed on the bottom and side surfaces of the sidewall 9b.

  In the n-type MIS transistor formation region Rn and the p-type MIS transistor formation region Rp, the side surfaces of the first sidewalls 9a and 9b and the side surfaces of the second sidewalls 10a and 10b are covered on the semiconductor substrate 1. An etching stop film 13 is formed. A first interlayer insulating film 14 is formed on the top and side surfaces of the etching stop film 13. The second interlayer insulating film 14 is formed on the first interlayer insulating film 14, the etching stop film 13, the second sidewalls 10a and 10b, the first sidewalls 9a and 9b, and the full silicide gate electrodes 4A and 4B. A film 17 is formed. As described above, the second interlayer insulating film 17 is also embedded between the full silicide gate electrode 4A and the second sidewall 10a.

  In the first and second interlayer insulating films 14 and 17, a contact plug 19a that reaches the silicide film 12a is formed in the n-type MIS transistor formation region Rn, and in the p-type MIS transistor formation region Rp, A contact plug 19b reaching the silicide film 12b is formed. On the second interlayer insulating film 17, a metal wiring 20 connected to the upper ends of the contact plugs 19a and 19b is formed.

  The effects obtained by the structure of the semiconductor device according to the first embodiment of the present invention will be described below.

  2A is a cross-sectional view showing the n-type MIS transistor formation region Rn in the semiconductor device according to the first embodiment of the present invention. FIG. 2B is a cross-sectional view of the n-type MIS transistor formation region Rn. It is a related figure of the horizontal position (micrometer) along the cross section of the IIa-IIa line | wire of (a), and a horizontal stress (MPa).

  As is clear from FIG. 2B, in the n-type MIS transistor formation region in the first embodiment of the present invention, the full silicide gate electrode 4A is formed from the region immediately below the first and second sidewalls 9a and 10a. It can be seen that the tensile stress in the lateral direction rises compared to the conventional structure (see, for example, FIG. 10D) in the region immediately below. In particular, in the region immediately below the full silicide gate electrode 4A, the tensile stress in the lateral direction is increased by about 100 MPa as compared with the conventional structure, and when calculated from the piezoresistance effect, the n-type MIS in the <100> crystal axis direction. In the case of a transistor, the mobility of electrons moving in the channel region is improved by 5%.

  A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below.

  FIGS. 3A to 3D, FIGS. 4A to 4D, and FIGS. 5A and 5B show respective steps of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. The cross-sectional state in FIG. 3A, 4A, and 5A, the n-type MIS transistor formation region Rn and the p-type MIS, which are regions where the n-type MIS transistor is formed, are representative of the respective drawings. A p-type MIS transistor formation region Rp, which is a region where transistors are formed, is shown.

  First, as shown in FIG. 3A, an element isolation region 2 made of shallow trench isolation (STI) is formed on a semiconductor substrate 1 by a normal element isolation formation method. Thereby, the active region of the n-type MIS transistor and the active region of the p-type MIS transistor are partitioned. Subsequently, a p-type impurity is ion-implanted in the semiconductor substrate 1 in the n-type MIS transistor formation region Rn to form a p-type well region 1a, while an n-type impurity is added in the semiconductor substrate 1 in the p-type MIS transistor formation region Rp. Are ion-implanted to form an n-type well region 1b.

  Subsequently, a gate oxide film to be a gate insulating film, a polysilicon film to be a gate forming silicon film, and a protective oxide film to be a protective insulating film are sequentially formed on the semiconductor substrate 1. Subsequently, by using a lithography technique and anisotropic dry etching, the protective oxide film, the polysilicon film, and the gate oxide film are sequentially etched, whereby the gate insulating films 3a and 3b, the gate forming silicon films 4a and 4b, and Protective insulating films 5a and 5b are formed. As a result, an n-type gate forming portion 6a including the gate insulating film 3a, the gate forming silicon film 4a, and the protective insulating film 5a is formed on the semiconductor substrate 1 in the n-type MIS transistor forming region Rn, and the p-type is formed. On the semiconductor substrate 1 in the MIS transistor formation region Rp, a p-type gate forming portion 6b including a gate insulating film 3b, a gate forming silicon film 4b, and a protective insulating film 5b is formed.

  Subsequently, by using the n-type gate forming portion 6a as a mask, an n-type impurity is ion-implanted into the semiconductor substrate 1 in the n-type MIS transistor forming region Rn, thereby forming an n-type extension region 7a. A p-type pocket region 8a is formed by ion-implanting p-type impurities into the semiconductor substrate 1 in the n-type MIS transistor formation region Rn using the gate formation portion 6a as a mask. Further, by using the p-type gate forming portion 6b as a mask, p-type impurities are ion-implanted into the semiconductor substrate 1 in the p-type MIS transistor forming region Rp, thereby forming a p-type extension region 7a. An n-type pocket region 8b is formed by ion-implanting n-type impurities into the semiconductor substrate 1 in the p-type MIS transistor formation region Rp using the formation portion 6b as a mask.

  Next, as shown in FIG. 3B, a first insulating film made of a silicon oxide film having a thickness of 20 nm and a second insulating film made of a silicon nitride film having a thickness of 50 nm are formed on the entire surface of the semiconductor substrate 1. A film is sequentially formed. Thereafter, by sequentially etching back the second insulating film and the first insulating film, the cross-sectional shape made of the first insulating film is formed on each side surface of the n-type gate forming portion 6a and the p-type gate forming portion 6b. L-shaped first sidewalls 9a and 9b and second sidewalls 10a and 10b made of a second insulating film are formed on the first sidewalls 9a and 9b.

Subsequently, arsenic ions, which are n-type impurities, are implanted into the semiconductor substrate 1 in the n-type MIS transistor formation region Rn using the n-type gate forming portion 6a and the sidewalls 9a and 10a as masks. The n-type source / drain region 11a is formed by ion implantation under the condition of an implantation dose of 1 × 10 ¹⁵ / cm ² . Further, boron ions, which are p-type impurities, are implanted into the semiconductor substrate 1 in the p-type MIS transistor formation region Rp using the p-type gate forming portion 6b and the sidewalls 9b and 10b as masks, and the implantation energy is 2 keV. P-type source / drain regions 11b are formed by ion implantation under the condition of a dose of 1 × 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 3C, a 10 nm thick metal film made of nickel is formed on the entire surface of the semiconductor substrate 1. Subsequently, the semiconductor substrate 1 is subjected to a heat treatment at 500 ° C. for about 20 seconds to cause the metal and silicon to react, thereby forming a silicide film on the n-type source / drain region 11a and the p-type source / drain region 11b. 12a and 12b are selectively formed. Thereafter, the unreacted remaining metal film is selectively removed.

  Next, as shown in FIG. 3D, an etching stop film 13 made of a silicon nitride film and having a thickness of 30 nm is formed on the entire surface of the semiconductor substrate 1.

  Next, as shown in FIG. 4A, a 300 nm-thick first interlayer insulating film 14 made of a silicon oxide film is formed on the etching stop film 13. Subsequently, the first interlayer insulating film 14 and the etching stop film 13 are polished and removed by CMP until the surfaces of the gate forming silicon films 4a and 4b are exposed, thereby planarizing the surfaces. . However, in this step, after polishing and removing until the protective insulating films 5a and 5b are exposed by CMP, the protective insulating films 5a and 5b may be etched to expose the gate forming silicon films 4a and 4b. Thereafter, the gate forming silicon films 4a and 4b may be etched by a desired thickness. In this case, for example, the thickness of the gate forming silicon film 4a is 80 nm, and the thickness of the gate forming silicon film 4b is 40 nm.

  Next, as shown in FIG. 4B, a 100 nm thick metal film (not shown) made of nickel is formed on the entire surface of the semiconductor substrate 1. Subsequently, the semiconductor substrate 1 is subjected to a heat treatment, for example, in a nitrogen atmosphere at a temperature of 400 ° C., so that the silicon of the gate forming silicon films 4a and 4b and the metal in contact with the silicon react with each other. The gate forming silicon films 4a and 4b are converted into full silicide (FUSI) to form full silicide gate electrodes 4A and 4B. The full silicide gate electrodes 4A and 4B thus formed have tensile internal stress.

Next, as illustrated in FIG. 4C, a resist 15 having an opening pattern that exposes the n-type gate forming portion 6 a and covers the p-type gate forming portion 6 b is formed on the interlayer insulating film 14. Thereafter, the resist 15 is used as a mask, and is interposed between the full silicide gate electrode 4A and the second sidewall 10a by dry etching using, for example, CF ₄ gas etching or wet etching using a hydrofluoric acid solution. The first sidewall 9a is removed. At this time, the upper end position of the first sidewall 9a after the etching is higher than the upper surface of the gate insulating film 3a, and is 1/2 or less, preferably 1/3 or less of the height of the full silicide gate electrode 4A. To do. Thereby, a recess 16 is formed between the full silicide gate electrode 4A and the second sidewall 10a. As described above, by etching the first sidewall 9a to form the recess 16, the tensile internal stress of the full silicide gate electrode 4A is released and reduced.

  Next, as shown in FIG. 4D, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 including the n-type gate forming portion 6a and the p-type gate forming portion 6b by using a CVD method having excellent coverage. A second interlayer insulating film 17 having a thickness of 200 nm is formed. At this time, the second interlayer insulating film 17 is also buried in the recess 16 formed between the full silicide gate electrode 4A and the second sidewall 10a.

  Next, as shown in FIG. 5A, the second interlayer insulating film 17, the first interlayer insulating film 14, and the etching stop film 13 are sequentially etched, so that the n-type of the n-type MIS transistor formation region Rn is obtained. A contact hole 18a reaching the silicide film 12a on the source / drain region 11a and a contact hole 18b reaching the silicide film 12b on the p-type source / drain region 11b of the p-type MIS transistor formation region Rp are formed.

  Next, as shown in FIG. 5B, after a metal film made of tungsten is formed on the second interlayer insulating film 17 including the contact holes 18a and 18b, the second film in the metal film is formed by CMP. By polishing and removing the portion on the interlayer insulating film 17, contact plugs 19a and 19b are formed in the contact holes 18a and 18b. Subsequently, after forming a 100 nm-thick metal film made of Al on the second interlayer insulating film 17 including the contact plugs 19a and 19b, the metal film is patterned to be connected to the contact plugs 19a and 19b. The metal wiring 20 to be formed is formed.

  As described above, according to the manufacturing method according to the first embodiment of the present invention, in the n-type MIS transistor formation region Rp, the tensile internal stress of the full silicide gate electrode 4A is released, while the p-type MIS transistor formation is performed. In the region Rp, the full silicide gate electrode 4B still has tensile internal stress. Here, the mobility of holes or electrons serving as carriers increases or decreases according to the direction of tensile internal stress from the metal gate electrode applied to the channel. For example, when carriers flow in the <110> direction or <100> direction in the (100) substrate, if the hole is a hole, the mobility is improved when the tensile internal stress of the gate electrode is applied to the peripheral material, In the case of electrons, the mobility is improved when the internal stress of the gate electrode is not applied to the surrounding material. Therefore, in the present embodiment, the p-type MIS transistor formation region Rp is configured not to release the tensile internal stress of the full silicide gate electrode 4B, and the n-type MIS transistor formation region Rn has a tensile force of the full silicide gate electrode 4A. If the internal stress is released, a semiconductor device having excellent electrical characteristics in which an n-type MIS transistor and a p-type MIS transistor are formed on the same semiconductor substrate 1 can be realized.

  When the temperature in the deposition condition when the material is embedded in the recess 16 is higher than the heat treatment temperature at the time of silicide formation, the full silicide gate electrode 4A once released from the tensile internal stress is re-stretched after the heat treatment. Therefore, it is desirable that the temperature under the deposition conditions when the material is embedded in the recess 16 (here, when the second interlayer insulating film 17 is deposited) is lower than the heat treatment temperature at the time of silicide formation.

--Modification of the first embodiment--
Hereinafter, modifications of the semiconductor device manufacturing method according to the first embodiment of the present invention will be described.

  6A to 6C show the cross-sectional states in the respective steps in the modification of the method for manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. In each step of the method for manufacturing a semiconductor device according to this modification, the description of the same steps as those for the method for manufacturing the semiconductor device according to the first embodiment of the present invention described above will be omitted, and the following will mainly differ. The process will be described. In FIG. 6A, the n-type MIS transistor formation region Rn, which is a region where an n-type MIS transistor is formed, and a p-type MIS transistor, which is a region where a p-type MIS transistor is formed, on behalf of each figure The formation region Rp is shown.

  First, the steps shown in FIG. 6A are performed in the same manner as described with reference to FIGS. 3A to 3D and FIGS. 4A to 4C in the first embodiment. Then, the structure shown in FIG. 6A shows a state after the resist 15 shown in FIG. 4C is removed after the recess 16 is formed.

  Next, as shown in FIG. 6B, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 including the n-type gate forming portion 6a and the p-type gate forming portion 6b by using a CVD method with poor coverage. A second interlayer insulating film 17 having a thickness of 200 nm is formed. At this time, since the coverage of the second interlayer insulating film 17 is poor, the second interlayer insulating film 17 is not completely embedded in the recess 16, so that a gap 16 </ b> A is formed.

  In the subsequent steps, the configuration shown in FIG. 6C can be obtained by performing the same steps as described with reference to FIGS. 5A and 5B.

  According to the modification of the method of manufacturing the semiconductor device according to the first embodiment of the present invention, the first embodiment is obtained by removing the first sidewall 9a formed on the side surface of the full silicide gate electrode 4A. In addition to the effects obtained, the following effects are obtained. A gap 16A (void) is formed on the side surface of the full silicide gate electrode 4a in the present embodiment, and air exists in the gap. Therefore, the tensile internal stress of the full silicide gate electrode 4A. Will always be open. Here, when the material is embedded in the recess 16, depending on the material, a material that originally has a tensile internal stress applied to the channel may be embedded, but according to the modification of the present embodiment, By forming the gap 16A, it is possible to realize a configuration in which the tensile internal stress of the full silicide gate electrode 4A is reliably released and a tensile stress applied to the channel is not newly generated.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below.

  FIGS. 7A to 7D and FIG. 8A show the cross-sectional states in each step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps, and FIG. ) Shows a cross-sectional view for explaining a modification of the semiconductor device manufacturing method according to the second embodiment of the present invention. Note that, in each step of the semiconductor device manufacturing method according to the second embodiment of the present invention, a part of the description of the same steps as those of the semiconductor device manufacturing method according to the first embodiment of the present invention is omitted. Yes. In FIGS. 7A and 8A, the n-type MIS transistor formation region Rn and the p-type MIS transistor are formed, which are regions where the n-type MIS transistor is formed, on behalf of the respective drawings. P-type MIS transistor formation region Rp. .

  First, the steps shown in FIG. 7A are performed in the same manner as described with reference to FIGS. 3A to 3D and FIG. The structure shown in a) is obtained.

  Next, as shown in FIG. 7B, after the gate forming silicon films 4a and 4b are selectively removed by wet etching using, for example, a KOH solution, a metal film (on the entire surface of the semiconductor substrate 1 is formed). (Not shown). Subsequently, the portion of the metal film existing on the first interlayer insulating film 14 is removed by CMP to remove the gate forming silicon films 4a and 4b, thereby removing the gate in the recess formed. Metal gate electrodes 21a and 21b are formed on insulating films 3a and 3b.

Next, as shown in FIG. 7C, a resist 15 having an opening pattern that exposes the n-type gate forming portion 6a and covers the p-type gate forming portion 6b is formed on the first interlayer insulating film. . Thereafter, the resist 15 is used as a mask, and is interposed between the metal gate electrode 21a and the second sidewall 10a by dry etching using etching such as CF ₄ gas or wet etching using a hydrofluoric acid solution. The first side wall 9a is removed. At this time, the upper end position of the first sidewall 9a after the etching is higher than the upper surface of the gate insulating film 3a, and is 1/2 or less, preferably 1/3 or less of the height of the metal gate electrode 21a. . Thereby, the recess 16 is formed between the metal gate electrode 21a and the second sidewall 10a. In this way, by etching the first sidewall 9a to form the recess 16, the tensile internal stress of the metal gate electrode 21a is released and reduced.

  Next, as shown in FIG. 7D, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 including the n-type gate forming portion 6a and the p-type gate forming portion 6b by using a CVD method having excellent coverage. A second interlayer insulating film 17 having a thickness of 200 nm is formed. At this time, the second interlayer insulating film 17 is also embedded in the recess 16 formed between the metal gate electrode 21a and the second sidewall 10a.

  Next, as shown in FIG. 8A, the second interlayer insulating film 17, the first interlayer insulating film 14, and the etching stop film 13 are sequentially etched, so that the n-type of the n-type MIS transistor formation region Rn is obtained. A contact hole 18a reaching the silicide film 12a on the source / drain region 11a and a contact hole 18b reaching the silicide film 12b on the p-type source / drain region 11b of the p-type MIS transistor formation region Rp are formed. Subsequently, after a metal film made of tungsten is formed on the second interlayer insulating film 17 including the contact holes 18a and 18b, a portion of the metal film on the second interlayer insulating film 17 is polished by CMP. By removing, contact plugs 19a and 19b are formed in the contact holes 18a and 18b. Subsequently, after forming a 100 nm-thick metal film made of Al on the second interlayer insulating film 17 including the contact plugs 19a and 19b, the metal film is patterned to be connected to the contact plugs 19a and 19b. The metal wiring 20 to be formed is formed.

  As described above, according to the manufacturing method according to the second embodiment of the present invention, in the n-type MIS transistor formation region Rp, the tensile internal stress of the metal gate electrode 21a is released, while the p-type MIS transistor formation region. In Rp, the metal gate electrode 21b has a tensile internal stress. For this reason, in the present embodiment, in the p-type MIS transistor formation region Rp, the tensile internal stress of the metal gate electrode 21b is not released, and in the n-type MIS transistor formation region Rn, the tensile internal stress of the metal gate electrode 21a. If the structure is opened, a semiconductor device having excellent electrical characteristics in which an n-type MIS transistor and a p-type MIS transistor are formed on the same semiconductor substrate 1 is realized for the same reason as in the first embodiment. can do.

  Note that it is desirable that the temperature under the deposition conditions when the material is embedded in the recess 16 (here, when depositing the second interlayer insulating film 17) is lower than the heat treatment temperature during silicide formation. This is the same as the embodiment.

  In the second embodiment described above, the case where the metal gate electrodes 21a and 21b are formed instead of the full silicide gate electrodes 4A and 4B in the first embodiment described above has been described. However, it goes without saying that the present invention can be similarly implemented even when a modification similar to the modification of the first embodiment is configured. That is, after the process shown in FIG. 7C described above, by performing the same as the description using FIGS. 6B and 6C in the modification of the first embodiment, FIG. As shown in FIG. 6, the structure in the case where the gate electrodes are the metal gate electrodes 21a and 21b and the void 16A is formed on the side surface thereof can be realized. In addition, it cannot be overemphasized that the effect in the case of this structure is the same as the effect described in the modification of 1st Embodiment.

  In each of the embodiments described above, the first sidewall (9a, 9b) having an L-shaped cross-section on the side surfaces of the gate insulating films (3a, 3b) and the gate electrodes (4a, 4b), and the first The case where the second sidewalls (10a, 10b) are formed has been described, but the first sidewalls (9a, 9b), the gate insulating films (3a, 3b), and the gate electrodes (4a, 4b) are formed. A configuration in which an offset spacer having an I-shaped cross section may be formed. At this time, the tensile internal stress of the metal gate electrode may be released by removing the upper portion of the offset spacer in the n-type MIS transistor formation region Rn to form a recess. In this case, the n-type MIS transistor formation region It is not always necessary to form the recess 16 by removing the upper portion of the first sidewall (9a) in Rn, and the first sidewall (9a, 9b) may not be provided.

  As described above, the present invention is useful for a semiconductor device having a structure that can relieve stress when forming a metal gate electrode, a manufacturing method thereof, and the like.

It is sectional drawing which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention. (A) is sectional drawing which showed the structure of the n-type MIS transistor formation area | region in the semiconductor device based on the 1st Embodiment of this invention. (B) is a stress distribution diagram along the IIa-IIa line shown in (a). (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A) And (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A)-(c) is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (A) is sectional drawing which shows the structure of the semiconductor device formed by the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is based on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device formed by the modification of the manufacturing method of a semiconductor device. (A)-(d) is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. (A)-(d) is sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Active region 1b of n-type MIS transistor Active region 2 of p-type MIS transistor 2 Element isolation region 3a, 3b Gate insulating film 4a, 4b Gate forming silicon film 5a, 5b Protective insulating film 6a N-type gate forming portion 6b p-type gate forming portion 7a n-type extension region 7b p-type extension region 8a p-type pocket region 8b n-type pocket regions 9a and 9b first side walls 10a and 10b second side walls 11a n-type source / drain regions 11b p Type source / drain regions 12a, 12b silicide film 13 etching stop film 14 first interlayer insulating film 15 resist 16 recess 16A gap (void)
17 Second interlayer insulating film 18a, 18b Contact hole 19a, 19b Contact plug 20 Metal wiring 21a, 21b Metal gate electrode Rn n-type MIS transistor formation region Rp p-type MIS transistor formation region

Claims (19)

A first gate insulating film formed on the semiconductor substrate; a first metal gate electrode formed on the first gate insulating film; and a side of the first metal gate in the semiconductor substrate. A semiconductor device including an n-channel MIS transistor having a first impurity diffusion region formed in a region located at a first side wall and a first sidewall formed on a side surface of the first metal gate electrode. And
A stress relaxation portion having a structure for reducing internal stress of the first metal gate electrode is formed between the first metal gate electrode and the first sidewall. Semiconductor device. The stress relieving part
A first insulating film formed on the semiconductor substrate, the first insulating film comprising a portion remaining after the insulating film is removed by etching;
A top portion of the first insulating film exposed by the etching is a bottom portion, and a gap portion surrounded by the first metal gate electrode and the first sidewall is provided. The semiconductor device according to claim 1. The stress relieving part
A first insulating film formed on the semiconductor substrate, the first insulating film comprising a portion remaining after the insulating film is removed by etching;
The semiconductor device according to claim 1, further comprising: a second insulating film formed on an upper surface of the first insulating film exposed by the etching.   A third insulating film is further formed between the stress relieving part and the first metal gate electrode or between the stress relieving part and the first metal gate electrode. The semiconductor device according to claim 1.   The semiconductor device according to claim 4, wherein a shape of a cross section constituted by the stress relieving portion and the third insulating film is L-shaped or I-shaped. A second gate insulating film formed on the semiconductor substrate; a second metal gate electrode formed on the second gate insulating film; and the second metal gate side of the semiconductor substrate. A p-channel MIS transistor having a second impurity diffusion region formed in a region located on the side and a second sidewall formed on a side surface of the second metal gate electrode,
The structure between the second sidewall and the second metal gate electrode does not have a structure for reducing the internal stress of the second metal gate electrode. The semiconductor device according to any one of 1 to 5.   The semiconductor device according to claim 1, wherein the metal gate electrode is a fully silicided gate electrode or a metal gate electrode embedded with metal. A method for manufacturing a semiconductor device having an n-channel MIS transistor disposed in an n-type semiconductor formation region partitioned by element isolation in a semiconductor substrate,
A first gate insulating film and a first gate silicon film are sequentially formed on the semiconductor substrate, and the first gate insulating film and the first gate silicon film are patterned, whereby the first gate insulating film and the first gate silicon film are patterned. Forming a first gate electrode formation film comprising a first gate insulating film and the first gate silicon film;
Forming a first insulating film on a side surface of the first gate electrode formation film;
Forming a first sidewall on a side surface of the first insulating film;
Forming a first impurity layer on the semiconductor substrate using the first gate electrode formation film on which the first insulating film and the first sidewall are formed as a mask;
After the step of forming the first impurity, performing a predetermined treatment on the first gate electrode formation film to form a first metal gate electrode;
By etching the first insulating film existing between the first metal gate electrode and the first sidewall, the first metal gate electrode and the first sidewall are And a step of forming a first recess that exposes an upper surface of a portion remaining after the first insulating film is etched. A method for manufacturing a semiconductor device, comprising: The method further comprises depositing an insulating film on the first metal gate electrode after the step of forming the recess so that a gap is formed in the first recess. Item 9. A method for manufacturing a semiconductor device according to Item 8. 9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of embedding an insulating film in the first recess after the step of forming the first recess. The step of forming the first metal gate electrode includes forming a metal film on the first gate electrode formation film, and then performing a heat treatment on the metal film to thereby form the first gate silicon. 11. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming the first metal gate electrode in which the film is fully silicided.   The step of forming the first metal gate electrode includes removing the first gate silicon film to form a second recess that exposes the upper surface of the gate insulating film, and then forming the second recess. 11. The semiconductor device according to claim 8, comprising a step of forming the first metal gate electrode in which the metal is embedded by embedding a metal in the semiconductor device. 11. Production method. After the step of forming the first gate electrode formation film and before the step of forming the first insulating film,
9. The method according to claim 8, further comprising a step of forming a first extension diffusion layer on a side of the first gate electrode formation film in the semiconductor substrate using the first gate electrode formation film as a mask. 12. A method of manufacturing a semiconductor device according to claim 1. An n-channel MIS transistor disposed in an n-type semiconductor formation region partitioned by element isolation in a semiconductor substrate, and a p-channel MIS transistor disposed in a p-type semiconductor formation region partitioned by the element isolation in the semiconductor substrate A method of manufacturing a semiconductor device comprising:
A gate insulating film and a gate silicon film are sequentially formed on the semiconductor substrate, and the gate insulating film and the gate silicon film are patterned to form the gate insulating film and the gate in the n-type semiconductor formation region. Forming a first gate electrode forming film made of a silicon film for forming, and forming a second gate electrode forming film made of the gate insulating film and the gate silicon film in the p-type semiconductor forming region;
Forming a first insulating film on a side surface of the first gate electrode forming film and forming a second insulating film on a side surface of the second gate electrode forming film;
Forming a first sidewall on the side surface of the first insulating film and forming a second sidewall on the side surface of the second insulating film;
Forming a first impurity layer in the n-type semiconductor formation region using the first gate electrode formation film formed with the first insulating film and the first sidewall as a mask;
Forming a second impurity layer in the p-type semiconductor formation region, using the second gate electrode formation film formed with the second insulating film and the second sidewall as a mask;
After the step of forming the first impurity and the second impurity, a predetermined treatment is performed on the first gate electrode formation film and the second gate electrode formation film to form a first metal Forming a gate electrode and a second metal gate electrode;
By etching, the first insulating film existing between the first metal gate electrode and the first sidewall is removed, and the first insulating film is etched and remains. Forming a first recess exposing the upper surface of the portion, and not removing the second insulating film existing between the second metal gate electrode and the second sidewall. A method for manufacturing a semiconductor device, comprising: The method further comprises depositing an insulating film on the first metal gate electrode after the step of forming the recess so that a gap is formed in the first recess. Item 15. A method for manufacturing a semiconductor device according to Item 14. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of embedding an insulating film in the first recess after the step of forming the recess.   The step of forming the first metal gate electrode includes forming a metal film on the first gate electrode formation film, and then performing a heat treatment on the metal film to thereby form the first gate silicon. 17. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of forming the first metal gate electrode in which the film is fully silicided. 17.   The step of forming the first metal gate electrode includes removing the first gate silicon film to form a second recess that exposes the upper surface of the gate insulating film, and then forming the second recess. 17. The semiconductor device according to claim 14, comprising a step of forming the first metal gate electrode formed by embedding a metal in the metal. Production method. After the step of forming the first gate electrode formation film and before the step of forming the first insulating film,
15. The method of claim 14, further comprising forming a first extension diffusion layer on a side of the first gate electrode formation film in the semiconductor substrate using the first gate electrode formation film as a mask. The method for manufacturing a semiconductor device according to any one of 18.

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