JPS62114272A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a threshold voltage from varying by forming the first conductivity type high density impurity region having a impurity density higher than a substrate and a shorter width than the average free step of carrier between a drain region and a channel region to eliminate the adverse influence of impact ions. CONSTITUTION:A gate electrode 14 is formed through a gate oxide film 13 on a P-type Si substrate 11, and N<+> type layer (source, drain regions) 18a, 18b due to N-type impurity diffusion are formed outside the channel region under the electrode 14. The same conductivity type P<+> layer (high density impurity regions) 16a, 16b as the substrate 11 are formed between the regions 18a, 18b and a channel region. Here, the widths of the regions 16a, 16b are shorter than the average free step of a carrier.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to the improvement of semiconductor devices, and particularly to a semiconductor device that eliminates the influence of impact ionization in a MOS structure or the like.

[Technical background of the invention and its problems]

In recent years, MOS elements constituting integrated circuits have tended to become more and more miniaturized, and with the miniaturization of these elements, the problem of adverse effects due to impact ionization, particularly fluctuations in gate threshold voltage, has arisen. That is, when a fine MOS transistor is operated, carriers that start flowing from the source side flow into the train region while being accelerated by the electric field caused by the drain voltage. At this time, the electrons accelerated to an energy higher than the bandgap of the semiconductor become electrons.
Hole pairs are generated, but when the generated carriers are injected into the gate oxide film, the gate oxide film begins to deteriorate. If this state continued for a long time, the fluctuation of the gate threshold voltage would be affected by JB.

Therefore, recently, LDD and zero
MOS transistors with structures such as GI) are being considered. FIGS. 4 and 5 respectively show the source-drain potentials of an N-type MOS transistor with a conventional structure and an N-type MOS transistor with an LDD or DGD structure during operation.

Compared to the conventional structure shown in FIG. 4, the electric field in the DD structure shown in FIG. However, as the channel length of the device becomes shorter, the electric field strength near the drain increases even in a structure such as an LDD, and when the channel length of the device becomes about 0.5 [μTrL], there is a negative impact due to impact ionization. It is expected that this will become unavoidable.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and its purpose is to eliminate the adverse effects of impact ionization, prevent fluctuations in gate threshold voltage, improve reliability, and improve device fineness. The object of the present invention is to provide a semiconductor device that can be used in various ways.

[Summary of the invention]

The gist of the present invention is to provide an impurity region between the drain region and the channel region that has the same conductivity type as the substrate and has a higher concentration than the substrate, thereby preventing the generation of ions under the gate electrode. .

That is, the present invention provides a second sN type source/drain region in a first conductivity type semiconductor substrate with a distance of 111, and
In a semiconductor device in which a gate electrode is formed on a channel region between source and drain regions, there is a gap between the drain region and the channel region that has a higher impurity concentration than the substrate and is shorter than the mean free path of carriers. Width 1st
A conductive type high concentration impurity region is provided.

〔Effect of the invention〕

According to the present invention, carriers flowing from the source are not accelerated until they reach the high concentration impurity region between the drain region and the channel region, and are rapidly accelerated in the impurity region. Here, since the width of the high concentration impurity region is shorter than the mean free path of carriers, almost no carriers are generated in the impurity region. On the other hand, carriers that have passed through the high-concentration impurity region reach the drain, where they are generated by impact ionization, but since there is no gate masking film above this, carriers are prevented from being injected into the gate. I can do it. Therefore, a stable and highly reliable fine MOS transistor with less adverse effects caused by impact ionization can be realized, and it can be provided with practically sufficient characteristics as a circuit of a semiconductor device with an island integration degree.

[Embodiments of the invention]

Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a sectional view showing a schematic structure of a MOS transistor according to an embodiment of the present invention. 11 in the figure is P-type Si!
! A gate oxide layer 11m13 is formed on this substrate 11.
A gate 1lfi14 is formed through the gate 1lfi14. Outside the channel region under the gate electrode 14, there is an N+ layer (source/drain fitii) 18a formed by diffusion of N-type under N-type,
18b is formed. And the source faiIi1
A P'' layer (high concentration impurity region) 16a of the same conductivity type as the substrate 11 is between the drain l1ff118b and the channel region.

16b are formed respectively. Here, the width of the high concentration impurity regions 16a and 16b is shorter than the mean free path of carriers.

In such a configuration, when the MO8 element is operated, the potential distribution between the source and drain becomes as shown in FIG. That is, the potential is approximately constant directly below the gate electrode 14,
Since there is a large electric field near the train 18b, the electrons are rapidly accelerated in this vicinity and move to the drain region 1i! 1
It will flow into 8b. Here, P+ with a large electric field
The width of the type impurity region 16b is shorter than the mean free path of electrons.

Therefore, even if electrons are accelerated to an energy higher than the band gap of silicon, almost no carriers are generated in the P+ type impurity region 16b.

Furthermore, the end of the gate electrode 14 does not reach the boundary between the P+ impurity region 16b and the drain region 18b. Therefore, when accelerated electrons flow to the drain region 18b, recarriers are generated by impact ionization, but since there is no gate above this, it is possible to prevent carriers from being injected into the gate region. Therefore, a highly reliable fine MOS with extremely little fluctuation in threshold voltage
A transistor will be realized.

Next, a method for manufacturing the MOS transistor having the above structure will be described with reference to FIGS. 3(a) to 3(b).

First, as shown in FIG. 3(a), a field oxide layer 1112 for element isolation is formed on a P-type Sil plate 11, and a gate oxide layer 113 and a polycrystalline silicon layer are formed on the element formation region surrounded by this field oxide film 12. Silicon 1114 is formed. This polycrystalline silicon layer 14 is patterned to a width of 0.5 μm to form a gate electrode. Subsequently, after oxidizing the polycrystalline silicon film 14 to form oxide 1115, poron 8 is ion-implanted at an acceleration voltage of 50 [KV] to form P.
+ layers 16a and 16b are formed.

Next, as shown in FIG. 3(b), silicon oxide J was applied to the entire surface.
1117 is deposited by CVD method. After that, the entire surface was etched using reactive ion etching, as shown in Figure 3 (
As shown in C), the silicon oxide film 17 is left only on the sides of the gate electrode 14.

That is, the side 9 oxide film 17 is formed on the side of the gate electrode 14 in a self-aligned manner. In this state, the acceleration voltage is 40 [K
Arsenic As is ion-implanted at a temperature of V] to form N+ layers 18a and 18t) which will become source/drain regions. At this time,
The P+ layer 16a.

16b is mostly N1 layer 18a, 18b,
Due to the masking effect of the sidewall oxide film, a portion of the P+ layers 16a and 16b remain on the sides of the gate electrode 14. This P" layer 1
The widths of 6a and 16b were extremely short at 0.05 μm'Il'J.

From this point on, as in the normal process, the interlayer insulation is completed as shown in Figure 3(d). Deposition of 119, formation of contact 1~hole, ARii! By depositing and patterning the lit layer 20, an N-channel MOS transistor is completed.

The MOS transistor thus formed is free from the adverse effects of impact ionization and has a threshold of 1.
IiIi! The pressure fluctuation was extremely small and the reliability was high. Further, although the series resistance of the device was slightly higher, it exhibited sufficient characteristics as a MOS transistor.

Note that the present invention is not limited to the embodiments described above. For example, the transistor is not necessarily limited to the MO8 structure, but may be a MrS structure using a gate insulating film instead of a gate oxide film, or may be roughly an MES structure. Also, the first conductivity type on the source side is high! 1
The one-time impurity region is formed because ion implantation is performed in a self-aligned manner, and it can be eliminated depending on the method of ion implantation. For example, the first conductivity type impurity may be ion-implanted only into the drain side using a focused ion beam or the like. Also, game 1-
The drain side boundary of the I pole may be as short as it is provided that it does not overlap the drain region. In addition, N-type Si is used as the substrate.
Of course, the present invention can be applied to a P-channel MOS transistor using a substrate. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the schematic structure of a MOS transistor according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing the potential distribution during operation of the MOS transistor, and FIG.
4 and 5, which are cross-sectional views showing the manufacturing process of the OS transistor, are characteristic diagrams showing the potential distribution during operation of a conventional MOS transistor, respectively. 11...P-type SiM board (first conductivity type semiconductor substrate)
, 12...Field oxide film, 13...Goo 1-oxide film, 14...=gate electrode, 16a, 16b
・P” layer (first conductivity type high concentration impurity 1jti31),
18a. 18b... Source/drain region (second conductivity type high concentration impurity region). Applicant's agent Patent attorney Takehiko Suzue Figure 1 1A

Claims (2)

[Claims] (1) A source/drain region of a second conductivity type formed separately in a semiconductor substrate of a first conductivity type, a gate electrode formed on a channel region between these source/drain regions, and the drain region. A first conductivity type high concentration impurity region having a higher impurity concentration than the substrate and having a width shorter than the mean free path of carriers is formed between the region and the channel region. semiconductor devices. (2) The boundary on the drain side of the gate electrode is located closer to the source than the boundary between the drain region and the first conductivity type high concentration impurity region.
1. Semiconductor device described in Section 1.