JPS628876B2 - - Google Patents
Info
- Publication number
- JPS628876B2 JPS628876B2 JP14394780A JP14394780A JPS628876B2 JP S628876 B2 JPS628876 B2 JP S628876B2 JP 14394780 A JP14394780 A JP 14394780A JP 14394780 A JP14394780 A JP 14394780A JP S628876 B2 JPS628876 B2 JP S628876B2
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- blocks
- data
- memory
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/34—Accessing multiple bits simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
Description
本発明はデータ書き込み時間の短縮化をはかつ
た不揮発性半導体メモリーに関する。
一般に、電荷補獲手段をゲート絶縁膜内にもつ
たIG−FET（絶縁ゲート型電界効果トランジス
タ）をメモリーセルとしたPROM
（Programmable Read Only Memory）におい
て、電荷捕獲手段としてのフローテイング・ゲー
トに電子を注入するつまりプログラムを行なう
時、メモリーセルのゲートとドレインにプログラ
ム電圧Ｖp（例えば25V）を印加するが、１つの
メモリーセルをプログラムするには通常50ミリ秒
程度の時間が必要である。ところで従来は、１ビ
ツトのデータを得るためのメモリー領域で、１つ
の番地毎にプログラムを行なつていたため4096ワ
ード×８ピツトのメモリーの場合、4096×50〔ｍ
ｓ〕＝204800≒3.4分となり、プログラムに多くの
時間を要した。
本発明は上記実情に鑑みてなされたもので、１
ビツトのデータを得るためのメモリー領域の２つ
以上の番地に同時にデータ書き込みが行なえるよ
うにすることにより、プログラム時間の短縮化を
はかつた不揮発性半導体メモリーを提供しようと
するものある。
以下図面を参照して本発明の一実施例を説明す
る。第１図において１はメモリーセル・アレイで
あり、このセル・アレイ１には行線２０，……、
列線３10，……，３1l，３2l，……３2l、メモリー
セル４10，……４1l，４20，……４2l等が設けられ
ている。行線２０，……の一端は行デコーダ５に
接続される。ブロツクＡの列線３10，……３1lの
一端はIG−FET６10，……６1lを介して端子７A
に接続され、この端子７AはIG−FET（負荷トラ
ンジスタ）８Aを介してプログラム電源Ｖp（例え
ば25V）に接続される。ブロツクＢの列線３20，
……３2lの一端はIG−FET６20，……６2lを介し
て端子７Bに接続され、この端子７BはIG−FET
８B（負荷トランジスタ）を介してプログラム電
源Ｖpに接続される。上記IG−FET６10，６20，
……６1l，６2lは列デコーダ１４の出力線１５10，
……１５1lで選択される。上記IG−FET８Aはブ
ロツクＡで指定されたメモリーセル（番地）にデ
ータ“１”を書き込むか“０”を書き込むかを決
めるためのものであり、IG−FET８Bはブロツク
Ｂで指定されたメモリーセル（番地）に“１”を
書き込むか“０”を書き込むかを決めるためのも
のである。即ち電位検出回路９は、供給される書
き込みデータの電位レベルに応じてIG−FET８
A，８Bのオン、オフ状態を決定する。また上記端
子７A，７Bは、データ読み出し時のみ使用される
IG−FET１０A，１０Bを介して端子１１に接続
される。IG−FET１０A，１０Bはアドレス入力
A0，０で制御される。上記端子１１に読み出
された１ビツトのデータは、IG−FET１２を介
してセンスアンプ及び出力バツフア回路１３に供
給される。上記IG−FET１２はデータ読み出し
信号Ｒ／で制御される。
上記第１図は、１ビツトのデータを得るメモリ
ー領域の２つの番地のデータを、同時にプログラ
ムする際の構成例である。このメモリーににおい
て通常のデータ読み出し時、ブロツクＡの列線
は、アドレス入力A0＝“１”の時列デコーダ１４
によつて１本が選択され、ブロツクＢの列線は、
アドレス入力A0＝“０”つまり０＝“１”の時
列デコーダ１４によつて１本が選択される。
一方本実施例の主旨は、A0＝“０”（０＝
“１”）及びA0＝“１”の２つの状態つまりブロツ
クＡ及びＢの２つの番地を同時にプログラムする
もので、ブロツクＡ，Ｂのそれぞれ１本、つまり
２本の列線が同時に選択され、その時選択された
行線との交点のメモリーセル２個が同時にプログ
ラムされる。具体的には、下記の第１表に示すよ
うに電位検出回路９への書き込みデータを、例え
ば０〔Ｖ〕、５〔Ｖ〕、10〔Ｖ〕、15〔Ｖ〕の４種
の電位に区別することにより、A0＝“０”（０
＝“１”）、A0＝“１”の２つの番地のデータを、
電位検出回路９の出力ｓ，ｔの電位で、IG−
FET８A，８Bをオン／オフすることで、その時
列デコーダ１４、行デコーダ５で選択された２つ
のメモリーセル（番地）を同時にプログラムす
る。ただし、ここではフローテイングゲートをゲ
ート絶縁膜内にもつIG−FETをメモリーセルと
するPROMを例にとつているから、このPROMの
何もしない状態つまりフローテイングゲートが中
性の時を“０”の状態、フローテイングゲートに
電子が注入された状態を“１”とする。そしてフ
ローテイングゲートに電子を注入することは、メ
モリーセルのゲート及びドレインにプログラム電
圧ＶP（例えば25V）を印加することにより行な
う。
The present invention relates to a nonvolatile semiconductor memory that reduces data writing time. Generally, PROM uses an IG-FET (insulated gate field effect transistor) as a memory cell, which has a charge capture means in the gate insulating film.
(Programmable Read Only Memory), when injecting electrons into the floating gate as a charge trapping means, i.e., performing programming, a programming voltage V p (for example, 25 V) is applied to the gate and drain of the memory cell. Programming a memory cell typically takes about 50 milliseconds. By the way, in the past, programming was performed for each address in the memory area for obtaining 1 bit of data, so in the case of a memory of 4096 words x 8 pits, the memory area was 4096 x 50 m.
s]=204800≒3.4 minutes, and the program required a lot of time. The present invention has been made in view of the above circumstances, and includes:
Some attempts have been made to provide a nonvolatile semiconductor memory in which programming time can be shortened by allowing data to be simultaneously written to two or more addresses in a memory area for obtaining bit data. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a memory cell array, and this cell array 1 has row lines 2 0 , . . .
Column lines 310 ,..., 31l , 32l,... 32l , memory cells 410 ,... 41l , 420 ,... 42l, etc. are provided. One end of the row lines 2 0 , . . . is connected to the row decoder 5 . One end of column line 310 ,... 31l of block A is connected to terminal 7A via IG- FET610 ,... 61l .
This terminal 7A is connected to a program power supply Vp (for example, 25V) via an IG-FET (load transistor) 8A . Block B column line 3 20 ,
...3 2l one end is connected to terminal 7 B via IG-FET6 20 , ...6 2l , and this terminal 7 B is connected to IG-FET6 20 , ...6 2l
8 B (load transistor) to the program power supply V p . The above IG-FET6 10 , 6 20 ,
...6 1l and 6 2l are the output lines 15 10 of the column decoder 14,
...15 Selected by 1l . The above IG- FET8A is used to decide whether to write data "1" or "0" to the memory cell (address) specified by block A, and IG- FET8B is used to decide whether to write data "1" or "0" to the memory cell (address) specified by block B. This is to decide whether to write "1" or "0" to the memory cell (address). That is, the potential detection circuit 9 detects the IG-FET 8 according to the potential level of the supplied write data.
Determine the on/off state of A and 8 B. Also, the above terminals 7 A and 7 B are used only when reading data.
It is connected to the terminal 11 via IG- FET10A and 10B . IG- FET10A , 10B is address input
Controlled by A 0,0 . The 1-bit data read to the terminal 11 is supplied to the sense amplifier and output buffer circuit 13 via the IG-FET 12. The IG-FET 12 is controlled by a data read signal R/. The above-mentioned FIG. 1 shows an example of a configuration in which data at two addresses in a memory area from which 1-bit data is obtained is simultaneously programmed. When reading data normally in this memory, the column line of block A is connected to the time column decoder 14 with address input A 0 = “1”.
One line is selected by , and the column line of block B is
One line is selected by the time sequence decoder 14 with address input A 0 =“0”, that is, 0 =“1”. On the other hand, the gist of this embodiment is that A 0 = “0” ( 0 =
This program simultaneously programs the two states of ``1'' and A 0 = ``1'', that is, the two addresses of blocks A and B, and one column line each of blocks A and B, that is, two column lines, are selected at the same time. , two memory cells at the intersection with the row line selected at that time are simultaneously programmed. Specifically, as shown in Table 1 below, the data written to the potential detection circuit 9 is set to four potentials, for example, 0 [V], 5 [V], 10 [V], and 15 [V]. By distinguishing, A 0 = “0” ( 0
= “1”) and A 0 = “1”,
At the potentials of the outputs s and t of the potential detection circuit 9, IG-
By turning on/off FETs 8 A and 8 B , two memory cells (addresses) selected by the column decoder 14 and row decoder 5 are simultaneously programmed. However, since we are taking as an example a PROM whose memory cell is an IG-FET with a floating gate in the gate insulating film, the state where this PROM does nothing, that is, when the floating gate is neutral, is "0". ” state, in which electrons are injected into the floating gate, is defined as “1”. Injecting electrons into the floating gate is performed by applying a programming voltage V P (for example, 25 V) to the gate and drain of the memory cell.
【表】
第１図において、書き込みデータの電位レベル
が0Vの時、ｓ＝“０”、ｔ＝“０”を電位検出回路
９の出力とする。この時IG−FET８A，８Bはオ
フのままであるから、列線にはプログラム電圧Ｖ
pが印加されず、従つて書き込みは行なわれず、
メモリーセルは“０”のままである。このこと
は、ブロツクＡ，Ｂで指定されたメモリーセル
（番地）に“０”が書き込まれたことと等価であ
る。書き込みデータが５Ｖになつた場合は、ｓ＝
“１”、ｔ＝“０”となつてIG−FET８Bのみがオ
ンし、いま列デコーダ１４の出力線１５108行デ
コーダ５の行線２０が選択されていれば、メモリ
ーセル４20のゲート及びドレインにプログラム電
圧Ｖpが印加され、プログラムが行なわれてメモ
リーセル４20は“１”の状態になる。この時IG−
FET８Aはオフで、メモリーセル４10は“０”の
ままだから、該セルに“０”書き込みが高なわれ
たことと等価である。以下同様に書き込みデータ
が10Vの時、ｓ＝“０”、ｔ＝“１”となつてIG−
FET８Aのみがオンし、この時行線２０、出力線
１５10が選択されていれば、メモリーセル４10に
“１”が書き込まれる。書き込みデータが１５Ｖ
の場合は、IG−FET８A，８Bが共にオンし、出
力線１５10、行線２０が選択されればメモリーセ
ル４10，４20に“１”が書き込まれるものであ
る。
第２図は電位検出回路９の一例を示し、下記の
第２表にこの回路の各点の電位レベルを示す。但
しこの第２表で、“０”はすべて０〔Ｖ〕を示す
が、“１”は端子ｘ〜ｚについては電源Ｖc（例え
ば5V）レベル、端子ｓ，ｔについてはＶp（例え
ば25V）レベルに対応する。[Table] In FIG. 1, when the potential level of the write data is 0V, s=“0” and t=“0” are the outputs of the potential detection circuit 9. At this time, IG-FETs 8 A and 8 B remain off, so the program voltage V is applied to the column line.
p is not applied, so no writing takes place,
The memory cell remains at "0". This is equivalent to writing "0" into the memory cells (addresses) designated by blocks A and B. If the write data becomes 5V, s=
“1”, t=“0”, and only IG-FET 8 B is turned on, and if the output line 15 of the column decoder 14 and the row line 20 of the row decoder 5 are currently selected, then the memory cell 4 20 A programming voltage V p is applied to the gate and drain, programming is performed, and the memory cell 420 becomes a "1" state. At this time IG-
Since FET 8A is off and memory cell 410 remains at "0", this is equivalent to writing "0" to that cell. Similarly, when the write data is 10V, s = "0", t = "1", and IG-
If only FET 8 A is turned on and row line 2 0 and output line 15 10 are selected at this time, “1” is written in memory cell 4 10 . Write data is 15V
In this case, if both IG-FETs 8A and 8B are turned on and the output line 1510 and row line 20 are selected, "1" is written into the memory cells 410 and 420 . FIG. 2 shows an example of the potential detection circuit 9, and Table 2 below shows potential levels at each point of this circuit. However, in this Table 2, all "0" indicate 0 [V], but "1" indicates the power supply V c (for example, 5V) level for terminals x to z, and V p (for example, 25V) for terminals s and t. ) corresponding to the level.
【表】
第２図の電位検出回路において２１〜２３は基
準電圧発生部であり、例えばその出力端O1には
２Ｖが、O2には７Ｖが、O3には１２Ｖが得られ
る。２４〜２６は電位検出部、２７〜３０はゲー
ト回路である。電位検出部２４〜２６は、基準電
位発生部の出力電圧と書き込みデータの電位レベ
ルを比較し、その結果でゲート回路を制御し、出
力ｓ，ｔのレベルを決める。例えば書き込みデー
タがOVの時、デプレツシヨン型トランジスタ３
１の抵抗値はトランジスタ３２のそれと比較して
大であり、エンハンスメント型トランジスタ３３
はオン方向、トランジスタ３４はオフ方向にあ
る。書き込み信号／Ｗの供給でトランジスタ３
５がオン状態になると出力端O4，O5のレベルが
決まり、この場合O4は“０”、O5が“１”とな
る。この“１”でゲート回路２７のトランジスタ
３６と、ゲート回路２８のトランジスタ３７がオ
ンし、出力ｓ，ｔは共に“０”となり、第２表の
結果と一致する。書き込みデータの電位レベルが
他の値をとつた時の動作も第２表の結果と一致す
る。
第３図は電位検出回路の他の例を示すもので、
この場合は基準電圧発生部４１から、電位検出部
４２に例えば７Ｖ、電位検出部４３に12V、検出
部４４に１８Ｖ、検出部４５に２１Ｖの基準電圧
を与え、書き込みデータの電位レベルとの比較を
行なうようにしている。この回路は、書き込みデ
ータが０〜5Vの間に従来通り、入力アドレスに
より指定された１つのメモリーセルをプログラム
するが、書き込みデータが１０Ｖ，１５Ｖ，２０
Ｖ，２５Ｖの４つの状態になると、２つの番地を
同時にプログラムするものである。この時の回路
動作は下記の第３表に示される。[Table] In the potential detection circuit of FIG. 2, 21 to 23 are reference voltage generating sections, and for example, 2V is obtained at the output terminal O1 , 7V at O2 , and 12V at O3 . Reference numerals 24 to 26 are potential detection sections, and 27 to 30 are gate circuits. The potential detection units 24 to 26 compare the output voltage of the reference potential generation unit and the potential level of the write data, control the gate circuit based on the result, and determine the levels of the outputs s and t. For example, when the write data is OV, the depletion type transistor 3
The resistance value of the transistor 1 is larger than that of the transistor 32, and the resistance value of the enhancement type transistor 33 is larger than that of the transistor 32.
is in the on direction, and transistor 34 is in the off direction. Transistor 3 by supplying write signal /W
5 is turned on, the levels of output terminals O 4 and O 5 are determined, and in this case, O 4 becomes "0" and O 5 becomes "1". This "1" turns on the transistor 36 of the gate circuit 27 and the transistor 37 of the gate circuit 28, and the outputs s and t both become "0", which agrees with the results in Table 2. The operation when the potential level of the write data takes other values also matches the results in Table 2. Figure 3 shows another example of the potential detection circuit.
In this case, the reference voltage generation section 41 applies a reference voltage of, for example, 7V to the potential detection section 42, 12V to the potential detection section 43, 18V to the detection section 44, and 21V to the detection section 45, and compares it with the potential level of the written data. I try to do this. This circuit programs one memory cell designated by an input address as before when write data is 0 to 5V, but when write data is 10V, 15V, 20V,
When the four states of V and 25V are reached, two addresses are programmed at the same time. The circuit operation at this time is shown in Table 3 below.
【表】
なお上記実施例では、メモリー領域を２つのブ
ロツクに分割してプログラムに要する時間を従来
の1/2としたが、メモリー領域をｎ個に分割すれ
ば、プログラム所要時間を１／ｎにできる等、本
発明は実施例に限られず種々の応用が可能であ
る。
以上説明した如く本発明によれば、複数の番地
を同時にプログラムできるため、プログラム時間
が短縮される不揮発性半導体メモリーが提供でき
るものである。[Table] In the above embodiment, the memory area is divided into two blocks to reduce the time required for programming to 1/2 of the conventional time. However, if the memory area is divided into n blocks, the time required for programming is reduced to 1/n. The present invention is not limited to the embodiments and can be applied in various ways. As described above, according to the present invention, it is possible to provide a non-volatile semiconductor memory in which a plurality of addresses can be programmed simultaneously, thereby reducing the programming time.
第１図は本発明の一実施例を示す回路図、第２
図は同回路の一部詳細回路図、第３図は同回路の
他の例を示す回路図である。
１……メモリーセル・アレイ、２０……行線、
３10〜３2l……列線、４10〜４2l……メモリーセ
ル、５……行デコーダ、６10〜６2l……列選択ゲ
ート、８A，８B……ブロツク選択ゲート、９……
電位検出回路、１４……列デコーダ、Ａ，Ｂ……
ブロツク。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a partial detailed circuit diagram of the same circuit, and FIG. 3 is a circuit diagram showing another example of the same circuit. 1...Memory cell array, 2 0 ...Row line,
3 10 - 3 2l ... Column line, 4 10 - 4 2l ... Memory cell, 5 ... Row decoder, 6 10 - 6 2l ... Column selection gate, 8 A , 8 B ... Block selection gate, 9... …
Potential detection circuit, 14... Column decoder, A, B...
Block.
Claims (1)
の出力がＮ個のビツトである不揮発性半導体メモ
リーにおいて、前記出力１ビツトを得るための構
成は、電荷捕獲手段をゲート絶縁膜内にもつた
IG−FETをメモリーセルとして出力１ビツトの
データを得るメモリー領域の列線を複数のブロツ
クに分割し、各ブロツク内の１つのメモリーセル
にそれぞれデータを書き込むために前記各ブロツ
ク内で同時に選択されたメモリーセルのゲートと
ドレインに、論理データ“１”を書き込むか論理
データ“０”を書き込むかに応じて、各ブロツク
に対応して設けられ書き込みデータに応じてスイ
ツチング制御される負荷トランジスタをそれぞれ
制御することによつてプログラム電圧を選択印加
する電圧印加手段を具備したことを特徴とする不
揮発性半導体メモリー。 ２ 前記ブロツクの数はｎ個であり、前記電圧印
加手段は、前記各ブロツクにそれぞれプログラム
電源電圧を与えるｎ個のスイツチ素子を有し、か
つ2n個の電位レベルをもつ入力信号のレベルに
応じて前記各スイツチ素子を制御する電位検出回
路を有することを特徴とする特許請求の範囲第１
項に記載の不揮発性半導体メモリー。[Claims] In a nonvolatile semiconductor memory having a configuration of 1 M words x N bits (M and N are natural numbers), the output is N bits, and the configuration for obtaining the 1 bit output includes charge trapping means. If there is a problem in the gate insulating film,
The column lines in the memory area are divided into multiple blocks to obtain output 1-bit data using the IG-FET as a memory cell, and in order to write data to one memory cell in each block, the lines are selected simultaneously in each block. Depending on whether logic data "1" or logic data "0" is written to the gate and drain of the memory cell, a load transistor is provided corresponding to each block and is switched and controlled according to the write data. 1. A nonvolatile semiconductor memory characterized by comprising voltage application means for selectively applying a program voltage through control. 2. The number of the blocks is n, and the voltage application means has n switch elements that respectively apply a program power supply voltage to each of the blocks, and the voltage application means applies a program power supply voltage to each of the blocks according to the level of an input signal having 2n potential levels. Claim 1 further comprises a potential detection circuit for controlling each of the switch elements.
Non-volatile semiconductor memory as described in .
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14394780A JPS5769583A (en) | 1980-10-15 | 1980-10-15 | Non_volatile semiconductor memory |
| EP81304660A EP0050005B1 (en) | 1980-10-15 | 1981-10-07 | Semiconductor memory with improved data programming time |
| DE8181304660T DE3176751D1 (en) | 1980-10-15 | 1981-10-07 | Semiconductor memory with improved data programming time |
| EP19860201618 EP0214705B1 (en) | 1980-10-15 | 1981-10-07 | Semiconductor memory with improvend data programming time |
| DE8686201618T DE3177270D1 (en) | 1980-10-15 | 1981-10-07 | SEMICONDUCTOR MEMORY WITH DATA PROGRAMMING TIME. |
| US06/310,822 US4477884A (en) | 1980-10-15 | 1981-10-13 | Semiconductor memory with improved data programming time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14394780A JPS5769583A (en) | 1980-10-15 | 1980-10-15 | Non_volatile semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5769583A JPS5769583A (en) | 1982-04-28 |
| JPS628876B2 true JPS628876B2 (en) | 1987-02-25 |
Family
ID=15350745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14394780A Granted JPS5769583A (en) | 1980-10-15 | 1980-10-15 | Non_volatile semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5769583A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5136546A (en) * | 1984-09-26 | 1992-08-04 | Hitachi, Ltd. | Semiconductor memory |
| JPS6180597A (en) * | 1984-09-26 | 1986-04-24 | Hitachi Ltd | Semiconductor memory device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54107638A (en) * | 1978-02-10 | 1979-08-23 | Sanyo Electric Co Ltd | Memory data readout circuit in semiconductor memory unit |
| JPS54110742A (en) * | 1978-02-17 | 1979-08-30 | Sanyo Electric Co Ltd | Nonvolatile semiconductor memory device |
-
1980
- 1980-10-15 JP JP14394780A patent/JPS5769583A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54107638A (en) * | 1978-02-10 | 1979-08-23 | Sanyo Electric Co Ltd | Memory data readout circuit in semiconductor memory unit |
| JPS54110742A (en) * | 1978-02-17 | 1979-08-30 | Sanyo Electric Co Ltd | Nonvolatile semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5769583A (en) | 1982-04-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4958317A (en) | Nonvolatile semiconductor memory device and a writing method using electron tunneling | |
| US5337281A (en) | Non-volatile semiconductor memory device in which data can be erased on a block basis and method of erasing data on a block basis in non-volatile semiconductor memory device | |
| US5097152A (en) | Buffer circuit used in a semiconductor device operating by different supply potentials and method of operating the same | |
| US5917753A (en) | Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells | |
| US7355903B2 (en) | Semiconductor device including memory cells and current limiter | |
| JPH08279297A (en) | Nonvolatile semiconductor memory of nand structure and its programming method | |
| US4543647A (en) | Electrically programmable non-volatile semiconductor memory device | |
| US5544117A (en) | Non-volatile semiconductor memory device with improved collective erasing operation | |
| US4805151A (en) | Nonvolatile semiconductor memory device | |
| US6160738A (en) | Nonvolatile semiconductor memory system | |
| JPS62120700A (en) | Semiconductor memory device | |
| US4870618A (en) | Semiconductor memory equipped with test circuit for testing data holding characteristic during data programming period | |
| KR900013522A (en) | Semiconductor nonvolatile memory and information processing system using the same | |
| JP2591740B2 (en) | Nonvolatile programmable semiconductor memory | |
| JP3693504B2 (en) | Memory device | |
| JP3998908B2 (en) | Nonvolatile memory device | |
| US5278786A (en) | Non-volatile semiconductor memory device having an area responsive to writing allowance signal | |
| US4751678A (en) | Erase circuit for CMOS EEPROM | |
| JP2725564B2 (en) | Semiconductor memory device and data writing method thereof | |
| JPS628877B2 (en) | ||
| JPS628876B2 (en) | ||
| US4827451A (en) | Safety device for the programming of an electrically programmable non-volatile memory | |
| JPH05128877A (en) | Nonvolatile semiconductor memory device | |
| JP3307299B2 (en) | Flash memory device | |
| KR970051328A (en) | Nonvolatile Memory with Separate Source Lines |