JPS54142031A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS54142031A
JPS54142031A JP5085678A JP5085678A JPS54142031A JP S54142031 A JPS54142031 A JP S54142031A JP 5085678 A JP5085678 A JP 5085678A JP 5085678 A JP5085678 A JP 5085678A JP S54142031 A JPS54142031 A JP S54142031A
Authority
JP
Japan
Prior art keywords
line
memory cell
read
write selection
earth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5085678A
Other languages
Japanese (ja)
Inventor
Tsutomu Iima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5085678A priority Critical patent/JPS54142031A/en
Publication of JPS54142031A publication Critical patent/JPS54142031A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To reduce the occupied area of the memory cell and to increase the degree of integration by utilizing the read or write selection line of the adjacent memory cell as the power line of the earth or the like. CONSTITUTION:Both the read and write selection lines are always ''0'' when the memory cell is not selected, and thus the read or write selection line of the nonselected memory cell which is adjacent to the selected memory cell can be utilized as the earth line. In case the information written to node 12 of the memory circuit is ''1'', FETM12 also conducts. As a result, the charge of data line A leaks out to R2 of the 2nd line memory cell prescribed by read and write selection lines R2 and W2 via FETM12 and M13. As described above, both the read and write selection lines of the nonselected line are always ''0'' possessing the path leading to the earth pontential via MOSFET of line decoder circuit 4. Thus, the charge of data line A leaks out to the earth potential and then turns to level ''0''.
JP5085678A 1978-04-27 1978-04-27 Memory circuit Pending JPS54142031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5085678A JPS54142031A (en) 1978-04-27 1978-04-27 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5085678A JPS54142031A (en) 1978-04-27 1978-04-27 Memory circuit

Publications (1)

Publication Number Publication Date
JPS54142031A true JPS54142031A (en) 1979-11-05

Family

ID=12870356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5085678A Pending JPS54142031A (en) 1978-04-27 1978-04-27 Memory circuit

Country Status (1)

Country Link
JP (1) JPS54142031A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61120395A (en) * 1984-11-14 1986-06-07 Toshiba Corp Semi conductor storage device
JPS63138593A (en) * 1986-11-28 1988-06-10 Mitsubishi Electric Corp Semiconductor memory device
WO2011096264A1 (en) * 2010-02-05 2011-08-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61120395A (en) * 1984-11-14 1986-06-07 Toshiba Corp Semi conductor storage device
JPS63138593A (en) * 1986-11-28 1988-06-10 Mitsubishi Electric Corp Semiconductor memory device
JPH0568797B2 (en) * 1986-11-28 1993-09-29 Mitsubishi Electric Corp
WO2011096264A1 (en) * 2010-02-05 2011-08-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device
JP2011181167A (en) * 2010-02-05 2011-09-15 Semiconductor Energy Lab Co Ltd Semiconductor device and method of driving semiconductor device
KR20120124471A (en) * 2010-02-05 2012-11-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method of driving semiconductor device
JP2015135719A (en) * 2010-02-05 2015-07-27 株式会社半導体エネルギー研究所 Semiconductor device

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